Function Layout, Global Variable Layout and Pooled Constants Layout Reordering

src/IceTargetLoweringX86BaseImpl.h

 //===- subzero/src/IceTargetLoweringX86BaseImpl.h - x86 lowering -*- C++ -*-==//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 //
 // This file implements the TargetLoweringX86Base class, which
@@ skipping 3384 matching lines @@
     Context.insert(
         InstFakeUse::create(Func, Context.getLastInserted()->getDest()));
     return;
   }
   case Intrinsics::AtomicRMW:
     if (!Intrinsics::isMemoryOrderValid(
             ID, getConstantMemoryOrder(Instr->getArg(3)))) {
       Func->setError("Unexpected memory ordering for AtomicRMW");
       return;
     }
-    lowerAtomicRMW(Instr->getDest(),
-                   static_cast<uint32_t>(llvm::cast<ConstantInteger32>(
-                                             Instr->getArg(0))->getValue()),
-                   Instr->getArg(1), Instr->getArg(2));
+    lowerAtomicRMW(
+        Instr->getDest(),
+        static_cast<uint32_t>(
+            llvm::cast<ConstantInteger32>(Instr->getArg(0))->getValue()),
+        Instr->getArg(1), Instr->getArg(2));
     return;
   case Intrinsics::AtomicStore: {
     if (!Intrinsics::isMemoryOrderValid(
             ID, getConstantMemoryOrder(Instr->getArg(2)))) {
       Func->setError("Unexpected memory ordering for AtomicStore");
       return;
     }
     // We require the memory address to be naturally aligned.
     // Given that is the case, then normal stores are atomic.
     // Add a fence after the store to make it visible.
@@ skipping 1984 matching lines @@
       // The offset of this mem operand should be blinded or pooled
       Ctx->statsUpdateRPImms();
       if (Ctx->getFlags().getRandomizeAndPoolImmediatesOption() ==
           RPI_Randomize) {
         // blind the constant offset
         // FROM:
         //  offset[base, index, shift]
         // TO:
         //  insert: lea offset+cookie[base], RegTemp
         //  => -cookie[RegTemp, index, shift]
-        uint32_t Value = llvm::dyn_cast<ConstantInteger32>(
-                             MemOperand->getOffset())->getValue();
+        uint32_t Value =
+            llvm::dyn_cast<ConstantInteger32>(MemOperand->getOffset())
+                ->getValue();
         uint32_t Cookie = Ctx->getRandomizationCookie();
         Constant *Mask1 = Ctx->getConstantInt(
             MemOperand->getOffset()->getType(), Cookie + Value);
         Constant *Mask2 =
             Ctx->getConstantInt(MemOperand->getOffset()->getType(), 0 - Cookie);
 
         OperandX8632Mem *TempMemOperand = OperandX8632Mem::create(
             Func, MemOperand->getType(), MemOperand->getBase(), Mask1);
         // If we have already assigned a physical register, we must come from
         // advancedPhiLowering()=>lowerAssign(). In this case we should reuse
@@ skipping 69 matching lines @@
   }
   // the offset is not eligible for blinding or pooling, return the original
   // mem operand
   return MemOperand;
 }
 
 } // end of namespace X86Internal
 } // end of namespace Ice
 
 #endif // SUBZERO_SRC_ICETARGETLOWERINGX86BASEIMPL_H