| Index: runtime/vm/intermediate_language_x64.cc
|
| diff --git a/runtime/vm/intermediate_language_x64.cc b/runtime/vm/intermediate_language_x64.cc
|
| index bf7cb827706b97068cc1e39ad7a36baeeaf13580..5a92da3aad2895a078ef9ad5a8ba04c4798bf70c 100644
|
| --- a/runtime/vm/intermediate_language_x64.cc
|
| +++ b/runtime/vm/intermediate_language_x64.cc
|
| @@ -2402,40 +2402,6 @@ void DoubleToDoubleInstr::EmitNativeCode(FlowGraphCompiler* compiler) {
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| }
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|
|
|
|
| -LocationSummary* InvokeMathCFunctionInstr::MakeLocationSummary() const {
|
| - // Calling convention on x64 uses XMM0 and XMM1 to pass the first two
|
| - // double arguments and XMM0 to return the result. Unfortunately
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| - // currently we can't specify these registers because ParallelMoveResolver
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| - // assumes that XMM0 is free at all times.
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| - // TODO(vegorov): allow XMM0 to be used.
|
| - ASSERT((InputCount() == 1) || (InputCount() == 2));
|
| - const intptr_t kNumTemps = 0;
|
| - LocationSummary* result =
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| - new LocationSummary(InputCount(), kNumTemps, LocationSummary::kCall);
|
| - result->set_in(0, Location::FpuRegisterLocation(XMM1, Location::kDouble));
|
| - if (InputCount() == 2) {
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| - result->set_in(1, Location::FpuRegisterLocation(XMM2, Location::kDouble));
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| - }
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| - result->set_out(Location::FpuRegisterLocation(XMM1, Location::kDouble));
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| - return result;
|
| -}
|
| -
|
| -
|
| -void InvokeMathCFunctionInstr::EmitNativeCode(FlowGraphCompiler* compiler) {
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| - ASSERT(locs()->in(0).fpu_reg() == XMM1);
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| - __ enter(Immediate(0));
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| - __ ReserveAlignedFrameSpace(kDoubleSize * InputCount());
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| - __ movaps(XMM0, locs()->in(0).fpu_reg());
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| - if (InputCount() == 2) {
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| - ASSERT(locs()->in(1).fpu_reg() == XMM2);
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| - __ movaps(XMM1, locs()->in(1).fpu_reg());
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| - }
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| - __ CallRuntime(TargetFunction());
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| - __ movaps(locs()->out().fpu_reg(), XMM0);
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| - __ leave();
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| -}
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| -
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| -
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| LocationSummary* PolymorphicInstanceCallInstr::MakeLocationSummary() const {
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| return MakeCallSummary();
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| }
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|
|