Extracts an TargetX86Base target which will be used as the common X86{32,64} implementation.

src/IceTargetLoweringX86BaseImpl.h

-//===- subzero/src/IceTargetLoweringX8632.cpp - x86-32 lowering -----------===//
+//===- subzero/src/IceTargetLoweringX86BaseImpl.h - x86 lowering *- C++ -*-===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 //
-// This file implements the TargetLoweringX8632 class, which
+// This file implements the TargetLoweringX86Base class, which
 // consists almost entirely of the lowering sequence for each
 // high-level instruction.
 //
 //===----------------------------------------------------------------------===//
 
+#ifndef SUBZERO_SRC_ICETARGETLOWERINGX86BASEIMPL_H
+#define SUBZERO_SRC_ICETARGETLOWERINGX86BASEIMPL_H
+
 #include "llvm/Support/MathExtras.h"
 
 #include "IceCfg.h"
 #include "IceCfgNode.h"
 #include "IceClFlags.h"
 #include "IceDefs.h"
 #include "IceELFObjectWriter.h"
 #include "IceGlobalInits.h"
 #include "IceInstX8632.h"
 #include "IceLiveness.h"
 #include "IceOperand.h"
 #include "IceRegistersX8632.h"
 #include "IceTargetLoweringX8632.def"
 #include "IceTargetLoweringX8632.h"
 #include "IceUtils.h"
 
 namespace Ice {
-
-namespace {
-
-// The following table summarizes the logic for lowering the fcmp
-// instruction.  There is one table entry for each of the 16 conditions.
-//
-// The first four columns describe the case when the operands are
-// floating point scalar values.  A comment in lowerFcmp() describes the
-// lowering template.  In the most general case, there is a compare
-// followed by two conditional branches, because some fcmp conditions
-// don't map to a single x86 conditional branch.  However, in many cases
-// it is possible to swap the operands in the comparison and have a
-// single conditional branch.  Since it's quite tedious to validate the
-// table by hand, good execution tests are helpful.
-//
-// The last two columns describe the case when the operands are vectors
-// of floating point values.  For most fcmp conditions, there is a clear
-// mapping to a single x86 cmpps instruction variant.  Some fcmp
-// conditions require special code to handle and these are marked in the
-// table with a Cmpps_Invalid predicate.
-const struct TableFcmp_ {
-  uint32_t Default;
-  bool SwapScalarOperands;
-  CondX86::BrCond C1, C2;
-  bool SwapVectorOperands;
-  CondX86::CmppsCond Predicate;
-} TableFcmp[] = {
-#define X(val, dflt, swapS, C1, C2, swapV, pred)                               \
-  { dflt, swapS, CondX86::C1, CondX86::C2, swapV, CondX86::pred }              \
-  ,
-    FCMPX8632_TABLE
-#undef X
-};
-const size_t TableFcmpSize = llvm::array_lengthof(TableFcmp);
-
-// The following table summarizes the logic for lowering the icmp instruction
-// for i32 and narrower types.  Each icmp condition has a clear mapping to an
-// x86 conditional branch instruction.
-
-const struct TableIcmp32_ {
-  CondX86::BrCond Mapping;
-} TableIcmp32[] = {
-#define X(val, C_32, C1_64, C2_64, C3_64)                                      \
-  { CondX86::C_32 }                                                            \
-  ,
-    ICMPX8632_TABLE
-#undef X
-};
-const size_t TableIcmp32Size = llvm::array_lengthof(TableIcmp32);
-
-// The following table summarizes the logic for lowering the icmp instruction
-// for the i64 type.  For Eq and Ne, two separate 32-bit comparisons and
-// conditional branches are needed.  For the other conditions, three separate
-// conditional branches are needed.
-const struct TableIcmp64_ {
-  CondX86::BrCond C1, C2, C3;
-} TableIcmp64[] = {
-#define X(val, C_32, C1_64, C2_64, C3_64)                                      \
-  { CondX86::C1_64, CondX86::C2_64, CondX86::C3_64 }                           \
-  ,
-    ICMPX8632_TABLE
-#undef X
-};
-const size_t TableIcmp64Size = llvm::array_lengthof(TableIcmp64);
-
-CondX86::BrCond getIcmp32Mapping(InstIcmp::ICond Cond) {
-  size_t Index = static_cast<size_t>(Cond);
-  assert(Index < TableIcmp32Size);
-  return TableIcmp32[Index].Mapping;
-}
-
-const struct TableTypeX8632Attributes_ {
-  Type InVectorElementType;
-} TableTypeX8632Attributes[] = {
-#define X(tag, elementty, cvt, sdss, pack, width, fld)                         \
-  { elementty }                                                                \
-  ,
-    ICETYPEX8632_TABLE
-#undef X
-};
-const size_t TableTypeX8632AttributesSize =
-    llvm::array_lengthof(TableTypeX8632Attributes);
-
-// Return the type which the elements of the vector have in the X86
-// representation of the vector.
-Type getInVectorElementType(Type Ty) {
-  assert(isVectorType(Ty));
-  size_t Index = static_cast<size_t>(Ty);
-  (void)Index;
-  assert(Index < TableTypeX8632AttributesSize);
-  return TableTypeX8632Attributes[Ty].InVectorElementType;
-}
-
-// The maximum number of arguments to pass in XMM registers
-const uint32_t X86_MAX_XMM_ARGS = 4;
-// The number of bits in a byte
-const uint32_t X86_CHAR_BIT = 8;
-// Stack alignment
-const uint32_t X86_STACK_ALIGNMENT_BYTES = 16;
-// Size of the return address on the stack
-const uint32_t X86_RET_IP_SIZE_BYTES = 4;
-// The number of different NOP instructions
-const uint32_t X86_NUM_NOP_VARIANTS = 5;
-
-// Value is in bytes. Return Value adjusted to the next highest multiple
-// of the stack alignment.
-uint32_t applyStackAlignment(uint32_t Value) {
-  return Utils::applyAlignment(Value, X86_STACK_ALIGNMENT_BYTES);
-}
-
-// In some cases, there are x-macros tables for both high-level and
-// low-level instructions/operands that use the same enum key value.
-// The tables are kept separate to maintain a proper separation
-// between abstraction layers.  There is a risk that the tables could
-// get out of sync if enum values are reordered or if entries are
-// added or deleted.  The following dummy namespaces use
-// static_asserts to ensure everything is kept in sync.
-
-// Validate the enum values in FCMPX8632_TABLE.
-namespace dummy1 {
-// Define a temporary set of enum values based on low-level table
-// entries.
-enum _tmp_enum {
-#define X(val, dflt, swapS, C1, C2, swapV, pred) _tmp_##val,
-  FCMPX8632_TABLE
-#undef X
-      _num
-};
-// Define a set of constants based on high-level table entries.
-#define X(tag, str) static const int _table1_##tag = InstFcmp::tag;
-ICEINSTFCMP_TABLE
-#undef X
-// Define a set of constants based on low-level table entries, and
-// ensure the table entry keys are consistent.
-#define X(val, dflt, swapS, C1, C2, swapV, pred)                               \
-  static const int _table2_##val = _tmp_##val;                                 \
-  static_assert(                                                               \
-      _table1_##val == _table2_##val,                                          \
-      "Inconsistency between FCMPX8632_TABLE and ICEINSTFCMP_TABLE");
-FCMPX8632_TABLE
-#undef X
-// Repeat the static asserts with respect to the high-level table
-// entries in case the high-level table has extra entries.
-#define X(tag, str)                                                            \
-  static_assert(                                                               \
-      _table1_##tag == _table2_##tag,                                          \
-      "Inconsistency between FCMPX8632_TABLE and ICEINSTFCMP_TABLE");
-ICEINSTFCMP_TABLE
-#undef X
-} // end of namespace dummy1
-
-// Validate the enum values in ICMPX8632_TABLE.
-namespace dummy2 {
-// Define a temporary set of enum values based on low-level table
-// entries.
-enum _tmp_enum {
-#define X(val, C_32, C1_64, C2_64, C3_64) _tmp_##val,
-  ICMPX8632_TABLE
-#undef X
-      _num
-};
-// Define a set of constants based on high-level table entries.
-#define X(tag, str) static const int _table1_##tag = InstIcmp::tag;
-ICEINSTICMP_TABLE
-#undef X
-// Define a set of constants based on low-level table entries, and
-// ensure the table entry keys are consistent.
-#define X(val, C_32, C1_64, C2_64, C3_64)                                      \
-  static const int _table2_##val = _tmp_##val;                                 \
-  static_assert(                                                               \
-      _table1_##val == _table2_##val,                                          \
-      "Inconsistency between ICMPX8632_TABLE and ICEINSTICMP_TABLE");
-ICMPX8632_TABLE
-#undef X
-// Repeat the static asserts with respect to the high-level table
-// entries in case the high-level table has extra entries.
-#define X(tag, str)                                                            \
-  static_assert(                                                               \
-      _table1_##tag == _table2_##tag,                                          \
-      "Inconsistency between ICMPX8632_TABLE and ICEINSTICMP_TABLE");
-ICEINSTICMP_TABLE
-#undef X
-} // end of namespace dummy2
-
-// Validate the enum values in ICETYPEX8632_TABLE.
-namespace dummy3 {
-// Define a temporary set of enum values based on low-level table
-// entries.
-enum _tmp_enum {
-#define X(tag, elementty, cvt, sdss, pack, width, fld) _tmp_##tag,
-  ICETYPEX8632_TABLE
-#undef X
-      _num
-};
-// Define a set of constants based on high-level table entries.
-#define X(tag, size, align, elts, elty, str)                                   \
-  static const int _table1_##tag = tag;
-ICETYPE_TABLE
-#undef X
-// Define a set of constants based on low-level table entries, and
-// ensure the table entry keys are consistent.
-#define X(tag, elementty, cvt, sdss, pack, width, fld)                         \
-  static const int _table2_##tag = _tmp_##tag;                                 \
-  static_assert(_table1_##tag == _table2_##tag,                                \
-                "Inconsistency between ICETYPEX8632_TABLE and ICETYPE_TABLE");
-ICETYPEX8632_TABLE
-#undef X
-// Repeat the static asserts with respect to the high-level table
-// entries in case the high-level table has extra entries.
-#define X(tag, size, align, elts, elty, str)                                   \
-  static_assert(_table1_##tag == _table2_##tag,                                \
-                "Inconsistency between ICETYPEX8632_TABLE and ICETYPE_TABLE");
-ICETYPE_TABLE
-#undef X
-} // end of namespace dummy3
+namespace X86Internal {
 
 // A helper class to ease the settings of RandomizationPoolingPause
 // to disable constant blinding or pooling for some translation phases.
 class BoolFlagSaver {
   BoolFlagSaver() = delete;
   BoolFlagSaver(const BoolFlagSaver &) = delete;
   BoolFlagSaver &operator=(const BoolFlagSaver &) = delete;
 
 public:
   BoolFlagSaver(bool &F, bool NewValue) : OldValue(F), Flag(F) { F = NewValue; }
   ~BoolFlagSaver() { Flag = OldValue; }
 
 private:
   const bool OldValue;
   bool &Flag;
 };
 
-} // end of anonymous namespace
+template <class MachineTraits> class BoolFoldingEntry {
+  BoolFoldingEntry(const BoolFoldingEntry &) = delete;
 
-BoolFoldingEntry::BoolFoldingEntry(Inst *I)
-    : Instr(I), IsComplex(BoolFolding::hasComplexLowering(I)) {}
+public:
+  BoolFoldingEntry() = default;
+  explicit BoolFoldingEntry(Inst *I);
+  BoolFoldingEntry &operator=(const BoolFoldingEntry &) = default;
+  // Instr is the instruction producing the i1-type variable of interest.
+  Inst *Instr = nullptr;
+  // IsComplex is the cached result of BoolFolding::hasComplexLowering(Instr).
+  bool IsComplex = false;
+  // IsLiveOut is initialized conservatively to true, and is set to false when
+  // we encounter an instruction that ends Var's live range.  We disable the
+  // folding optimization when Var is live beyond this basic block.  Note that
+  // if liveness analysis is not performed (e.g. in Om1 mode), IsLiveOut will
+  // always be true and the folding optimization will never be performed.
+  bool IsLiveOut = true;
+  // NumUses counts the number of times Var is used as a source operand in the
+  // basic block.  If IsComplex is true and there is more than one use of Var,
+  // then the folding optimization is disabled for Var.
+  uint32_t NumUses = 0;
+};
 
-BoolFolding::BoolFoldingProducerKind
-BoolFolding::getProducerKind(const Inst *Instr) {
+template <class MachineTraits> class BoolFolding {
+public:
+  enum BoolFoldingProducerKind {
+    PK_None,
+    PK_Icmp32,
+    PK_Icmp64,
+    PK_Fcmp,
+    PK_Trunc
+  };
+
+  // Currently the actual enum values are not used (other than CK_None), but we
+  // go
+  // ahead and produce them anyway for symmetry with the
+  // BoolFoldingProducerKind.
+  enum BoolFoldingConsumerKind { CK_None, CK_Br, CK_Select, CK_Sext, CK_Zext };
+
+private:
+  BoolFolding(const BoolFolding &) = delete;
+  BoolFolding &operator=(const BoolFolding &) = delete;
+
+public:
+  BoolFolding() = default;
+  static BoolFoldingProducerKind getProducerKind(const Inst *Instr);
+  static BoolFoldingConsumerKind getConsumerKind(const Inst *Instr);
+  static bool hasComplexLowering(const Inst *Instr);
+  void init(CfgNode *Node);
+  const Inst *getProducerFor(const Operand *Opnd) const;
+  void dump(const Cfg *Func) const;
+
+private:
+  // Returns true if Producers contains a valid entry for the given VarNum.
+  bool containsValid(SizeT VarNum) const {
+    auto Element = Producers.find(VarNum);
+    return Element != Producers.end() && Element->second.Instr != nullptr;
+  }
+  void setInvalid(SizeT VarNum) { Producers[VarNum].Instr = nullptr; }
+  // Producers maps Variable::Number to a BoolFoldingEntry.
+  std::unordered_map<SizeT, BoolFoldingEntry<MachineTraits>> Producers;
+};
+
+template <class MachineTraits>
+BoolFoldingEntry<MachineTraits>::BoolFoldingEntry(Inst *I)
+    : Instr(I), IsComplex(BoolFolding<MachineTraits>::hasComplexLowering(I)) {}
+
+template <class MachineTraits>
+typename BoolFolding<MachineTraits>::BoolFoldingProducerKind
+BoolFolding<MachineTraits>::getProducerKind(const Inst *Instr) {
   if (llvm::isa<InstIcmp>(Instr)) {
     if (Instr->getSrc(0)->getType() != IceType_i64)
       return PK_Icmp32;
     return PK_None; // TODO(stichnot): actually PK_Icmp64;
   }
   return PK_None; // TODO(stichnot): remove this
 
   if (llvm::isa<InstFcmp>(Instr))
     return PK_Fcmp;
   if (auto *Cast = llvm::dyn_cast<InstCast>(Instr)) {
     switch (Cast->getCastKind()) {
     default:
       return PK_None;
     case InstCast::Trunc:
       return PK_Trunc;
     }
   }
   return PK_None;
 }
 
-BoolFolding::BoolFoldingConsumerKind
-BoolFolding::getConsumerKind(const Inst *Instr) {
+template <class MachineTraits>
+typename BoolFolding<MachineTraits>::BoolFoldingConsumerKind
+BoolFolding<MachineTraits>::getConsumerKind(const Inst *Instr) {
   if (llvm::isa<InstBr>(Instr))
     return CK_Br;
   if (llvm::isa<InstSelect>(Instr))
     return CK_Select;
   return CK_None; // TODO(stichnot): remove this
 
   if (auto *Cast = llvm::dyn_cast<InstCast>(Instr)) {
     switch (Cast->getCastKind()) {
     default:
       return CK_None;
     case InstCast::Sext:
       return CK_Sext;
     case InstCast::Zext:
       return CK_Zext;
     }
   }
   return CK_None;
 }
 
 // Returns true if the producing instruction has a "complex" lowering
 // sequence.  This generally means that its lowering sequence requires
 // more than one conditional branch, namely 64-bit integer compares
 // and some floating-point compares.  When this is true, and there is
 // more than one consumer, we prefer to disable the folding
 // optimization because it minimizes branches.
-bool BoolFolding::hasComplexLowering(const Inst *Instr) {
+template <class MachineTraits>
+bool BoolFolding<MachineTraits>::hasComplexLowering(const Inst *Instr) {
   switch (getProducerKind(Instr)) {
   default:
     return false;
   case PK_Icmp64:
     return true;
   case PK_Fcmp:
-    return TableFcmp[llvm::cast<InstFcmp>(Instr)->getCondition()].C2 !=
-           CondX86::Br_None;
+    return MachineTraits::TableFcmp[llvm::cast<InstFcmp>(Instr)->getCondition()]
+               .C2 != CondX86::Br_None;
   }
 }
 
-void BoolFolding::init(CfgNode *Node) {
+template <class MachineTraits>
+void BoolFolding<MachineTraits>::init(CfgNode *Node) {
   Producers.clear();
   for (Inst &Instr : Node->getInsts()) {
     // Check whether Instr is a valid producer.
     Variable *Var = Instr.getDest();
     if (!Instr.isDeleted() // only consider non-deleted instructions
         && Var             // only instructions with an actual dest var
         && Var->getType() == IceType_i1          // only bool-type dest vars
         && getProducerKind(&Instr) != PK_None) { // white-listed instructions
-      Producers[Var->getIndex()] = BoolFoldingEntry(&Instr);
+      Producers[Var->getIndex()] = BoolFoldingEntry<MachineTraits>(&Instr);
     }
     // Check each src variable against the map.
     for (SizeT I = 0; I < Instr.getSrcSize(); ++I) {
       Operand *Src = Instr.getSrc(I);
       SizeT NumVars = Src->getNumVars();
       for (SizeT J = 0; J < NumVars; ++J) {
         const Variable *Var = Src->getVar(J);
         SizeT VarNum = Var->getIndex();
         if (containsValid(VarNum)) {
           if (I != 0 // All valid consumers use Var as the first source operand
@@ skipping 21 matching lines @@
       continue;
     }
     // Mark as "dead" rather than outright deleting.  This is so that
     // other peephole style optimizations during or before lowering
     // have access to this instruction in undeleted form.  See for
     // example tryOptimizedCmpxchgCmpBr().
     I.second.Instr->setDead();
   }
 }
 
-const Inst *BoolFolding::getProducerFor(const Operand *Opnd) const {
+template <class MachineTraits>
+const Inst *
+BoolFolding<MachineTraits>::getProducerFor(const Operand *Opnd) const {
   auto *Var = llvm::dyn_cast<const Variable>(Opnd);
   if (Var == nullptr)
     return nullptr;
   SizeT VarNum = Var->getIndex();
   auto Element = Producers.find(VarNum);
   if (Element == Producers.end())
     return nullptr;
   return Element->second.Instr;
 }
 
-void BoolFolding::dump(const Cfg *Func) const {
+template <class MachineTraits>
+void BoolFolding<MachineTraits>::dump(const Cfg *Func) const {
   if (!ALLOW_DUMP || !Func->isVerbose(IceV_Folding))
     return;
   OstreamLocker L(Func->getContext());
   Ostream &Str = Func->getContext()->getStrDump();
   for (auto &I : Producers) {
     if (I.second.Instr == nullptr)
       continue;
     Str << "Found foldable producer:\n  ";
     I.second.Instr->dump(Func);
     Str << "\n";
   }
 }
 
-void TargetX8632::initNodeForLowering(CfgNode *Node) {
+template <class Machine>
+void TargetX86Base<Machine>::initNodeForLowering(CfgNode *Node) {
   FoldingInfo.init(Node);
   FoldingInfo.dump(Func);
 }
 
-TargetX8632::TargetX8632(Cfg *Func) : TargetLowering(Func) {
-  static_assert((X86InstructionSet::End - X86InstructionSet::Begin) ==
-                    (TargetInstructionSet::X86InstructionSet_End -
-                     TargetInstructionSet::X86InstructionSet_Begin),
-                "X86InstructionSet range different from TargetInstructionSet");
+template <class Machine>
+TargetX86Base<Machine>::TargetX86Base(Cfg *Func)
+    : Machine(Func) {
+  static_assert(
+      (Traits::InstructionSet::End - Traits::InstructionSet::Begin) ==
+          (TargetInstructionSet::X86InstructionSet_End -
+           TargetInstructionSet::X86InstructionSet_Begin),
+      "Traits::InstructionSet range different from TargetInstructionSet");
   if (Func->getContext()->getFlags().getTargetInstructionSet() !=
       TargetInstructionSet::BaseInstructionSet) {
-    InstructionSet = static_cast<X86InstructionSet>(
+    InstructionSet = static_cast<typename Traits::InstructionSet>(
         (Func->getContext()->getFlags().getTargetInstructionSet() -
          TargetInstructionSet::X86InstructionSet_Begin) +
-        X86InstructionSet::Begin);
+        Traits::InstructionSet::Begin);
   }
   // TODO: Don't initialize IntegerRegisters and friends every time.
   // Instead, initialize in some sort of static initializer for the
   // class.
   llvm::SmallBitVector IntegerRegisters(RegX8632::Reg_NUM);
   llvm::SmallBitVector IntegerRegistersI8(RegX8632::Reg_NUM);
   llvm::SmallBitVector FloatRegisters(RegX8632::Reg_NUM);
   llvm::SmallBitVector VectorRegisters(RegX8632::Reg_NUM);
   llvm::SmallBitVector InvalidRegisters(RegX8632::Reg_NUM);
   ScratchRegs.resize(RegX8632::Reg_NUM);
@@ skipping 16 matching lines @@
   TypeToRegisterSet[IceType_f64] = FloatRegisters;
   TypeToRegisterSet[IceType_v4i1] = VectorRegisters;
   TypeToRegisterSet[IceType_v8i1] = VectorRegisters;
   TypeToRegisterSet[IceType_v16i1] = VectorRegisters;
   TypeToRegisterSet[IceType_v16i8] = VectorRegisters;
   TypeToRegisterSet[IceType_v8i16] = VectorRegisters;
   TypeToRegisterSet[IceType_v4i32] = VectorRegisters;
   TypeToRegisterSet[IceType_v4f32] = VectorRegisters;
 }
 
-void TargetX8632::translateO2() {
+template <class Machine> void TargetX86Base<Machine>::translateO2() {
   TimerMarker T(TimerStack::TT_O2, Func);
 
   if (!Ctx->getFlags().getPhiEdgeSplit()) {
     // Lower Phi instructions.
     Func->placePhiLoads();
     if (Func->hasError())
       return;
     Func->placePhiStores();
     if (Func->hasError())
       return;
@@ skipping 91 matching lines @@
   // needed for searching for opportunities.
   Func->doBranchOpt();
   Func->dump("After branch optimization");
 
   // Nop insertion
   if (Ctx->getFlags().shouldDoNopInsertion()) {
     Func->doNopInsertion();
   }
 }
 
-void TargetX8632::translateOm1() {
+template <class Machine> void TargetX86Base<Machine>::translateOm1() {
   TimerMarker T(TimerStack::TT_Om1, Func);
 
   Func->placePhiLoads();
   if (Func->hasError())
     return;
   Func->placePhiStores();
   if (Func->hasError())
     return;
   Func->deletePhis();
   if (Func->hasError())
@@ skipping 16 matching lines @@
   if (Func->hasError())
     return;
   Func->dump("After stack frame mapping");
 
   // Nop insertion
   if (Ctx->getFlags().shouldDoNopInsertion()) {
     Func->doNopInsertion();
   }
 }
 
-namespace {
-
 bool canRMW(const InstArithmetic *Arith) {
   Type Ty = Arith->getDest()->getType();
   // X86 vector instructions write to a register and have no RMW
   // option.
   if (isVectorType(Ty))
     return false;
   bool isI64 = Ty == IceType_i64;
 
   switch (Arith->getOp()) {
   // Not handled for lack of simple lowering:
@@ skipping 25 matching lines @@
       return MemA->getBase() == MemB->getBase() &&
              MemA->getOffset() == MemB->getOffset() &&
              MemA->getIndex() == MemB->getIndex() &&
              MemA->getShift() == MemB->getShift() &&
              MemA->getSegmentRegister() == MemB->getSegmentRegister();
     }
   }
   return false;
 }
 
-} // end of anonymous namespace
-
-void TargetX8632::findRMW() {
+template <class Machine> void TargetX86Base<Machine>::findRMW() {
   Func->dump("Before RMW");
   OstreamLocker L(Func->getContext());
   Ostream &Str = Func->getContext()->getStrDump();
   for (CfgNode *Node : Func->getNodes()) {
     // Walk through the instructions, considering each sequence of 3
     // instructions, and look for the particular RMW pattern.  Note that this
     // search can be "broken" (false negatives) if there are intervening deleted
     // instructions, or intervening instructions that could be safely moved out
     // of the way to reveal an RMW pattern.
     auto E = Node->getInsts().end();
@@ skipping 71 matching lines @@
             InstX8632FakeRMW *RMW = InstX8632FakeRMW::create(
                 Func, ArithSrcOther, Store->getAddr(), Beacon, Arith->getOp());
             Node->getInsts().insert(I3, RMW);
           }
         }
       }
     }
   }
 }
 
-namespace {
-
 // Converts a ConstantInteger32 operand into its constant value, or
 // MemoryOrderInvalid if the operand is not a ConstantInteger32.
 uint64_t getConstantMemoryOrder(Operand *Opnd) {
   if (auto Integer = llvm::dyn_cast<ConstantInteger32>(Opnd))
     return Integer->getValue();
   return Intrinsics::MemoryOrderInvalid;
 }
 
 // Determines whether the dest of a Load instruction can be folded
 // into one of the src operands of a 2-operand instruction.  This is
 // true as long as the load dest matches exactly one of the binary
 // instruction's src operands.  Replaces Src0 or Src1 with LoadSrc if
 // the answer is true.
 bool canFoldLoadIntoBinaryInst(Operand *LoadSrc, Variable *LoadDest,
                                Operand *&Src0, Operand *&Src1) {
   if (Src0 == LoadDest && Src1 != LoadDest) {
     Src0 = LoadSrc;
     return true;
   }
   if (Src0 != LoadDest && Src1 == LoadDest) {
     Src1 = LoadSrc;
     return true;
   }
   return false;
 }
 
-} // end of anonymous namespace
-
-void TargetX8632::doLoadOpt() {
+template <class Machine> void TargetX86Base<Machine>::doLoadOpt() {
   for (CfgNode *Node : Func->getNodes()) {
     Context.init(Node);
     while (!Context.atEnd()) {
       Variable *LoadDest = nullptr;
       Operand *LoadSrc = nullptr;
       Inst *CurInst = Context.getCur();
       Inst *Next = Context.getNextInst();
       // Determine whether the current instruction is a Load
       // instruction or equivalent.
       if (auto *Load = llvm::dyn_cast<InstLoad>(CurInst)) {
@@ skipping 69 matching lines @@
           NewInst->spliceLivenessInfo(Next, CurInst);
         }
       }
       Context.advanceCur();
       Context.advanceNext();
     }
   }
   Func->dump("After load optimization");
 }
 
-bool TargetX8632::doBranchOpt(Inst *I, const CfgNode *NextNode) {
+template <class Machine>
+bool TargetX86Base<Machine>::doBranchOpt(Inst *I, const CfgNode *NextNode) {
   if (InstX8632Br *Br = llvm::dyn_cast<InstX8632Br>(I)) {
     return Br->optimizeBranch(NextNode);
   }
   return false;
 }
 
-IceString TargetX8632::RegNames[] = {
+template <class Machine>
+IceString TargetX86Base<Machine>::RegNames[] = {
 #define X(val, encode, name, name16, name8, scratch, preserved, stackptr,      \
           frameptr, isI8, isInt, isFP)                                         \
   name,
     REGX8632_TABLE
 #undef X
 };
 
-Variable *TargetX8632::getPhysicalRegister(SizeT RegNum, Type Ty) {
+template <class Machine>
+Variable *TargetX86Base<Machine>::getPhysicalRegister(SizeT RegNum, Type Ty) {
   if (Ty == IceType_void)
     Ty = IceType_i32;
   if (PhysicalRegisters[Ty].empty())
     PhysicalRegisters[Ty].resize(RegX8632::Reg_NUM);
   assert(RegNum < PhysicalRegisters[Ty].size());
   Variable *Reg = PhysicalRegisters[Ty][RegNum];
   if (Reg == nullptr) {
     Reg = Func->makeVariable(Ty);
     Reg->setRegNum(RegNum);
     PhysicalRegisters[Ty][RegNum] = Reg;
     // Specially mark esp as an "argument" so that it is considered
     // live upon function entry.
     if (RegNum == RegX8632::Reg_esp) {
       Func->addImplicitArg(Reg);
       Reg->setIgnoreLiveness();
     }
   }
   return Reg;
 }
 
-IceString TargetX8632::getRegName(SizeT RegNum, Type Ty) const {
+template <class Machine>
+IceString TargetX86Base<Machine>::getRegName(SizeT RegNum, Type Ty) const {
   assert(RegNum < RegX8632::Reg_NUM);
   static IceString RegNames8[] = {
 #define X(val, encode, name, name16, name8, scratch, preserved, stackptr,      \
           frameptr, isI8, isInt, isFP)                                         \
   name8,
       REGX8632_TABLE
 #undef X
   };
   static IceString RegNames16[] = {
 #define X(val, encode, name, name16, name8, scratch, preserved, stackptr,      \
           frameptr, isI8, isInt, isFP)                                         \
   name16,
       REGX8632_TABLE
 #undef X
   };
   switch (Ty) {
   case IceType_i1:
   case IceType_i8:
     return RegNames8[RegNum];
   case IceType_i16:
     return RegNames16[RegNum];
   default:
     return RegNames[RegNum];
   }
 }
 
-void TargetX8632::emitVariable(const Variable *Var) const {
+template <class Machine>
+void TargetX86Base<Machine>::emitVariable(const Variable *Var) const {
   Ostream &Str = Ctx->getStrEmit();
   if (Var->hasReg()) {
     Str << "%" << getRegName(Var->getRegNum(), Var->getType());
     return;
   }
   if (Var->getWeight().isInf()) {
     llvm_unreachable("Infinite-weight Variable has no register assigned");
   }
   int32_t Offset = Var->getStackOffset();
   if (!hasFramePointer())
     Offset += getStackAdjustment();
   if (Offset)
     Str << Offset;
   const Type FrameSPTy = IceType_i32;
   Str << "(%" << getRegName(getFrameOrStackReg(), FrameSPTy) << ")";
 }
 
-X8632::Address TargetX8632::stackVarToAsmOperand(const Variable *Var) const {
+template <class Machine>
+X8632::Address
+TargetX86Base<Machine>::stackVarToAsmOperand(const Variable *Var) const {
   if (Var->hasReg())
     llvm_unreachable("Stack Variable has a register assigned");
   if (Var->getWeight().isInf()) {
     llvm_unreachable("Infinite-weight Variable has no register assigned");
   }
   int32_t Offset = Var->getStackOffset();
   if (!hasFramePointer())
     Offset += getStackAdjustment();
   return X8632::Address(RegX8632::getEncodedGPR(getFrameOrStackReg()), Offset);
 }
 
-void TargetX8632::lowerArguments() {
+template <class Machine> void TargetX86Base<Machine>::lowerArguments() {
   VarList &Args = Func->getArgs();
   // The first four arguments of vector type, regardless of their
   // position relative to the other arguments in the argument list, are
   // passed in registers xmm0 - xmm3.
   unsigned NumXmmArgs = 0;
 
   Context.init(Func->getEntryNode());
   Context.setInsertPoint(Context.getCur());
 
-  for (SizeT I = 0, E = Args.size(); I < E && NumXmmArgs < X86_MAX_XMM_ARGS;
-       ++I) {
+  for (SizeT I = 0, E = Args.size();
+       I < E && NumXmmArgs < Traits::X86_MAX_XMM_ARGS; ++I) {
     Variable *Arg = Args[I];
     Type Ty = Arg->getType();
     if (!isVectorType(Ty))
       continue;
     // Replace Arg in the argument list with the home register.  Then
     // generate an instruction in the prolog to copy the home register
     // to the assigned location of Arg.
     int32_t RegNum = RegX8632::Reg_xmm0 + NumXmmArgs;
     ++NumXmmArgs;
     Variable *RegisterArg = Func->makeVariable(Ty);
@@ skipping 10 matching lines @@
 
 // Helper function for addProlog().
 //
 // This assumes Arg is an argument passed on the stack.  This sets the
 // frame offset for Arg and updates InArgsSizeBytes according to Arg's
 // width.  For an I64 arg that has been split into Lo and Hi components,
 // it calls itself recursively on the components, taking care to handle
 // Lo first because of the little-endian architecture.  Lastly, this
 // function generates an instruction to copy Arg into its assigned
 // register if applicable.
-void TargetX8632::finishArgumentLowering(Variable *Arg, Variable *FramePtr,
-                                         size_t BasicFrameOffset,
-                                         size_t &InArgsSizeBytes) {
+template <class Machine>
+void TargetX86Base<Machine>::finishArgumentLowering(Variable *Arg,
+                                                    Variable *FramePtr,
+                                                    size_t BasicFrameOffset,
+                                                    size_t &InArgsSizeBytes) {
   Variable *Lo = Arg->getLo();
   Variable *Hi = Arg->getHi();
   Type Ty = Arg->getType();
   if (Lo && Hi && Ty == IceType_i64) {
     assert(Lo->getType() != IceType_i64); // don't want infinite recursion
     assert(Hi->getType() != IceType_i64); // don't want infinite recursion
     finishArgumentLowering(Lo, FramePtr, BasicFrameOffset, InArgsSizeBytes);
     finishArgumentLowering(Hi, FramePtr, BasicFrameOffset, InArgsSizeBytes);
     return;
   }
   if (isVectorType(Ty)) {
-    InArgsSizeBytes = applyStackAlignment(InArgsSizeBytes);
+    InArgsSizeBytes = Traits::applyStackAlignment(InArgsSizeBytes);
   }
   Arg->setStackOffset(BasicFrameOffset + InArgsSizeBytes);
   InArgsSizeBytes += typeWidthInBytesOnStack(Ty);
   if (Arg->hasReg()) {
     assert(Ty != IceType_i64);
     OperandX8632Mem *Mem = OperandX8632Mem::create(
         Func, Ty, FramePtr, Ctx->getConstantInt32(Arg->getStackOffset()));
     if (isVectorType(Arg->getType())) {
       _movp(Arg, Mem);
     } else {
       _mov(Arg, Mem);
     }
     // This argument-copying instruction uses an explicit
     // OperandX8632Mem operand instead of a Variable, so its
     // fill-from-stack operation has to be tracked separately for
     // statistics.
     Ctx->statsUpdateFills();
   }
 }
 
-Type TargetX8632::stackSlotType() { return IceType_i32; }
+template <class Machine> Type TargetX86Base<Machine>::stackSlotType() {
+  return IceType_i32;
+}
 
-void TargetX8632::addProlog(CfgNode *Node) {
+template <class Machine> void TargetX86Base<Machine>::addProlog(CfgNode *Node) {
   // Stack frame layout:
   //
   // +------------------------+
   // | 1. return address      |
   // +------------------------+
   // | 2. preserved registers |
   // +------------------------+
   // | 3. padding             |
   // +------------------------+
   // | 4. global spill area   |
@@ skipping 88 matching lines @@
     _mov(ebp, esp);
     // Keep ebp live for late-stage liveness analysis
     // (e.g. asm-verbose mode).
     Context.insert(InstFakeUse::create(Func, ebp));
   }
 
   // Align the variables area. SpillAreaPaddingBytes is the size of
   // the region after the preserved registers and before the spill areas.
   // LocalsSlotsPaddingBytes is the amount of padding between the globals
   // and locals area if they are separate.
-  assert(SpillAreaAlignmentBytes <= X86_STACK_ALIGNMENT_BYTES);
+  assert(SpillAreaAlignmentBytes <= Traits::X86_STACK_ALIGNMENT_BYTES);
   assert(LocalsSlotsAlignmentBytes <= SpillAreaAlignmentBytes);
   uint32_t SpillAreaPaddingBytes = 0;
   uint32_t LocalsSlotsPaddingBytes = 0;
-  alignStackSpillAreas(X86_RET_IP_SIZE_BYTES + PreservedRegsSizeBytes,
+  alignStackSpillAreas(Traits::X86_RET_IP_SIZE_BYTES + PreservedRegsSizeBytes,
                        SpillAreaAlignmentBytes, GlobalsSize,
                        LocalsSlotsAlignmentBytes, &SpillAreaPaddingBytes,
                        &LocalsSlotsPaddingBytes);
   SpillAreaSizeBytes += SpillAreaPaddingBytes + LocalsSlotsPaddingBytes;
   uint32_t GlobalsAndSubsequentPaddingSize =
       GlobalsSize + LocalsSlotsPaddingBytes;
 
   // Align esp if necessary.
   if (NeedsStackAlignment) {
-    uint32_t StackOffset = X86_RET_IP_SIZE_BYTES + PreservedRegsSizeBytes;
-    uint32_t StackSize = applyStackAlignment(StackOffset + SpillAreaSizeBytes);
+    uint32_t StackOffset =
+        Traits::X86_RET_IP_SIZE_BYTES + PreservedRegsSizeBytes;
+    uint32_t StackSize =
+        Traits::applyStackAlignment(StackOffset + SpillAreaSizeBytes);
     SpillAreaSizeBytes = StackSize - StackOffset;
   }
 
   // Generate "sub esp, SpillAreaSizeBytes"
   if (SpillAreaSizeBytes)
     _sub(getPhysicalRegister(RegX8632::Reg_esp),
          Ctx->getConstantInt32(SpillAreaSizeBytes));
   Ctx->statsUpdateFrameBytes(SpillAreaSizeBytes);
 
   resetStackAdjustment();
 
   // Fill in stack offsets for stack args, and copy args into registers
   // for those that were register-allocated.  Args are pushed right to
   // left, so Arg[0] is closest to the stack/frame pointer.
   Variable *FramePtr = getPhysicalRegister(getFrameOrStackReg());
-  size_t BasicFrameOffset = PreservedRegsSizeBytes + X86_RET_IP_SIZE_BYTES;
+  size_t BasicFrameOffset =
+      PreservedRegsSizeBytes + Traits::X86_RET_IP_SIZE_BYTES;
   if (!IsEbpBasedFrame)
     BasicFrameOffset += SpillAreaSizeBytes;
 
   const VarList &Args = Func->getArgs();
   size_t InArgsSizeBytes = 0;
   unsigned NumXmmArgs = 0;
   for (Variable *Arg : Args) {
     // Skip arguments passed in registers.
-    if (isVectorType(Arg->getType()) && NumXmmArgs < X86_MAX_XMM_ARGS) {
+    if (isVectorType(Arg->getType()) && NumXmmArgs < Traits::X86_MAX_XMM_ARGS) {
       ++NumXmmArgs;
       continue;
     }
     finishArgumentLowering(Arg, FramePtr, BasicFrameOffset, InArgsSizeBytes);
   }
 
   // Fill in stack offsets for locals.
   assignVarStackSlots(SortedSpilledVariables, SpillAreaPaddingBytes,
                       SpillAreaSizeBytes, GlobalsAndSubsequentPaddingSize,
                       IsEbpBasedFrame);
   // Assign stack offsets to variables that have been linked to spilled
   // variables.
   for (Variable *Var : VariablesLinkedToSpillSlots) {
     Variable *Linked = (llvm::cast<SpillVariable>(Var))->getLinkedTo();
     Var->setStackOffset(Linked->getStackOffset());
   }
   this->HasComputedFrame = true;
 
   if (ALLOW_DUMP && Func->isVerbose(IceV_Frame)) {
     OstreamLocker L(Func->getContext());
     Ostream &Str = Func->getContext()->getStrDump();
 
     Str << "Stack layout:\n";
     uint32_t EspAdjustmentPaddingSize =
         SpillAreaSizeBytes - LocalsSpillAreaSize -
         GlobalsAndSubsequentPaddingSize - SpillAreaPaddingBytes;
     Str << " in-args = " << InArgsSizeBytes << " bytes\n"
-        << " return address = " << X86_RET_IP_SIZE_BYTES << " bytes\n"
+        << " return address = " << Traits::X86_RET_IP_SIZE_BYTES << " bytes\n"
         << " preserved registers = " << PreservedRegsSizeBytes << " bytes\n"
         << " spill area padding = " << SpillAreaPaddingBytes << " bytes\n"
         << " globals spill area = " << GlobalsSize << " bytes\n"
         << " globals-locals spill areas intermediate padding = "
         << GlobalsAndSubsequentPaddingSize - GlobalsSize << " bytes\n"
         << " locals spill area = " << LocalsSpillAreaSize << " bytes\n"
         << " esp alignment padding = " << EspAdjustmentPaddingSize
         << " bytes\n";
 
     Str << "Stack details:\n"
         << " esp adjustment = " << SpillAreaSizeBytes << " bytes\n"
         << " spill area alignment = " << SpillAreaAlignmentBytes << " bytes\n"
         << " locals spill area alignment = " << LocalsSlotsAlignmentBytes
         << " bytes\n"
         << " is ebp based = " << IsEbpBasedFrame << "\n";
   }
 }
 
-void TargetX8632::addEpilog(CfgNode *Node) {
+template <class Machine> void TargetX86Base<Machine>::addEpilog(CfgNode *Node) {
   InstList &Insts = Node->getInsts();
   InstList::reverse_iterator RI, E;
   for (RI = Insts.rbegin(), E = Insts.rend(); RI != E; ++RI) {
     if (llvm::isa<InstX8632Ret>(*RI))
       break;
   }
   if (RI == E)
     return;
 
   // Convert the reverse_iterator position into its corresponding
@@ skipping 32 matching lines @@
 
   if (!Ctx->getFlags().getUseSandboxing())
     return;
   // Change the original ret instruction into a sandboxed return sequence.
   // t:ecx = pop
   // bundle_lock
   // and t, ~31
   // jmp *t
   // bundle_unlock
   // FakeUse <original_ret_operand>
-  const SizeT BundleSize = 1
-                           << Func->getAssembler<>()->getBundleAlignLog2Bytes();
+  const SizeT BundleSize =
+      1 << Func->template getAssembler<>()->getBundleAlignLog2Bytes();
   Variable *T_ecx = makeReg(IceType_i32, RegX8632::Reg_ecx);
   _pop(T_ecx);
   _bundle_lock();
   _and(T_ecx, Ctx->getConstantInt32(~(BundleSize - 1)));
   _jmp(T_ecx);
   _bundle_unlock();
   if (RI->getSrcSize()) {
     Variable *RetValue = llvm::cast<Variable>(RI->getSrc(0));
     Context.insert(InstFakeUse::create(Func, RetValue));
   }
   RI->setDeleted();
 }
 
-void TargetX8632::split64(Variable *Var) {
+template <class Machine> void TargetX86Base<Machine>::split64(Variable *Var) {
   switch (Var->getType()) {
   default:
     return;
   case IceType_i64:
   // TODO: Only consider F64 if we need to push each half when
   // passing as an argument to a function call.  Note that each half
   // is still typed as I32.
   case IceType_f64:
     break;
   }
@@ skipping 10 matching lines @@
     Lo->setName(Func, Var->getName(Func) + "__lo");
     Hi->setName(Func, Var->getName(Func) + "__hi");
   }
   Var->setLoHi(Lo, Hi);
   if (Var->getIsArg()) {
     Lo->setIsArg();
     Hi->setIsArg();
   }
 }
 
-Operand *TargetX8632::loOperand(Operand *Operand) {
+template <class Machine>
+Operand *TargetX86Base<Machine>::loOperand(Operand *Operand) {
   assert(Operand->getType() == IceType_i64 ||
          Operand->getType() == IceType_f64);
   if (Operand->getType() != IceType_i64 && Operand->getType() != IceType_f64)
     return Operand;
   if (Variable *Var = llvm::dyn_cast<Variable>(Operand)) {
     split64(Var);
     return Var->getLo();
   }
   if (ConstantInteger64 *Const = llvm::dyn_cast<ConstantInteger64>(Operand)) {
     ConstantInteger32 *ConstInt = llvm::dyn_cast<ConstantInteger32>(
         Ctx->getConstantInt32(static_cast<int32_t>(Const->getValue())));
     return legalize(ConstInt);
   }
   if (OperandX8632Mem *Mem = llvm::dyn_cast<OperandX8632Mem>(Operand)) {
     OperandX8632Mem *MemOperand = OperandX8632Mem::create(
         Func, IceType_i32, Mem->getBase(), Mem->getOffset(), Mem->getIndex(),
         Mem->getShift(), Mem->getSegmentRegister());
     // Test if we should randomize or pool the offset, if so randomize it or
     // pool it then create mem operand with the blinded/pooled constant.
     // Otherwise, return the mem operand as ordinary mem operand.
     return legalize(MemOperand);
   }
   llvm_unreachable("Unsupported operand type");
   return nullptr;
 }
 
-Operand *TargetX8632::hiOperand(Operand *Operand) {
+template <class Machine>
+Operand *TargetX86Base<Machine>::hiOperand(Operand *Operand) {
   assert(Operand->getType() == IceType_i64 ||
          Operand->getType() == IceType_f64);
   if (Operand->getType() != IceType_i64 && Operand->getType() != IceType_f64)
     return Operand;
   if (Variable *Var = llvm::dyn_cast<Variable>(Operand)) {
     split64(Var);
     return Var->getHi();
   }
   if (ConstantInteger64 *Const = llvm::dyn_cast<ConstantInteger64>(Operand)) {
     ConstantInteger32 *ConstInt = llvm::dyn_cast<ConstantInteger32>(
@@ skipping 20 matching lines @@
         Mem->getShift(), Mem->getSegmentRegister());
     // Test if the Offset is an eligible i32 constants for randomization and
     // pooling. Blind/pool it if it is. Otherwise return as oridinary mem
     // operand.
     return legalize(MemOperand);
   }
   llvm_unreachable("Unsupported operand type");
   return nullptr;
 }
 
-llvm::SmallBitVector TargetX8632::getRegisterSet(RegSetMask Include,
-                                                 RegSetMask Exclude) const {
+template <class Machine>
+llvm::SmallBitVector
+TargetX86Base<Machine>::getRegisterSet(RegSetMask Include,
+                                       RegSetMask Exclude) const {
   llvm::SmallBitVector Registers(RegX8632::Reg_NUM);
 
 #define X(val, encode, name, name16, name8, scratch, preserved, stackptr,      \
           frameptr, isI8, isInt, isFP)                                         \
   if (scratch && (Include & RegSet_CallerSave))                                \
     Registers[RegX8632::val] = true;                                           \
   if (preserved && (Include & RegSet_CalleeSave))                              \
     Registers[RegX8632::val] = true;                                           \
   if (stackptr && (Include & RegSet_StackPointer))                             \
     Registers[RegX8632::val] = true;                                           \
   if (frameptr && (Include & RegSet_FramePointer))                             \
     Registers[RegX8632::val] = true;                                           \
   if (scratch && (Exclude & RegSet_CallerSave))                                \
     Registers[RegX8632::val] = false;                                          \
   if (preserved && (Exclude & RegSet_CalleeSave))                              \
     Registers[RegX8632::val] = false;                                          \
   if (stackptr && (Exclude & RegSet_StackPointer))                             \
     Registers[RegX8632::val] = false;                                          \
   if (frameptr && (Exclude & RegSet_FramePointer))                             \
     Registers[RegX8632::val] = false;
 
   REGX8632_TABLE
 
 #undef X
 
   return Registers;
 }
 
-void TargetX8632::lowerAlloca(const InstAlloca *Inst) {
+template <class Machine>
+void TargetX86Base<Machine>::lowerAlloca(const InstAlloca *Inst) {
   IsEbpBasedFrame = true;
   // Conservatively require the stack to be aligned.  Some stack
   // adjustment operations implemented below assume that the stack is
   // aligned before the alloca.  All the alloca code ensures that the
   // stack alignment is preserved after the alloca.  The stack alignment
   // restriction can be relaxed in some cases.
   NeedsStackAlignment = true;
 
   // TODO(stichnot): minimize the number of adjustments of esp, etc.
   Variable *esp = getPhysicalRegister(RegX8632::Reg_esp);
   Operand *TotalSize = legalize(Inst->getSizeInBytes());
   Variable *Dest = Inst->getDest();
   uint32_t AlignmentParam = Inst->getAlignInBytes();
   // For default align=0, set it to the real value 1, to avoid any
   // bit-manipulation problems below.
   AlignmentParam = std::max(AlignmentParam, 1u);
 
   // LLVM enforces power of 2 alignment.
   assert(llvm::isPowerOf2_32(AlignmentParam));
-  assert(llvm::isPowerOf2_32(X86_STACK_ALIGNMENT_BYTES));
+  assert(llvm::isPowerOf2_32(Traits::X86_STACK_ALIGNMENT_BYTES));
 
-  uint32_t Alignment = std::max(AlignmentParam, X86_STACK_ALIGNMENT_BYTES);
-  if (Alignment > X86_STACK_ALIGNMENT_BYTES) {
+  uint32_t Alignment =
+      std::max(AlignmentParam, Traits::X86_STACK_ALIGNMENT_BYTES);
+  if (Alignment > Traits::X86_STACK_ALIGNMENT_BYTES) {
     _and(esp, Ctx->getConstantInt32(-Alignment));
   }
   if (const auto *ConstantTotalSize =
           llvm::dyn_cast<ConstantInteger32>(TotalSize)) {
     uint32_t Value = ConstantTotalSize->getValue();
     Value = Utils::applyAlignment(Value, Alignment);
     _sub(esp, Ctx->getConstantInt32(Value));
   } else {
     // Non-constant sizes need to be adjusted to the next highest
     // multiple of the required alignment at runtime.
     Variable *T = makeReg(IceType_i32);
     _mov(T, TotalSize);
     _add(T, Ctx->getConstantInt32(Alignment - 1));
     _and(T, Ctx->getConstantInt32(-Alignment));
     _sub(esp, T);
   }
   _mov(Dest, esp);
 }
 
 // Strength-reduce scalar integer multiplication by a constant (for
 // i32 or narrower) for certain constants.  The lea instruction can be
 // used to multiply by 3, 5, or 9, and the lsh instruction can be used
 // to multiply by powers of 2.  These can be combined such that
 // e.g. multiplying by 100 can be done as 2 lea-based multiplies by 5,
 // combined with left-shifting by 2.
-bool TargetX8632::optimizeScalarMul(Variable *Dest, Operand *Src0,
-                                    int32_t Src1) {
+template <class Machine>
+bool TargetX86Base<Machine>::optimizeScalarMul(Variable *Dest, Operand *Src0,
+                                               int32_t Src1) {
   // Disable this optimization for Om1 and O0, just to keep things
   // simple there.
   if (Ctx->getFlags().getOptLevel() < Opt_1)
     return false;
   Type Ty = Dest->getType();
   Variable *T = nullptr;
   if (Src1 == -1) {
     _mov(T, Src0);
     _neg(T);
     _mov(Dest, T);
@@ skipping 68 matching lines @@
   }
   if (Count2) {
     _shl(T, Ctx->getConstantInt(Ty, Count2));
   }
   if (Src1IsNegative)
     _neg(T);
   _mov(Dest, T);
   return true;
 }
 
-void TargetX8632::lowerArithmetic(const InstArithmetic *Inst) {
+template <class Machine>
+void TargetX86Base<Machine>::lowerArithmetic(const InstArithmetic *Inst) {
   Variable *Dest = Inst->getDest();
   Operand *Src0 = legalize(Inst->getSrc(0));
   Operand *Src1 = legalize(Inst->getSrc(1));
   if (Inst->isCommutative()) {
     if (!llvm::isa<Variable>(Src0) && llvm::isa<Variable>(Src1))
       std::swap(Src0, Src1);
     if (llvm::isa<Constant>(Src0) && !llvm::isa<Constant>(Src1))
       std::swap(Src0, Src1);
   }
   if (Dest->getType() == IceType_i64) {
@@ skipping 282 matching lines @@
     case InstArithmetic::Sub: {
       Variable *T = makeReg(Dest->getType());
       _movp(T, Src0);
       _psub(T, Src1);
       _movp(Dest, T);
     } break;
     case InstArithmetic::Mul: {
       bool TypesAreValidForPmull =
           Dest->getType() == IceType_v4i32 || Dest->getType() == IceType_v8i16;
       bool InstructionSetIsValidForPmull =
-          Dest->getType() == IceType_v8i16 || InstructionSet >= SSE4_1;
+          Dest->getType() == IceType_v8i16 || InstructionSet >= Machine::SSE4_1;
       if (TypesAreValidForPmull && InstructionSetIsValidForPmull) {
         Variable *T = makeReg(Dest->getType());
         _movp(T, Src0);
         _pmull(T, Src1);
         _movp(Dest, T);
       } else if (Dest->getType() == IceType_v4i32) {
         // Lowering sequence:
         // Note: The mask arguments have index 0 on the left.
         //
         // movups  T1, Src0
@@ skipping 173 matching lines @@
         if (Divisor > 0 && llvm::isPowerOf2_32(UDivisor)) {
           uint32_t LogDiv = llvm::Log2_32(UDivisor);
           Type Ty = Dest->getType();
           // LLVM does the following for dest=src/(1<<log):
           //   t=src
           //   sar t,typewidth-1 // -1 if src is negative, 0 if not
           //   shr t,typewidth-log
           //   add t,src
           //   sar t,log
           //   dest=t
-          uint32_t TypeWidth = X86_CHAR_BIT * typeWidthInBytes(Ty);
+          uint32_t TypeWidth = Traits::X86_CHAR_BIT * typeWidthInBytes(Ty);
           _mov(T, Src0);
           // If for some reason we are dividing by 1, just treat it
           // like an assignment.
           if (LogDiv > 0) {
             // The initial sar is unnecessary when dividing by 2.
             if (LogDiv > 1)
               _sar(T, Ctx->getConstantInt(Ty, TypeWidth - 1));
             _shr(T, Ctx->getConstantInt(Ty, TypeWidth - LogDiv));
             _add(T, Src0);
             _sar(T, Ctx->getConstantInt(Ty, LogDiv));
@@ skipping 48 matching lines @@
           Type Ty = Dest->getType();
           // LLVM does the following for dest=src%(1<<log):
           //   t=src
           //   sar t,typewidth-1 // -1 if src is negative, 0 if not
           //   shr t,typewidth-log
           //   add t,src
           //   and t, -(1<<log)
           //   sub t,src
           //   neg t
           //   dest=t
-          uint32_t TypeWidth = X86_CHAR_BIT * typeWidthInBytes(Ty);
+          uint32_t TypeWidth = Traits::X86_CHAR_BIT * typeWidthInBytes(Ty);
           // If for some reason we are dividing by 1, just assign 0.
           if (LogDiv == 0) {
             _mov(Dest, Ctx->getConstantZero(Ty));
             return;
           }
           _mov(T, Src0);
           // The initial sar is unnecessary when dividing by 2.
           if (LogDiv > 1)
             _sar(T, Ctx->getConstantInt(Ty, TypeWidth - 1));
           _shr(T, Ctx->getConstantInt(Ty, TypeWidth - LogDiv));
@@ skipping 47 matching lines @@
     Type Ty = Dest->getType();
     InstCall *Call = makeHelperCall(
         isFloat32Asserting32Or64(Ty) ? H_frem_f32 : H_frem_f64, Dest, MaxSrcs);
     Call->addArg(Src0);
     Call->addArg(Src1);
     return lowerCall(Call);
   }
   }
 }
 
-void TargetX8632::lowerAssign(const InstAssign *Inst) {
+template <class Machine>
+void TargetX86Base<Machine>::lowerAssign(const InstAssign *Inst) {
   Variable *Dest = Inst->getDest();
   Operand *Src0 = Inst->getSrc(0);
   assert(Dest->getType() == Src0->getType());
   if (Dest->getType() == IceType_i64) {
     Src0 = legalize(Src0);
     Operand *Src0Lo = loOperand(Src0);
     Operand *Src0Hi = hiOperand(Src0);
     Variable *DestLo = llvm::cast<Variable>(loOperand(Dest));
     Variable *DestHi = llvm::cast<Variable>(hiOperand(Dest));
     Variable *T_Lo = nullptr, *T_Hi = nullptr;
@@ skipping 24 matching lines @@
       // register or a scalar integer immediate.
       RI = legalize(Src0, Legal_Reg | Legal_Imm);
     }
     if (isVectorType(Dest->getType()))
       _movp(Dest, RI);
     else
       _mov(Dest, RI);
   }
 }
 
-void TargetX8632::lowerBr(const InstBr *Inst) {
+template <class Machine>
+void TargetX86Base<Machine>::lowerBr(const InstBr *Inst) {
   if (Inst->isUnconditional()) {
     _br(Inst->getTargetUnconditional());
     return;
   }
   Operand *Cond = Inst->getCondition();
 
   // Handle folding opportunities.
   if (const class Inst *Producer = FoldingInfo.getProducerFor(Cond)) {
     assert(Producer->isDeleted());
     switch (BoolFolding::getProducerKind(Producer)) {
     default:
       break;
     case BoolFolding::PK_Icmp32: {
       // TODO(stichnot): Refactor similarities between this block and
       // the corresponding code in lowerIcmp().
       auto *Cmp = llvm::dyn_cast<InstIcmp>(Producer);
       Operand *Src0 = Producer->getSrc(0);
       Operand *Src1 = legalize(Producer->getSrc(1));
       Operand *Src0RM = legalizeSrc0ForCmp(Src0, Src1);
       _cmp(Src0RM, Src1);
-      _br(getIcmp32Mapping(Cmp->getCondition()), Inst->getTargetTrue(),
+      _br(Traits::getIcmp32Mapping(Cmp->getCondition()), Inst->getTargetTrue(),
           Inst->getTargetFalse());
       return;
     }
     }
   }
 
   Operand *Src0 = legalize(Cond, Legal_Reg | Legal_Mem);
   Constant *Zero = Ctx->getConstantZero(IceType_i32);
   _cmp(Src0, Zero);
   _br(CondX86::Br_ne, Inst->getTargetTrue(), Inst->getTargetFalse());
 }
 
-void TargetX8632::lowerCall(const InstCall *Instr) {
+template <class Machine>
+void TargetX86Base<Machine>::lowerCall(const InstCall *Instr) {
   // x86-32 calling convention:
   //
   // * At the point before the call, the stack must be aligned to 16
   // bytes.
   //
   // * The first four arguments of vector type, regardless of their
   // position relative to the other arguments in the argument list, are
   // placed in registers xmm0 - xmm3.
   //
   // * Other arguments are pushed onto the stack in right-to-left order,
@@ skipping 14 matching lines @@
   OperandList StackArgs, StackArgLocations;
   uint32_t ParameterAreaSizeBytes = 0;
 
   // Classify each argument operand according to the location where the
   // argument is passed.
   for (SizeT i = 0, NumArgs = Instr->getNumArgs(); i < NumArgs; ++i) {
     Operand *Arg = Instr->getArg(i);
     Type Ty = Arg->getType();
     // The PNaCl ABI requires the width of arguments to be at least 32 bits.
     assert(typeWidthInBytes(Ty) >= 4);
-    if (isVectorType(Ty) && XmmArgs.size() < X86_MAX_XMM_ARGS) {
+    if (isVectorType(Ty) && XmmArgs.size() < Traits::X86_MAX_XMM_ARGS) {
       XmmArgs.push_back(Arg);
     } else {
       StackArgs.push_back(Arg);
       if (isVectorType(Arg->getType())) {
-        ParameterAreaSizeBytes = applyStackAlignment(ParameterAreaSizeBytes);
+        ParameterAreaSizeBytes =
+            Traits::applyStackAlignment(ParameterAreaSizeBytes);
       }
       Variable *esp = Func->getTarget()->getPhysicalRegister(RegX8632::Reg_esp);
       Constant *Loc = Ctx->getConstantInt32(ParameterAreaSizeBytes);
       StackArgLocations.push_back(OperandX8632Mem::create(Func, Ty, esp, Loc));
       ParameterAreaSizeBytes += typeWidthInBytesOnStack(Arg->getType());
     }
   }
 
   // Adjust the parameter area so that the stack is aligned.  It is
   // assumed that the stack is already aligned at the start of the
   // calling sequence.
-  ParameterAreaSizeBytes = applyStackAlignment(ParameterAreaSizeBytes);
+  ParameterAreaSizeBytes = Traits::applyStackAlignment(ParameterAreaSizeBytes);
 
   // Subtract the appropriate amount for the argument area.  This also
   // takes care of setting the stack adjustment during emission.
   //
   // TODO: If for some reason the call instruction gets dead-code
   // eliminated after lowering, we would need to ensure that the
   // pre-call and the post-call esp adjustment get eliminated as well.
   if (ParameterAreaSizeBytes) {
     _adjust_stack(ParameterAreaSizeBytes);
   }
@@ skipping 62 matching lines @@
   Operand *CallTarget = legalize(Instr->getCallTarget());
   const bool NeedSandboxing = Ctx->getFlags().getUseSandboxing();
   if (NeedSandboxing) {
     if (llvm::isa<Constant>(CallTarget)) {
       _bundle_lock(InstBundleLock::Opt_AlignToEnd);
     } else {
       Variable *CallTargetVar = nullptr;
       _mov(CallTargetVar, CallTarget);
       _bundle_lock(InstBundleLock::Opt_AlignToEnd);
       const SizeT BundleSize =
-          1 << Func->getAssembler<>()->getBundleAlignLog2Bytes();
+          1 << Func->template getAssembler<>()->getBundleAlignLog2Bytes();
       _and(CallTargetVar, Ctx->getConstantInt32(~(BundleSize - 1)));
       CallTarget = CallTargetVar;
     }
   }
   Inst *NewCall = InstX8632Call::create(Func, ReturnReg, CallTarget);
   Context.insert(NewCall);
   if (NeedSandboxing)
     _bundle_unlock();
   if (ReturnRegHi)
     Context.insert(InstFakeDef::create(Func, ReturnRegHi));
@@ skipping 41 matching lines @@
     // st(0).
     // If Dest ends up being a physical xmm register, the fstp emit code
     // will route st(0) through a temporary stack slot.
     _fstp(Dest);
     // Create a fake use of Dest in case it actually isn't used,
     // because st(0) still needs to be popped.
     Context.insert(InstFakeUse::create(Func, Dest));
   }
 }
 
-void TargetX8632::lowerCast(const InstCast *Inst) {
+template <class Machine>
+void TargetX86Base<Machine>::lowerCast(const InstCast *Inst) {
   // a = cast(b) ==> t=cast(b); a=t; (link t->b, link a->t, no overlap)
   InstCast::OpKind CastKind = Inst->getCastKind();
   Variable *Dest = Inst->getDest();
   switch (CastKind) {
   default:
     Func->setError("Cast type not supported");
     return;
   case InstCast::Sext: {
     // Src0RM is the source operand legalized to physical register or memory,
     // but not immediate, since the relevant x86 native instructions don't
     // allow an immediate operand.  If the operand is an immediate, we could
     // consider computing the strength-reduced result at translation time,
     // but we're unlikely to see something like that in the bitcode that
     // the optimizer wouldn't have already taken care of.
     Operand *Src0RM = legalize(Inst->getSrc(0), Legal_Reg | Legal_Mem);
     if (isVectorType(Dest->getType())) {
       Type DestTy = Dest->getType();
       if (DestTy == IceType_v16i8) {
         // onemask = materialize(1,1,...); dst = (src & onemask) > 0
         Variable *OneMask = makeVectorOfOnes(Dest->getType());
         Variable *T = makeReg(DestTy);
         _movp(T, Src0RM);
         _pand(T, OneMask);
         Variable *Zeros = makeVectorOfZeros(Dest->getType());
         _pcmpgt(T, Zeros);
         _movp(Dest, T);
       } else {
         // width = width(elty) - 1; dest = (src << width) >> width
         SizeT ShiftAmount =
-            X86_CHAR_BIT * typeWidthInBytes(typeElementType(DestTy)) - 1;
+            Traits::X86_CHAR_BIT * typeWidthInBytes(typeElementType(DestTy)) -
+            1;
         Constant *ShiftConstant = Ctx->getConstantInt8(ShiftAmount);
         Variable *T = makeReg(DestTy);
         _movp(T, Src0RM);
         _psll(T, ShiftConstant);
         _psra(T, ShiftConstant);
         _movp(Dest, T);
       }
     } else if (Dest->getType() == IceType_i64) {
       // t1=movsx src; t2=t1; t2=sar t2, 31; dst.lo=t1; dst.hi=t2
       Constant *Shift = Ctx->getConstantInt32(31);
@@ skipping 14 matching lines @@
       _mov(T_Hi, T_Lo);
       if (Src0RM->getType() != IceType_i1)
         // For i1, the sar instruction is already done above.
         _sar(T_Hi, Shift);
       _mov(DestHi, T_Hi);
     } else if (Src0RM->getType() == IceType_i1) {
       // t1 = src
       // shl t1, dst_bitwidth - 1
       // sar t1, dst_bitwidth - 1
       // dst = t1
-      size_t DestBits = X86_CHAR_BIT * typeWidthInBytes(Dest->getType());
+      size_t DestBits =
+          Traits::X86_CHAR_BIT * typeWidthInBytes(Dest->getType());
       Constant *ShiftAmount = Ctx->getConstantInt32(DestBits - 1);
       Variable *T = makeReg(Dest->getType());
       if (typeWidthInBytes(Dest->getType()) <=
           typeWidthInBytes(Src0RM->getType())) {
         _mov(T, Src0RM);
       } else {
         // Widen the source using movsx or movzx.  (It doesn't matter
         // which one, since the following shl/sar overwrite the bits.)
         _movzx(T, Src0RM);
       }
@@ skipping 384 matching lines @@
     case IceType_v4i32:
     case IceType_v4f32: {
       _movp(Dest, legalizeToVar(Src0));
     } break;
     }
     break;
   }
   }
 }
 
-void TargetX8632::lowerExtractElement(const InstExtractElement *Inst) {
+template <class Machine>
+void TargetX86Base<Machine>::lowerExtractElement(
+    const InstExtractElement *Inst) {
   Operand *SourceVectNotLegalized = Inst->getSrc(0);
   ConstantInteger32 *ElementIndex =
       llvm::dyn_cast<ConstantInteger32>(Inst->getSrc(1));
   // Only constant indices are allowed in PNaCl IR.
   assert(ElementIndex);
 
   unsigned Index = ElementIndex->getValue();
   Type Ty = SourceVectNotLegalized->getType();
   Type ElementTy = typeElementType(Ty);
-  Type InVectorElementTy = getInVectorElementType(Ty);
+  Type InVectorElementTy = Traits::getInVectorElementType(Ty);
   Variable *ExtractedElementR = makeReg(InVectorElementTy);
 
   // TODO(wala): Determine the best lowering sequences for each type.
-  bool CanUsePextr =
-      Ty == IceType_v8i16 || Ty == IceType_v8i1 || InstructionSet >= SSE4_1;
+  bool CanUsePextr = Ty == IceType_v8i16 || Ty == IceType_v8i1 ||
+                     InstructionSet >= Machine::SSE4_1;
   if (CanUsePextr && Ty != IceType_v4f32) {
     // Use pextrb, pextrw, or pextrd.
     Constant *Mask = Ctx->getConstantInt32(Index);
     Variable *SourceVectR = legalizeToVar(SourceVectNotLegalized);
     _pextr(ExtractedElementR, SourceVectR, Mask);
   } else if (Ty == IceType_v4i32 || Ty == IceType_v4f32 || Ty == IceType_v4i1) {
     // Use pshufd and movd/movss.
     Variable *T = nullptr;
     if (Index) {
       // The shuffle only needs to occur if the element to be extracted
@@ skipping 40 matching lines @@
         InstCast::create(Func, InstCast::Trunc, T, ExtractedElementR);
     lowerCast(Cast);
     ExtractedElementR = T;
   }
 
   // Copy the element to the destination.
   Variable *Dest = Inst->getDest();
   _mov(Dest, ExtractedElementR);
 }
 
-void TargetX8632::lowerFcmp(const InstFcmp *Inst) {
+template <class Machine>
+void TargetX86Base<Machine>::lowerFcmp(const InstFcmp *Inst) {
   Operand *Src0 = Inst->getSrc(0);
   Operand *Src1 = Inst->getSrc(1);
   Variable *Dest = Inst->getDest();
 
   if (isVectorType(Dest->getType())) {
     InstFcmp::FCond Condition = Inst->getCondition();
     size_t Index = static_cast<size_t>(Condition);
-    assert(Index < TableFcmpSize);
+    assert(Index < Traits::TableFcmpSize);
 
-    if (TableFcmp[Index].SwapVectorOperands) {
+    if (Traits::TableFcmp[Index].SwapVectorOperands) {
       Operand *T = Src0;
       Src0 = Src1;
       Src1 = T;
     }
 
     Variable *T = nullptr;
 
     if (Condition == InstFcmp::True) {
       // makeVectorOfOnes() requires an integer vector type.
       T = makeVectorOfMinusOnes(IceType_v4i32);
     } else if (Condition == InstFcmp::False) {
       T = makeVectorOfZeros(Dest->getType());
     } else {
       Operand *Src0RM = legalize(Src0, Legal_Reg | Legal_Mem);
       Operand *Src1RM = legalize(Src1, Legal_Reg | Legal_Mem);
       if (llvm::isa<OperandX8632Mem>(Src1RM))
         Src1RM = legalizeToVar(Src1RM);
 
       switch (Condition) {
       default: {
-        CondX86::CmppsCond Predicate = TableFcmp[Index].Predicate;
+        CondX86::CmppsCond Predicate = Traits::TableFcmp[Index].Predicate;
         assert(Predicate != CondX86::Cmpps_Invalid);
         T = makeReg(Src0RM->getType());
         _movp(T, Src0RM);
         _cmpps(T, Src1RM, Predicate);
       } break;
       case InstFcmp::One: {
         // Check both unequal and ordered.
         T = makeReg(Src0RM->getType());
         Variable *T2 = makeReg(Src0RM->getType());
         _movp(T, Src0RM);
@@ skipping 28 matching lines @@
   //   j<C2> label        /* only if C2 != Br_None */
   //   FakeUse(a)         /* only if C1 != Br_None */
   //   mov a, !<default>  /* only if C1 != Br_None */
   //   label:             /* only if C1 != Br_None */
   //
   // setcc lowering when C1 != Br_None && C2 == Br_None:
   //   ucomiss b, c       /* but swap b,c order if SwapOperands==true */
   //   setcc a, C1
   InstFcmp::FCond Condition = Inst->getCondition();
   size_t Index = static_cast<size_t>(Condition);
-  assert(Index < TableFcmpSize);
-  if (TableFcmp[Index].SwapScalarOperands)
+  assert(Index < Traits::TableFcmpSize);
+  if (Traits::TableFcmp[Index].SwapScalarOperands)
     std::swap(Src0, Src1);
-  bool HasC1 = (TableFcmp[Index].C1 != CondX86::Br_None);
-  bool HasC2 = (TableFcmp[Index].C2 != CondX86::Br_None);
+  bool HasC1 = (Traits::TableFcmp[Index].C1 != CondX86::Br_None);
+  bool HasC2 = (Traits::TableFcmp[Index].C2 != CondX86::Br_None);
   if (HasC1) {
     Src0 = legalize(Src0);
     Operand *Src1RM = legalize(Src1, Legal_Reg | Legal_Mem);
     Variable *T = nullptr;
     _mov(T, Src0);
     _ucomiss(T, Src1RM);
     if (!HasC2) {
-      assert(TableFcmp[Index].Default);
-      _setcc(Dest, TableFcmp[Index].C1);
+      assert(Traits::TableFcmp[Index].Default);
+      _setcc(Dest, Traits::TableFcmp[Index].C1);
       return;
     }
   }
-  Constant *Default = Ctx->getConstantInt32(TableFcmp[Index].Default);
+  Constant *Default = Ctx->getConstantInt32(Traits::TableFcmp[Index].Default);
   _mov(Dest, Default);
   if (HasC1) {
     InstX8632Label *Label = InstX8632Label::create(Func, this);
-    _br(TableFcmp[Index].C1, Label);
+    _br(Traits::TableFcmp[Index].C1, Label);
     if (HasC2) {
-      _br(TableFcmp[Index].C2, Label);
+      _br(Traits::TableFcmp[Index].C2, Label);
     }
-    Constant *NonDefault = Ctx->getConstantInt32(!TableFcmp[Index].Default);
+    Constant *NonDefault =
+        Ctx->getConstantInt32(!Traits::TableFcmp[Index].Default);
     _mov_nonkillable(Dest, NonDefault);
     Context.insert(Label);
   }
 }
 
-void TargetX8632::lowerIcmp(const InstIcmp *Inst) {
+template <class Machine>
+void TargetX86Base<Machine>::lowerIcmp(const InstIcmp *Inst) {
   Operand *Src0 = legalize(Inst->getSrc(0));
   Operand *Src1 = legalize(Inst->getSrc(1));
   Variable *Dest = Inst->getDest();
 
   if (isVectorType(Dest->getType())) {
     Type Ty = Src0->getType();
     // Promote i1 vectors to 128 bit integer vector types.
     if (typeElementType(Ty) == IceType_i1) {
       Type NewTy = IceType_NUM;
       switch (Ty) {
@@ skipping 97 matching lines @@
 
     _movp(Dest, T);
     eliminateNextVectorSextInstruction(Dest);
     return;
   }
 
   // a=icmp cond, b, c ==> cmp b,c; a=1; br cond,L1; FakeUse(a); a=0; L1:
   if (Src0->getType() == IceType_i64) {
     InstIcmp::ICond Condition = Inst->getCondition();
     size_t Index = static_cast<size_t>(Condition);
-    assert(Index < TableIcmp64Size);
+    assert(Index < Traits::TableIcmp64Size);
     Operand *Src0LoRM = legalize(loOperand(Src0), Legal_Reg | Legal_Mem);
     Operand *Src0HiRM = legalize(hiOperand(Src0), Legal_Reg | Legal_Mem);
     Operand *Src1LoRI = legalize(loOperand(Src1), Legal_Reg | Legal_Imm);
     Operand *Src1HiRI = legalize(hiOperand(Src1), Legal_Reg | Legal_Imm);
     Constant *Zero = Ctx->getConstantZero(IceType_i32);
     Constant *One = Ctx->getConstantInt32(1);
     InstX8632Label *LabelFalse = InstX8632Label::create(Func, this);
     InstX8632Label *LabelTrue = InstX8632Label::create(Func, this);
     _mov(Dest, One);
     _cmp(Src0HiRM, Src1HiRI);
-    if (TableIcmp64[Index].C1 != CondX86::Br_None)
-      _br(TableIcmp64[Index].C1, LabelTrue);
-    if (TableIcmp64[Index].C2 != CondX86::Br_None)
-      _br(TableIcmp64[Index].C2, LabelFalse);
+    if (Traits::TableIcmp64[Index].C1 != CondX86::Br_None)
+      _br(Traits::TableIcmp64[Index].C1, LabelTrue);
+    if (Traits::TableIcmp64[Index].C2 != CondX86::Br_None)
+      _br(Traits::TableIcmp64[Index].C2, LabelFalse);
     _cmp(Src0LoRM, Src1LoRI);
-    _br(TableIcmp64[Index].C3, LabelTrue);
+    _br(Traits::TableIcmp64[Index].C3, LabelTrue);
     Context.insert(LabelFalse);
     _mov_nonkillable(Dest, Zero);
     Context.insert(LabelTrue);
     return;
   }
 
   // cmp b, c
   Operand *Src0RM = legalizeSrc0ForCmp(Src0, Src1);
   _cmp(Src0RM, Src1);
-  _setcc(Dest, getIcmp32Mapping(Inst->getCondition()));
+  _setcc(Dest, Traits::getIcmp32Mapping(Inst->getCondition()));
 }
 
-void TargetX8632::lowerInsertElement(const InstInsertElement *Inst) {
+template <class Machine>
+void TargetX86Base<Machine>::lowerInsertElement(const InstInsertElement *Inst) {
   Operand *SourceVectNotLegalized = Inst->getSrc(0);
   Operand *ElementToInsertNotLegalized = Inst->getSrc(1);
   ConstantInteger32 *ElementIndex =
       llvm::dyn_cast<ConstantInteger32>(Inst->getSrc(2));
   // Only constant indices are allowed in PNaCl IR.
   assert(ElementIndex);
   unsigned Index = ElementIndex->getValue();
   assert(Index < typeNumElements(SourceVectNotLegalized->getType()));
 
   Type Ty = SourceVectNotLegalized->getType();
   Type ElementTy = typeElementType(Ty);
-  Type InVectorElementTy = getInVectorElementType(Ty);
+  Type InVectorElementTy = Traits::getInVectorElementType(Ty);
 
   if (ElementTy == IceType_i1) {
     // Expand the element to the appropriate size for it to be inserted
     // in the vector.
     Variable *Expanded = Func->makeVariable(InVectorElementTy);
     InstCast *Cast = InstCast::create(Func, InstCast::Zext, Expanded,
                                       ElementToInsertNotLegalized);
     lowerCast(Cast);
     ElementToInsertNotLegalized = Expanded;
   }
 
-  if (Ty == IceType_v8i16 || Ty == IceType_v8i1 || InstructionSet >= SSE4_1) {
+  if (Ty == IceType_v8i16 || Ty == IceType_v8i1 ||
+      InstructionSet >= Machine::SSE4_1) {
     // Use insertps, pinsrb, pinsrw, or pinsrd.
     Operand *ElementRM =
         legalize(ElementToInsertNotLegalized, Legal_Reg | Legal_Mem);
     Operand *SourceVectRM =
         legalize(SourceVectNotLegalized, Legal_Reg | Legal_Mem);
     Variable *T = makeReg(Ty);
     _movp(T, SourceVectRM);
     if (Ty == IceType_v4f32)
       _insertps(T, ElementRM, Ctx->getConstantInt32(Index << 4));
     else
@@ skipping 78 matching lines @@
     OperandX8632Mem *Loc =
         getMemoryOperandForStackSlot(InVectorElementTy, Slot, Offset);
     _store(legalizeToVar(ElementToInsertNotLegalized), Loc);
 
     Variable *T = makeReg(Ty);
     _movp(T, Slot);
     _movp(Inst->getDest(), T);
   }
 }
 
-void TargetX8632::lowerIntrinsicCall(const InstIntrinsicCall *Instr) {
+template <class Machine>
+void TargetX86Base<Machine>::lowerIntrinsicCall(
+    const InstIntrinsicCall *Instr) {
   switch (Intrinsics::IntrinsicID ID = Instr->getIntrinsicInfo().ID) {
   case Intrinsics::AtomicCmpxchg: {
     if (!Intrinsics::isMemoryOrderValid(
             ID, getConstantMemoryOrder(Instr->getArg(3)),
             getConstantMemoryOrder(Instr->getArg(4)))) {
       Func->setError("Unexpected memory ordering for AtomicCmpxchg");
       return;
     }
     Variable *DestPrev = Instr->getDest();
     Operand *PtrToMem = Instr->getArg(0);
@@ skipping 82 matching lines @@
     Context.insert(
         InstFakeUse::create(Func, Context.getLastInserted()->getDest()));
     return;
   }
   case Intrinsics::AtomicRMW:
     if (!Intrinsics::isMemoryOrderValid(
             ID, getConstantMemoryOrder(Instr->getArg(3)))) {
       Func->setError("Unexpected memory ordering for AtomicRMW");
       return;
     }
-    lowerAtomicRMW(
-        Instr->getDest(),
-        static_cast<uint32_t>(
-            llvm::cast<ConstantInteger32>(Instr->getArg(0))->getValue()),
-        Instr->getArg(1), Instr->getArg(2));
+    lowerAtomicRMW(Instr->getDest(),
+                   static_cast<uint32_t>(llvm::cast<ConstantInteger32>(
+                                             Instr->getArg(0))->getValue()),
+                   Instr->getArg(1), Instr->getArg(2));
     return;
   case Intrinsics::AtomicStore: {
     if (!Intrinsics::isMemoryOrderValid(
             ID, getConstantMemoryOrder(Instr->getArg(2)))) {
       Func->setError("Unexpected memory ordering for AtomicStore");
       return;
     }
     // We require the memory address to be naturally aligned.
     // Given that is the case, then normal stores are atomic.
     // Add a fence after the store to make it visible.
@@ skipping 205 matching lines @@
   case Intrinsics::Trap:
     _ud2();
     return;
   case Intrinsics::UnknownIntrinsic:
     Func->setError("Should not be lowering UnknownIntrinsic");
     return;
   }
   return;
 }
 
-void TargetX8632::lowerAtomicCmpxchg(Variable *DestPrev, Operand *Ptr,
-                                     Operand *Expected, Operand *Desired) {
+template <class Machine>
+void TargetX86Base<Machine>::lowerAtomicCmpxchg(Variable *DestPrev,
+                                                Operand *Ptr, Operand *Expected,
+                                                Operand *Desired) {
   if (Expected->getType() == IceType_i64) {
     // Reserve the pre-colored registers first, before adding any more
     // infinite-weight variables from formMemoryOperand's legalization.
     Variable *T_edx = makeReg(IceType_i32, RegX8632::Reg_edx);
     Variable *T_eax = makeReg(IceType_i32, RegX8632::Reg_eax);
     Variable *T_ecx = makeReg(IceType_i32, RegX8632::Reg_ecx);
     Variable *T_ebx = makeReg(IceType_i32, RegX8632::Reg_ebx);
     _mov(T_eax, loOperand(Expected));
     _mov(T_edx, hiOperand(Expected));
     _mov(T_ebx, loOperand(Desired));
     _mov(T_ecx, hiOperand(Desired));
     OperandX8632Mem *Addr = formMemoryOperand(Ptr, Expected->getType());
     const bool Locked = true;
     _cmpxchg8b(Addr, T_edx, T_eax, T_ecx, T_ebx, Locked);
     Variable *DestLo = llvm::cast<Variable>(loOperand(DestPrev));
     Variable *DestHi = llvm::cast<Variable>(hiOperand(DestPrev));
     _mov(DestLo, T_eax);
     _mov(DestHi, T_edx);
     return;
   }
   Variable *T_eax = makeReg(Expected->getType(), RegX8632::Reg_eax);
   _mov(T_eax, Expected);
   OperandX8632Mem *Addr = formMemoryOperand(Ptr, Expected->getType());
   Variable *DesiredReg = legalizeToVar(Desired);
   const bool Locked = true;
   _cmpxchg(Addr, T_eax, DesiredReg, Locked);
   _mov(DestPrev, T_eax);
 }
 
-bool TargetX8632::tryOptimizedCmpxchgCmpBr(Variable *Dest, Operand *PtrToMem,
-                                           Operand *Expected,
-                                           Operand *Desired) {
+template <class Machine>
+bool TargetX86Base<Machine>::tryOptimizedCmpxchgCmpBr(Variable *Dest,
+                                                      Operand *PtrToMem,
+                                                      Operand *Expected,
+                                                      Operand *Desired) {
   if (Ctx->getFlags().getOptLevel() == Opt_m1)
     return false;
   // Peek ahead a few instructions and see how Dest is used.
   // It's very common to have:
   //
   // %x = call i32 @llvm.nacl.atomic.cmpxchg.i32(i32* ptr, i32 %expected, ...)
   // [%y_phi = ...] // list of phi stores
   // %p = icmp eq i32 %x, %expected
   // br i1 %p, label %l1, label %l2
   //
@@ skipping 50 matching lines @@
         NextBr->setDeleted();
         Context.advanceNext();
         Context.advanceNext();
         return true;
       }
     }
   }
   return false;
 }
 
-void TargetX8632::lowerAtomicRMW(Variable *Dest, uint32_t Operation,
-                                 Operand *Ptr, Operand *Val) {
+template <class Machine>
+void TargetX86Base<Machine>::lowerAtomicRMW(Variable *Dest, uint32_t Operation,
+                                            Operand *Ptr, Operand *Val) {
   bool NeedsCmpxchg = false;
   LowerBinOp Op_Lo = nullptr;
   LowerBinOp Op_Hi = nullptr;
   switch (Operation) {
   default:
     Func->setError("Unknown AtomicRMW operation");
     return;
   case Intrinsics::AtomicAdd: {
     if (Dest->getType() == IceType_i64) {
       // All the fall-through paths must set this to true, but use this
       // for asserting.
       NeedsCmpxchg = true;
-      Op_Lo = &TargetX8632::_add;
-      Op_Hi = &TargetX8632::_adc;
+      Op_Lo = &TargetX86Base<Machine>::_add;
+      Op_Hi = &TargetX86Base<Machine>::_adc;
       break;
     }
     OperandX8632Mem *Addr = formMemoryOperand(Ptr, Dest->getType());
     const bool Locked = true;
     Variable *T = nullptr;
     _mov(T, Val);
     _xadd(Addr, T, Locked);
     _mov(Dest, T);
     return;
   }
   case Intrinsics::AtomicSub: {
     if (Dest->getType() == IceType_i64) {
       NeedsCmpxchg = true;
-      Op_Lo = &TargetX8632::_sub;
-      Op_Hi = &TargetX8632::_sbb;
+      Op_Lo = &TargetX86Base<Machine>::_sub;
+      Op_Hi = &TargetX86Base<Machine>::_sbb;
       break;
     }
     OperandX8632Mem *Addr = formMemoryOperand(Ptr, Dest->getType());
     const bool Locked = true;
     Variable *T = nullptr;
     _mov(T, Val);
     _neg(T);
     _xadd(Addr, T, Locked);
     _mov(Dest, T);
     return;
   }
   case Intrinsics::AtomicOr:
     // TODO(jvoung): If Dest is null or dead, then some of these
     // operations do not need an "exchange", but just a locked op.
     // That appears to be "worth" it for sub, or, and, and xor.
     // xadd is probably fine vs lock add for add, and xchg is fine
     // vs an atomic store.
     NeedsCmpxchg = true;
-    Op_Lo = &TargetX8632::_or;
-    Op_Hi = &TargetX8632::_or;
+    Op_Lo = &TargetX86Base<Machine>::_or;
+    Op_Hi = &TargetX86Base<Machine>::_or;
     break;
   case Intrinsics::AtomicAnd:
     NeedsCmpxchg = true;
-    Op_Lo = &TargetX8632::_and;
-    Op_Hi = &TargetX8632::_and;
+    Op_Lo = &TargetX86Base<Machine>::_and;
+    Op_Hi = &TargetX86Base<Machine>::_and;
     break;
   case Intrinsics::AtomicXor:
     NeedsCmpxchg = true;
-    Op_Lo = &TargetX8632::_xor;
-    Op_Hi = &TargetX8632::_xor;
+    Op_Lo = &TargetX86Base<Machine>::_xor;
+    Op_Hi = &TargetX86Base<Machine>::_xor;
     break;
   case Intrinsics::AtomicExchange:
     if (Dest->getType() == IceType_i64) {
       NeedsCmpxchg = true;
       // NeedsCmpxchg, but no real Op_Lo/Op_Hi need to be done. The values
       // just need to be moved to the ecx and ebx registers.
       Op_Lo = nullptr;
       Op_Hi = nullptr;
       break;
     }
     OperandX8632Mem *Addr = formMemoryOperand(Ptr, Dest->getType());
     Variable *T = nullptr;
     _mov(T, Val);
     _xchg(Addr, T);
     _mov(Dest, T);
     return;
   }
   // Otherwise, we need a cmpxchg loop.
   (void)NeedsCmpxchg;
   assert(NeedsCmpxchg);
   expandAtomicRMWAsCmpxchg(Op_Lo, Op_Hi, Dest, Ptr, Val);
 }
 
-void TargetX8632::expandAtomicRMWAsCmpxchg(LowerBinOp Op_Lo, LowerBinOp Op_Hi,
-                                           Variable *Dest, Operand *Ptr,
-                                           Operand *Val) {
+template <class Machine>
+void TargetX86Base<Machine>::expandAtomicRMWAsCmpxchg(LowerBinOp Op_Lo,
+                                                      LowerBinOp Op_Hi,
+                                                      Variable *Dest,
+                                                      Operand *Ptr,
+                                                      Operand *Val) {
   // Expand a more complex RMW operation as a cmpxchg loop:
   // For 64-bit:
   //   mov     eax, [ptr]
   //   mov     edx, [ptr + 4]
   // .LABEL:
   //   mov     ebx, eax
   //   <Op_Lo> ebx, <desired_adj_lo>
   //   mov     ecx, edx
   //   <Op_Hi> ecx, <desired_adj_hi>
   //   lock cmpxchg8b [ptr]
@@ skipping 84 matching lines @@
   // The address base (if any) is also reused in the loop.
   if (Variable *Base = Addr->getBase())
     Context.insert(InstFakeUse::create(Func, Base));
   _mov(Dest, T_eax);
 }
 
 // Lowers count {trailing, leading} zeros intrinsic.
 //
 // We could do constant folding here, but that should have
 // been done by the front-end/middle-end optimizations.
-void TargetX8632::lowerCountZeros(bool Cttz, Type Ty, Variable *Dest,
-                                  Operand *FirstVal, Operand *SecondVal) {
+template <class Machine>
+void TargetX86Base<Machine>::lowerCountZeros(bool Cttz, Type Ty, Variable *Dest,
+                                             Operand *FirstVal,
+                                             Operand *SecondVal) {
   // TODO(jvoung): Determine if the user CPU supports LZCNT (BMI).
   // Then the instructions will handle the Val == 0 case much more simply
   // and won't require conversion from bit position to number of zeros.
   //
   // Otherwise:
   //   bsr IF_NOT_ZERO, Val
   //   mov T_DEST, 63
   //   cmovne T_DEST, IF_NOT_ZERO
   //   xor T_DEST, 31
   //   mov DEST, T_DEST
@@ skipping 50 matching lines @@
   } else {
     _bsr(T_Dest2, SecondVar);
     _xor(T_Dest2, ThirtyOne);
   }
   _test(SecondVar, SecondVar);
   _cmov(T_Dest2, T_Dest, CondX86::Br_e);
   _mov(DestLo, T_Dest2);
   _mov(DestHi, Ctx->getConstantZero(IceType_i32));
 }
 
-namespace {
-
 bool isAdd(const Inst *Inst) {
   if (const InstArithmetic *Arith =
           llvm::dyn_cast_or_null<const InstArithmetic>(Inst)) {
     return (Arith->getOp() == InstArithmetic::Add);
   }
   return false;
 }
 
 void dumpAddressOpt(const Cfg *Func, const Variable *Base,
                     const Variable *Index, uint16_t Shift, int32_t Offset,
@@ skipping 220 matching lines @@
     //   set Index=Var, Offset+=(Const<<Shift)
 
     // Index is Index=Var-Const ==>
     //   set Index=Var, Offset-=(Const<<Shift)
 
     // TODO: consider overflow issues with respect to Offset.
     // TODO: handle symbolic constants.
   }
 }
 
-} // anonymous namespace
-
-void TargetX8632::lowerLoad(const InstLoad *Load) {
+template <class Machine>
+void TargetX86Base<Machine>::lowerLoad(const InstLoad *Load) {
   // A Load instruction can be treated the same as an Assign
   // instruction, after the source operand is transformed into an
   // OperandX8632Mem operand.  Note that the address mode
   // optimization already creates an OperandX8632Mem operand, so it
   // doesn't need another level of transformation.
   Variable *DestLoad = Load->getDest();
   Type Ty = DestLoad->getType();
   Operand *Src0 = formMemoryOperand(Load->getSourceAddress(), Ty);
   InstAssign *Assign = InstAssign::create(Func, DestLoad, Src0);
   lowerAssign(Assign);
 }
 
-void TargetX8632::doAddressOptLoad() {
+template <class Machine> void TargetX86Base<Machine>::doAddressOptLoad() {
   Inst *Inst = Context.getCur();
   Variable *Dest = Inst->getDest();
   Operand *Addr = Inst->getSrc(0);
   Variable *Index = nullptr;
   uint16_t Shift = 0;
   int32_t Offset = 0; // TODO: make Constant
   // Vanilla ICE load instructions should not use the segment registers,
   // and computeAddressOpt only works at the level of Variables and Constants,
   // not other OperandX8632Mem, so there should be no mention of segment
   // registers there either.
   const OperandX8632Mem::SegmentRegisters SegmentReg =
       OperandX8632Mem::DefaultSegment;
   Variable *Base = llvm::dyn_cast<Variable>(Addr);
   computeAddressOpt(Func, Inst, Base, Index, Shift, Offset);
   if (Base && Addr != Base) {
     Inst->setDeleted();
     Constant *OffsetOp = Ctx->getConstantInt32(Offset);
     Addr = OperandX8632Mem::create(Func, Dest->getType(), Base, OffsetOp, Index,
                                    Shift, SegmentReg);
     Context.insert(InstLoad::create(Func, Dest, Addr));
   }
 }
 
-void TargetX8632::randomlyInsertNop(float Probability) {
+template <class Machine>
+void TargetX86Base<Machine>::randomlyInsertNop(float Probability) {
   RandomNumberGeneratorWrapper RNG(Ctx->getRNG());
   if (RNG.getTrueWithProbability(Probability)) {
-    _nop(RNG(X86_NUM_NOP_VARIANTS));
+    _nop(RNG(Traits::X86_NUM_NOP_VARIANTS));
   }
 }
 
-void TargetX8632::lowerPhi(const InstPhi * /*Inst*/) {
+template <class Machine>
+void TargetX86Base<Machine>::lowerPhi(const InstPhi * /*Inst*/) {
   Func->setError("Phi found in regular instruction list");
 }
 
-void TargetX8632::lowerRet(const InstRet *Inst) {
+template <class Machine>
+void TargetX86Base<Machine>::lowerRet(const InstRet *Inst) {
   Variable *Reg = nullptr;
   if (Inst->hasRetValue()) {
     Operand *Src0 = legalize(Inst->getRetValue());
     if (Src0->getType() == IceType_i64) {
       Variable *eax = legalizeToVar(loOperand(Src0), RegX8632::Reg_eax);
       Variable *edx = legalizeToVar(hiOperand(Src0), RegX8632::Reg_edx);
       Reg = eax;
       Context.insert(InstFakeUse::create(Func, edx));
     } else if (isScalarFloatingType(Src0->getType())) {
       _fld(Src0);
     } else if (isVectorType(Src0->getType())) {
       Reg = legalizeToVar(Src0, RegX8632::Reg_xmm0);
     } else {
       _mov(Reg, Src0, RegX8632::Reg_eax);
     }
   }
   // Add a ret instruction even if sandboxing is enabled, because
   // addEpilog explicitly looks for a ret instruction as a marker for
   // where to insert the frame removal instructions.
   _ret(Reg);
   // Add a fake use of esp to make sure esp stays alive for the entire
   // function.  Otherwise post-call esp adjustments get dead-code
   // eliminated.  TODO: Are there more places where the fake use
   // should be inserted?  E.g. "void f(int n){while(1) g(n);}" may not
   // have a ret instruction.
   Variable *esp = Func->getTarget()->getPhysicalRegister(RegX8632::Reg_esp);
   Context.insert(InstFakeUse::create(Func, esp));
 }
 
-void TargetX8632::lowerSelect(const InstSelect *Inst) {
+template <class Machine>
+void TargetX86Base<Machine>::lowerSelect(const InstSelect *Inst) {
   Variable *Dest = Inst->getDest();
   Type DestTy = Dest->getType();
   Operand *SrcT = Inst->getTrueOperand();
   Operand *SrcF = Inst->getFalseOperand();
   Operand *Condition = Inst->getCondition();
 
   if (isVectorType(DestTy)) {
     Type SrcTy = SrcT->getType();
     Variable *T = makeReg(SrcTy);
     Operand *SrcTRM = legalize(SrcT, Legal_Reg | Legal_Mem);
     Operand *SrcFRM = legalize(SrcF, Legal_Reg | Legal_Mem);
-    if (InstructionSet >= SSE4_1) {
+    if (InstructionSet >= Machine::SSE4_1) {
       // TODO(wala): If the condition operand is a constant, use blendps
       // or pblendw.
       //
       // Use blendvps or pblendvb to implement select.
       if (SrcTy == IceType_v4i1 || SrcTy == IceType_v4i32 ||
           SrcTy == IceType_v4f32) {
         Operand *ConditionRM = legalize(Condition, Legal_Reg | Legal_Mem);
         Variable *xmm0 = makeReg(IceType_v4i32, RegX8632::Reg_xmm0);
         _movp(xmm0, ConditionRM);
         _psll(xmm0, Ctx->getConstantInt8(31));
         _movp(T, SrcFRM);
         _blendvps(T, SrcTRM, xmm0);
         _movp(Dest, T);
       } else {
         assert(typeNumElements(SrcTy) == 8 || typeNumElements(SrcTy) == 16);
         Type SignExtTy = Condition->getType() == IceType_v8i1 ? IceType_v8i16
                                                               : IceType_v16i8;
         Variable *xmm0 = makeReg(SignExtTy, RegX8632::Reg_xmm0);
         lowerCast(InstCast::create(Func, InstCast::Sext, xmm0, Condition));
         _movp(T, SrcFRM);
         _pblendvb(T, SrcTRM, xmm0);
         _movp(Dest, T);
       }
       return;
     }
-    // Lower select without SSE4.1:
+    // Lower select without Machine::SSE4.1:
     // a=d?b:c ==>
     //   if elementtype(d) != i1:
     //      d=sext(d);
     //   a=(b&d)|(c&~d);
     Variable *T2 = makeReg(SrcTy);
     // Sign extend the condition operand if applicable.
     if (SrcTy == IceType_v4f32) {
       // The sext operation takes only integer arguments.
       Variable *T3 = Func->makeVariable(IceType_v4i32);
       lowerCast(InstCast::create(Func, InstCast::Sext, T3, Condition));
@@ skipping 17 matching lines @@
   Operand *CmpOpnd0 = nullptr;
   Operand *CmpOpnd1 = nullptr;
   // Handle folding opportunities.
   if (const class Inst *Producer = FoldingInfo.getProducerFor(Condition)) {
     assert(Producer->isDeleted());
     switch (BoolFolding::getProducerKind(Producer)) {
     default:
       break;
     case BoolFolding::PK_Icmp32: {
       auto *Cmp = llvm::dyn_cast<InstIcmp>(Producer);
-      Cond = getIcmp32Mapping(Cmp->getCondition());
+      Cond = Traits::getIcmp32Mapping(Cmp->getCondition());
       CmpOpnd1 = legalize(Producer->getSrc(1));
       CmpOpnd0 = legalizeSrc0ForCmp(Producer->getSrc(0), CmpOpnd1);
     } break;
     }
   }
   if (CmpOpnd0 == nullptr) {
     CmpOpnd0 = legalize(Condition, Legal_Reg | Legal_Mem);
     CmpOpnd1 = Ctx->getConstantZero(IceType_i32);
   }
   assert(CmpOpnd0);
@@ skipping 43 matching lines @@
 
   assert(DestTy == IceType_i16 || DestTy == IceType_i32);
   Variable *T = nullptr;
   SrcF = legalize(SrcF);
   _mov(T, SrcF);
   SrcT = legalize(SrcT, Legal_Reg | Legal_Mem);
   _cmov(T, SrcT, Cond);
   _mov(Dest, T);
 }
 
-void TargetX8632::lowerStore(const InstStore *Inst) {
+template <class Machine>
+void TargetX86Base<Machine>::lowerStore(const InstStore *Inst) {
   Operand *Value = Inst->getData();
   Operand *Addr = Inst->getAddr();
   OperandX8632Mem *NewAddr = formMemoryOperand(Addr, Value->getType());
   Type Ty = NewAddr->getType();
 
   if (Ty == IceType_i64) {
     Value = legalize(Value);
     Operand *ValueHi = legalize(hiOperand(Value), Legal_Reg | Legal_Imm);
     Operand *ValueLo = legalize(loOperand(Value), Legal_Reg | Legal_Imm);
     _store(ValueHi, llvm::cast<OperandX8632Mem>(hiOperand(NewAddr)));
     _store(ValueLo, llvm::cast<OperandX8632Mem>(loOperand(NewAddr)));
   } else if (isVectorType(Ty)) {
     _storep(legalizeToVar(Value), NewAddr);
   } else {
     Value = legalize(Value, Legal_Reg | Legal_Imm);
     _store(Value, NewAddr);
   }
 }
 
-void TargetX8632::doAddressOptStore() {
+template <class Machine> void TargetX86Base<Machine>::doAddressOptStore() {
   InstStore *Inst = llvm::cast<InstStore>(Context.getCur());
   Operand *Data = Inst->getData();
   Operand *Addr = Inst->getAddr();
   Variable *Index = nullptr;
   uint16_t Shift = 0;
   int32_t Offset = 0; // TODO: make Constant
   Variable *Base = llvm::dyn_cast<Variable>(Addr);
   // Vanilla ICE store instructions should not use the segment registers,
   // and computeAddressOpt only works at the level of Variables and Constants,
   // not other OperandX8632Mem, so there should be no mention of segment
   // registers there either.
   const OperandX8632Mem::SegmentRegisters SegmentReg =
       OperandX8632Mem::DefaultSegment;
   computeAddressOpt(Func, Inst, Base, Index, Shift, Offset);
   if (Base && Addr != Base) {
     Inst->setDeleted();
     Constant *OffsetOp = Ctx->getConstantInt32(Offset);
     Addr = OperandX8632Mem::create(Func, Data->getType(), Base, OffsetOp, Index,
                                    Shift, SegmentReg);
     InstStore *NewStore = InstStore::create(Func, Data, Addr);
     if (Inst->getDest())
       NewStore->setRmwBeacon(Inst->getRmwBeacon());
     Context.insert(NewStore);
   }
 }
 
-void TargetX8632::lowerSwitch(const InstSwitch *Inst) {
+template <class Machine>
+void TargetX86Base<Machine>::lowerSwitch(const InstSwitch *Inst) {
   // This implements the most naive possible lowering.
   // cmp a,val[0]; jeq label[0]; cmp a,val[1]; jeq label[1]; ... jmp default
   Operand *Src0 = Inst->getComparison();
   SizeT NumCases = Inst->getNumCases();
   if (Src0->getType() == IceType_i64) {
     Src0 = legalize(Src0); // get Base/Index into physical registers
     Operand *Src0Lo = loOperand(Src0);
     Operand *Src0Hi = hiOperand(Src0);
     if (NumCases >= 2) {
       Src0Lo = legalizeToVar(Src0Lo);
@@ skipping 23 matching lines @@
     Src0 = legalize(Src0, Legal_Reg | Legal_Mem);
   for (SizeT I = 0; I < NumCases; ++I) {
     Constant *Value = Ctx->getConstantInt32(Inst->getValue(I));
     _cmp(Src0, Value);
     _br(CondX86::Br_e, Inst->getLabel(I));
   }
 
   _br(Inst->getLabelDefault());
 }
 
-void TargetX8632::scalarizeArithmetic(InstArithmetic::OpKind Kind,
-                                      Variable *Dest, Operand *Src0,
-                                      Operand *Src1) {
+template <class Machine>
+void TargetX86Base<Machine>::scalarizeArithmetic(InstArithmetic::OpKind Kind,
+                                                 Variable *Dest, Operand *Src0,
+                                                 Operand *Src1) {
   assert(isVectorType(Dest->getType()));
   Type Ty = Dest->getType();
   Type ElementTy = typeElementType(Ty);
   SizeT NumElements = typeNumElements(Ty);
 
   Operand *T = Ctx->getConstantUndef(Ty);
   for (SizeT I = 0; I < NumElements; ++I) {
     Constant *Index = Ctx->getConstantInt32(I);
 
     // Extract the next two inputs.
@@ skipping 16 matching lines @@
 }
 
 // The following pattern occurs often in lowered C and C++ code:
 //
 //   %cmp     = fcmp/icmp pred <n x ty> %src0, %src1
 //   %cmp.ext = sext <n x i1> %cmp to <n x ty>
 //
 // We can eliminate the sext operation by copying the result of pcmpeqd,
 // pcmpgtd, or cmpps (which produce sign extended results) to the result
 // of the sext operation.
-void TargetX8632::eliminateNextVectorSextInstruction(
+template <class Machine>
+void TargetX86Base<Machine>::eliminateNextVectorSextInstruction(
     Variable *SignExtendedResult) {
   if (InstCast *NextCast =
           llvm::dyn_cast_or_null<InstCast>(Context.getNextInst())) {
     if (NextCast->getCastKind() == InstCast::Sext &&
         NextCast->getSrc(0) == SignExtendedResult) {
       NextCast->setDeleted();
       _movp(NextCast->getDest(), legalizeToVar(SignExtendedResult));
       // Skip over the instruction.
       Context.advanceNext();
     }
   }
 }
 
-void TargetX8632::lowerUnreachable(const InstUnreachable * /*Inst*/) { _ud2(); }
+template <class Machine>
+void TargetX86Base<Machine>::lowerUnreachable(
+    const InstUnreachable * /*Inst*/) {
+  _ud2();
+}
 
-void TargetX8632::lowerRMW(const InstX8632FakeRMW *RMW) {
+template <class Machine>
+void TargetX86Base<Machine>::lowerRMW(const InstX8632FakeRMW *RMW) {
   // If the beacon variable's live range does not end in this
   // instruction, then it must end in the modified Store instruction
   // that follows.  This means that the original Store instruction is
   // still there, either because the value being stored is used beyond
   // the Store instruction, or because dead code elimination did not
   // happen.  In either case, we cancel RMW lowering (and the caller
   // deletes the RMW instruction).
   if (!RMW->isLastUse(RMW->getBeacon()))
     return;
   Operand *Src = RMW->getData();
@@ skipping 53 matching lines @@
       return;
     case InstArithmetic::Xor:
       Src = legalize(Src, Legal_Reg | Legal_Imm);
       _xor_rmw(Addr, Src);
       return;
     }
   }
   llvm::report_fatal_error("Couldn't lower RMW instruction");
 }
 
-void TargetX8632::lowerOther(const Inst *Instr) {
+template <class Machine>
+void TargetX86Base<Machine>::lowerOther(const Inst *Instr) {
   if (const auto *RMW = llvm::dyn_cast<InstX8632FakeRMW>(Instr)) {
     lowerRMW(RMW);
   } else {
     TargetLowering::lowerOther(Instr);
   }
 }
 
 // Turn an i64 Phi instruction into a pair of i32 Phi instructions, to
 // preserve integrity of liveness analysis.  Undef values are also
 // turned into zeroes, since loOperand() and hiOperand() don't expect
 // Undef input.
-void TargetX8632::prelowerPhis() {
+template <class Machine> void TargetX86Base<Machine>::prelowerPhis() {
   // Pause constant blinding or pooling, blinding or pooling will be done later
   // during phi lowering assignments
   BoolFlagSaver B(RandomizationPoolingPaused, true);
 
   CfgNode *Node = Context.getNode();
   for (Inst &I : Node->getPhis()) {
     auto Phi = llvm::dyn_cast<InstPhi>(&I);
     if (Phi->isDeleted())
       continue;
     Variable *Dest = Phi->getDest();
@@ skipping 10 matching lines @@
         PhiLo->addArgument(loOperand(Src), Label);
         PhiHi->addArgument(hiOperand(Src), Label);
       }
       Node->getPhis().push_back(PhiLo);
       Node->getPhis().push_back(PhiHi);
       Phi->setDeleted();
     }
   }
 }
 
-namespace {
-
 bool isMemoryOperand(const Operand *Opnd) {
   if (const auto Var = llvm::dyn_cast<Variable>(Opnd))
     return !Var->hasReg();
   // We treat vector undef values the same as a memory operand,
   // because they do in fact need a register to materialize the vector
   // of zeroes into.
   if (llvm::isa<ConstantUndef>(Opnd))
     return isScalarFloatingType(Opnd->getType()) ||
            isVectorType(Opnd->getType());
   if (llvm::isa<Constant>(Opnd))
     return isScalarFloatingType(Opnd->getType());
   return true;
 }
 
-} // end of anonymous namespace
-
 // Lower the pre-ordered list of assignments into mov instructions.
 // Also has to do some ad-hoc register allocation as necessary.
-void TargetX8632::lowerPhiAssignments(CfgNode *Node,
-                                      const AssignList &Assignments) {
+template <class Machine>
+void TargetX86Base<Machine>::lowerPhiAssignments(
+    CfgNode *Node, const AssignList &Assignments) {
   // Check that this is a properly initialized shell of a node.
   assert(Node->getOutEdges().size() == 1);
   assert(Node->getInsts().empty());
   assert(Node->getPhis().empty());
   CfgNode *Succ = Node->getOutEdges().front();
   getContext().init(Node);
   // Register set setup similar to regAlloc().
   RegSetMask RegInclude = RegSet_All;
   RegSetMask RegExclude = RegSet_StackPointer;
   if (hasFramePointer())
@@ skipping 130 matching lines @@
   _br(Succ);
 }
 
 // There is no support for loading or emitting vector constants, so the
 // vector values returned from makeVectorOfZeros, makeVectorOfOnes,
 // etc. are initialized with register operations.
 //
 // TODO(wala): Add limited support for vector constants so that
 // complex initialization in registers is unnecessary.
 
-Variable *TargetX8632::makeVectorOfZeros(Type Ty, int32_t RegNum) {
+template <class Machine>
+Variable *TargetX86Base<Machine>::makeVectorOfZeros(Type Ty, int32_t RegNum) {
   Variable *Reg = makeReg(Ty, RegNum);
   // Insert a FakeDef, since otherwise the live range of Reg might
   // be overestimated.
   Context.insert(InstFakeDef::create(Func, Reg));
   _pxor(Reg, Reg);
   return Reg;
 }
 
-Variable *TargetX8632::makeVectorOfMinusOnes(Type Ty, int32_t RegNum) {
+template <class Machine>
+Variable *TargetX86Base<Machine>::makeVectorOfMinusOnes(Type Ty,
+                                                        int32_t RegNum) {
   Variable *MinusOnes = makeReg(Ty, RegNum);
   // Insert a FakeDef so the live range of MinusOnes is not overestimated.
   Context.insert(InstFakeDef::create(Func, MinusOnes));
   _pcmpeq(MinusOnes, MinusOnes);
   return MinusOnes;
 }
 
-Variable *TargetX8632::makeVectorOfOnes(Type Ty, int32_t RegNum) {
+template <class Machine>
+Variable *TargetX86Base<Machine>::makeVectorOfOnes(Type Ty, int32_t RegNum) {
   Variable *Dest = makeVectorOfZeros(Ty, RegNum);
   Variable *MinusOne = makeVectorOfMinusOnes(Ty);
   _psub(Dest, MinusOne);
   return Dest;
 }
 
-Variable *TargetX8632::makeVectorOfHighOrderBits(Type Ty, int32_t RegNum) {
+template <class Machine>
+Variable *TargetX86Base<Machine>::makeVectorOfHighOrderBits(Type Ty,
+                                                            int32_t RegNum) {
   assert(Ty == IceType_v4i32 || Ty == IceType_v4f32 || Ty == IceType_v8i16 ||
          Ty == IceType_v16i8);
   if (Ty == IceType_v4f32 || Ty == IceType_v4i32 || Ty == IceType_v8i16) {
     Variable *Reg = makeVectorOfOnes(Ty, RegNum);
-    SizeT Shift = typeWidthInBytes(typeElementType(Ty)) * X86_CHAR_BIT - 1;
+    SizeT Shift =
+        typeWidthInBytes(typeElementType(Ty)) * Traits::X86_CHAR_BIT - 1;
     _psll(Reg, Ctx->getConstantInt8(Shift));
     return Reg;
   } else {
     // SSE has no left shift operation for vectors of 8 bit integers.
     const uint32_t HIGH_ORDER_BITS_MASK = 0x80808080;
     Constant *ConstantMask = Ctx->getConstantInt32(HIGH_ORDER_BITS_MASK);
     Variable *Reg = makeReg(Ty, RegNum);
     _movd(Reg, legalize(ConstantMask, Legal_Reg | Legal_Mem));
     _pshufd(Reg, Reg, Ctx->getConstantZero(IceType_i8));
     return Reg;
   }
 }
 
 // Construct a mask in a register that can be and'ed with a
 // floating-point value to mask off its sign bit.  The value will be
 // <4 x 0x7fffffff> for f32 and v4f32, and <2 x 0x7fffffffffffffff>
 // for f64.  Construct it as vector of ones logically right shifted
 // one bit.  TODO(stichnot): Fix the wala TODO above, to represent
 // vector constants in memory.
-Variable *TargetX8632::makeVectorOfFabsMask(Type Ty, int32_t RegNum) {
+template <class Machine>
+Variable *TargetX86Base<Machine>::makeVectorOfFabsMask(Type Ty,
+                                                       int32_t RegNum) {
   Variable *Reg = makeVectorOfMinusOnes(Ty, RegNum);
   _psrl(Reg, Ctx->getConstantInt8(1));
   return Reg;
 }
 
-OperandX8632Mem *TargetX8632::getMemoryOperandForStackSlot(Type Ty,
-                                                           Variable *Slot,
-                                                           uint32_t Offset) {
+template <class Machine>
+OperandX8632Mem *
+TargetX86Base<Machine>::getMemoryOperandForStackSlot(Type Ty, Variable *Slot,
+                                                     uint32_t Offset) {
   // Ensure that Loc is a stack slot.
   assert(Slot->getWeight().isZero());
   assert(Slot->getRegNum() == Variable::NoRegister);
   // Compute the location of Loc in memory.
   // TODO(wala,stichnot): lea should not be required.  The address of
   // the stack slot is known at compile time (although not until after
   // addProlog()).
   const Type PointerType = IceType_i32;
   Variable *Loc = makeReg(PointerType);
   _lea(Loc, Slot);
   Constant *ConstantOffset = Ctx->getConstantInt32(Offset);
   return OperandX8632Mem::create(Func, Ty, Loc, ConstantOffset);
 }
 
 // Helper for legalize() to emit the right code to lower an operand to a
 // register of the appropriate type.
-Variable *TargetX8632::copyToReg(Operand *Src, int32_t RegNum) {
+template <class Machine>
+Variable *TargetX86Base<Machine>::copyToReg(Operand *Src, int32_t RegNum) {
   Type Ty = Src->getType();
   Variable *Reg = makeReg(Ty, RegNum);
   if (isVectorType(Ty)) {
     _movp(Reg, Src);
   } else {
     _mov(Reg, Src);
   }
   return Reg;
 }
 
-Operand *TargetX8632::legalize(Operand *From, LegalMask Allowed,
-                               int32_t RegNum) {
+template <class Machine>
+Operand *TargetX86Base<Machine>::legalize(Operand *From, LegalMask Allowed,
+                                          int32_t RegNum) {
   Type Ty = From->getType();
   // Assert that a physical register is allowed.  To date, all calls
   // to legalize() allow a physical register.  If a physical register
   // needs to be explicitly disallowed, then new code will need to be
   // written to force a spill.
   assert(Allowed & Legal_Reg);
   // If we're asking for a specific physical register, make sure we're
   // not allowing any other operand kinds.  (This could be future
   // work, e.g. allow the shl shift amount to be either an immediate
   // or in ecx.)
@@ skipping 92 matching lines @@
         (RegNum != Variable::NoRegister && RegNum != Var->getRegNum())) {
       From = copyToReg(From, RegNum);
     }
     return From;
   }
   llvm_unreachable("Unhandled operand kind in legalize()");
   return From;
 }
 
 // Provide a trivial wrapper to legalize() for this common usage.
-Variable *TargetX8632::legalizeToVar(Operand *From, int32_t RegNum) {
+template <class Machine>
+Variable *TargetX86Base<Machine>::legalizeToVar(Operand *From, int32_t RegNum) {
   return llvm::cast<Variable>(legalize(From, Legal_Reg, RegNum));
 }
 
 // For the cmp instruction, if Src1 is an immediate, or known to be a
 // physical register, we can allow Src0 to be a memory operand.
 // Otherwise, Src0 must be copied into a physical register.
 // (Actually, either Src0 or Src1 can be chosen for the physical
 // register, but unfortunately we have to commit to one or the other
 // before register allocation.)
-Operand *TargetX8632::legalizeSrc0ForCmp(Operand *Src0, Operand *Src1) {
+template <class Machine>
+Operand *TargetX86Base<Machine>::legalizeSrc0ForCmp(Operand *Src0,
+                                                    Operand *Src1) {
   bool IsSrc1ImmOrReg = false;
   if (llvm::isa<Constant>(Src1)) {
     IsSrc1ImmOrReg = true;
   } else if (Variable *Var = llvm::dyn_cast<Variable>(Src1)) {
     if (Var->hasReg())
       IsSrc1ImmOrReg = true;
   }
   return legalize(Src0, IsSrc1ImmOrReg ? (Legal_Reg | Legal_Mem) : Legal_Reg);
 }
 
-OperandX8632Mem *TargetX8632::formMemoryOperand(Operand *Opnd, Type Ty,
-                                                bool DoLegalize) {
+template <class Machine>
+OperandX8632Mem *TargetX86Base<Machine>::formMemoryOperand(Operand *Opnd,
+                                                           Type Ty,
+                                                           bool DoLegalize) {
   OperandX8632Mem *Mem = llvm::dyn_cast<OperandX8632Mem>(Opnd);
   // It may be the case that address mode optimization already creates
   // an OperandX8632Mem, so in that case it wouldn't need another level
   // of transformation.
   if (!Mem) {
     Variable *Base = llvm::dyn_cast<Variable>(Opnd);
     Constant *Offset = llvm::dyn_cast<Constant>(Opnd);
     assert(Base || Offset);
     if (Offset) {
       // During memory operand building, we do not blind or pool
@@ skipping 11 matching lines @@
              llvm::isa<ConstantRelocatable>(Offset));
     }
     Mem = OperandX8632Mem::create(Func, Ty, Base, Offset);
   }
   // Do legalization, which contains randomization/pooling
   // or do randomization/pooling.
   return llvm::cast<OperandX8632Mem>(
       DoLegalize ? legalize(Mem) : randomizeOrPoolImmediate(Mem));
 }
 
-Variable *TargetX8632::makeReg(Type Type, int32_t RegNum) {
+template <class Machine>
+Variable *TargetX86Base<Machine>::makeReg(Type Type, int32_t RegNum) {
   // There aren't any 64-bit integer registers for x86-32.
   assert(Type != IceType_i64);
   Variable *Reg = Func->makeVariable(Type);
   if (RegNum == Variable::NoRegister)
     Reg->setWeightInfinite();
   else
     Reg->setRegNum(RegNum);
   return Reg;
 }
 
-void TargetX8632::postLower() {
+template <class Machine> void TargetX86Base<Machine>::postLower() {
   if (Ctx->getFlags().getOptLevel() == Opt_m1)
     return;
   inferTwoAddress();
 }
 
-void TargetX8632::makeRandomRegisterPermutation(
+template <class Machine>
+void TargetX86Base<Machine>::makeRandomRegisterPermutation(
     llvm::SmallVectorImpl<int32_t> &Permutation,
     const llvm::SmallBitVector &ExcludeRegisters) const {
   // TODO(stichnot): Declaring Permutation this way loses type/size
   // information.  Fix this in conjunction with the caller-side TODO.
   assert(Permutation.size() >= RegX8632::Reg_NUM);
   // Expected upper bound on the number of registers in a single
   // equivalence class.  For x86-32, this would comprise the 8 XMM
   // registers.  This is for performance, not correctness.
   static const unsigned MaxEquivalenceClassSize = 8;
   typedef llvm::SmallVector<int32_t, MaxEquivalenceClassSize> RegisterList;
@@ skipping 46 matching lines @@
         if (!First)
           Str << " ";
         First = false;
         Str << getRegName(Register, IceType_i32);
       }
       Str << "}\n";
     }
   }
 }
 
-void TargetX8632::emit(const ConstantInteger32 *C) const {
+template <class Machine>
+void TargetX86Base<Machine>::emit(const ConstantInteger32 *C) const {
   if (!ALLOW_DUMP)
     return;
   Ostream &Str = Ctx->getStrEmit();
   Str << getConstantPrefix() << C->getValue();
 }
 
-void TargetX8632::emit(const ConstantInteger64 *) const {
+template <class Machine>
+void TargetX86Base<Machine>::emit(const ConstantInteger64 *) const {
   llvm::report_fatal_error("Not expecting to emit 64-bit integers");
 }
 
-void TargetX8632::emit(const ConstantFloat *C) const {
+template <class Machine>
+void TargetX86Base<Machine>::emit(const ConstantFloat *C) const {
   if (!ALLOW_DUMP)
     return;
   Ostream &Str = Ctx->getStrEmit();
   C->emitPoolLabel(Str);
 }
 
-void TargetX8632::emit(const ConstantDouble *C) const {
+template <class Machine>
+void TargetX86Base<Machine>::emit(const ConstantDouble *C) const {
   if (!ALLOW_DUMP)
     return;
   Ostream &Str = Ctx->getStrEmit();
   C->emitPoolLabel(Str);
 }
 
-void TargetX8632::emit(const ConstantUndef *) const {
+template <class Machine>
+void TargetX86Base<Machine>::emit(const ConstantUndef *) const {
   llvm::report_fatal_error("undef value encountered by emitter.");
 }
 
-TargetDataX8632::TargetDataX8632(GlobalContext *Ctx)
-    : TargetDataLowering(Ctx) {}
-
-void TargetDataX8632::lowerGlobals(const VariableDeclarationList &Vars,
-                                   const IceString &SectionSuffix) {
-  switch (Ctx->getFlags().getOutFileType()) {
-  case FT_Elf: {
-    ELFObjectWriter *Writer = Ctx->getObjectWriter();
-    Writer->writeDataSection(Vars, llvm::ELF::R_386_32, SectionSuffix);
-  } break;
-  case FT_Asm:
-  case FT_Iasm: {
-    const IceString &TranslateOnly = Ctx->getFlags().getTranslateOnly();
-    OstreamLocker L(Ctx);
-    for (const VariableDeclaration *Var : Vars) {
-      if (GlobalContext::matchSymbolName(Var->getName(), TranslateOnly)) {
-        emitGlobal(*Var, SectionSuffix);
-      }
-    }
-  } break;
-  }
-}
-
-template <typename T> struct PoolTypeConverter {};
-
-template <> struct PoolTypeConverter<float> {
-  typedef uint32_t PrimitiveIntType;
-  typedef ConstantFloat IceType;
-  static const Type Ty = IceType_f32;
-  static const char *TypeName;
-  static const char *AsmTag;
-  static const char *PrintfString;
-};
-const char *PoolTypeConverter<float>::TypeName = "float";
-const char *PoolTypeConverter<float>::AsmTag = ".long";
-const char *PoolTypeConverter<float>::PrintfString = "0x%x";
-
-template <> struct PoolTypeConverter<double> {
-  typedef uint64_t PrimitiveIntType;
-  typedef ConstantDouble IceType;
-  static const Type Ty = IceType_f64;
-  static const char *TypeName;
-  static const char *AsmTag;
-  static const char *PrintfString;
-};
-const char *PoolTypeConverter<double>::TypeName = "double";
-const char *PoolTypeConverter<double>::AsmTag = ".quad";
-const char *PoolTypeConverter<double>::PrintfString = "0x%llx";
-
-// Add converter for int type constant pooling
-template <> struct PoolTypeConverter<uint32_t> {
-  typedef uint32_t PrimitiveIntType;
-  typedef ConstantInteger32 IceType;
-  static const Type Ty = IceType_i32;
-  static const char *TypeName;
-  static const char *AsmTag;
-  static const char *PrintfString;
-};
-const char *PoolTypeConverter<uint32_t>::TypeName = "i32";
-const char *PoolTypeConverter<uint32_t>::AsmTag = ".long";
-const char *PoolTypeConverter<uint32_t>::PrintfString = "0x%x";
-
-// Add converter for int type constant pooling
-template <> struct PoolTypeConverter<uint16_t> {
-  typedef uint32_t PrimitiveIntType;
-  typedef ConstantInteger32 IceType;
-  static const Type Ty = IceType_i16;
-  static const char *TypeName;
-  static const char *AsmTag;
-  static const char *PrintfString;
-};
-const char *PoolTypeConverter<uint16_t>::TypeName = "i16";
-const char *PoolTypeConverter<uint16_t>::AsmTag = ".short";
-const char *PoolTypeConverter<uint16_t>::PrintfString = "0x%x";
-
-// Add converter for int type constant pooling
-template <> struct PoolTypeConverter<uint8_t> {
-  typedef uint32_t PrimitiveIntType;
-  typedef ConstantInteger32 IceType;
-  static const Type Ty = IceType_i8;
-  static const char *TypeName;
-  static const char *AsmTag;
-  static const char *PrintfString;
-};
-const char *PoolTypeConverter<uint8_t>::TypeName = "i8";
-const char *PoolTypeConverter<uint8_t>::AsmTag = ".byte";
-const char *PoolTypeConverter<uint8_t>::PrintfString = "0x%x";
-
-template <typename T>
-void TargetDataX8632::emitConstantPool(GlobalContext *Ctx) {
-  if (!ALLOW_DUMP)
-    return;
-  Ostream &Str = Ctx->getStrEmit();
-  Type Ty = T::Ty;
-  SizeT Align = typeAlignInBytes(Ty);
-  ConstantList Pool = Ctx->getConstantPool(Ty);
-
-  Str << "\t.section\t.rodata.cst" << Align << ",\"aM\",@progbits," << Align
-      << "\n";
-  Str << "\t.align\t" << Align << "\n";
-  for (Constant *C : Pool) {
-    if (!C->getShouldBePooled())
-      continue;
-    typename T::IceType *Const = llvm::cast<typename T::IceType>(C);
-    typename T::IceType::PrimType Value = Const->getValue();
-    // Use memcpy() to copy bits from Value into RawValue in a way
-    // that avoids breaking strict-aliasing rules.
-    typename T::PrimitiveIntType RawValue;
-    memcpy(&RawValue, &Value, sizeof(Value));
-    char buf[30];
-    int CharsPrinted =
-        snprintf(buf, llvm::array_lengthof(buf), T::PrintfString, RawValue);
-    assert(CharsPrinted >= 0 &&
-           (size_t)CharsPrinted < llvm::array_lengthof(buf));
-    (void)CharsPrinted; // avoid warnings if asserts are disabled
-    Const->emitPoolLabel(Str);
-    Str << ":\n\t" << T::AsmTag << "\t" << buf << "\t# " << T::TypeName << " "
-        << Value << "\n";
-  }
-}
-
-void TargetDataX8632::lowerConstants() {
-  if (Ctx->getFlags().getDisableTranslation())
-    return;
-  // No need to emit constants from the int pool since (for x86) they
-  // are embedded as immediates in the instructions, just emit float/double.
-  switch (Ctx->getFlags().getOutFileType()) {
-  case FT_Elf: {
-    ELFObjectWriter *Writer = Ctx->getObjectWriter();
-
-    Writer->writeConstantPool<ConstantInteger32>(IceType_i8);
-    Writer->writeConstantPool<ConstantInteger32>(IceType_i16);
-    Writer->writeConstantPool<ConstantInteger32>(IceType_i32);
-
-    Writer->writeConstantPool<ConstantFloat>(IceType_f32);
-    Writer->writeConstantPool<ConstantDouble>(IceType_f64);
-  } break;
-  case FT_Asm:
-  case FT_Iasm: {
-    OstreamLocker L(Ctx);
-
-    emitConstantPool<PoolTypeConverter<uint8_t>>(Ctx);
-    emitConstantPool<PoolTypeConverter<uint16_t>>(Ctx);
-    emitConstantPool<PoolTypeConverter<uint32_t>>(Ctx);
-
-    emitConstantPool<PoolTypeConverter<float>>(Ctx);
-    emitConstantPool<PoolTypeConverter<double>>(Ctx);
-  } break;
-  }
-}
-
-TargetHeaderX8632::TargetHeaderX8632(GlobalContext *Ctx)
-    : TargetHeaderLowering(Ctx) {}
-
 // Randomize or pool an Immediate.
-Operand *TargetX8632::randomizeOrPoolImmediate(Constant *Immediate,
-                                               int32_t RegNum) {
+template <class Machine>
+Operand *TargetX86Base<Machine>::randomizeOrPoolImmediate(Constant *Immediate,
+                                                          int32_t RegNum) {
   assert(llvm::isa<ConstantInteger32>(Immediate) ||
          llvm::isa<ConstantRelocatable>(Immediate));
   if (Ctx->getFlags().getRandomizeAndPoolImmediatesOption() == RPI_None ||
       RandomizationPoolingPaused == true) {
     // Immediates randomization/pooling off or paused
     return Immediate;
   }
   if (Immediate->shouldBeRandomizedOrPooled(Ctx)) {
     Ctx->statsUpdateRPImms();
     if (Ctx->getFlags().getRandomizeAndPoolImmediatesOption() ==
@@ skipping 55 matching lines @@
           OperandX8632Mem::create(Func, Immediate->getType(), nullptr, Symbol);
       _mov(Reg, MemOperand);
       return Reg;
     }
     assert("Unsupported -randomize-pool-immediates option" && false);
   }
   // the constant Immediate is not eligible for blinding/pooling
   return Immediate;
 }
 
+template <class Machine>
 OperandX8632Mem *
-TargetX8632::randomizeOrPoolImmediate(OperandX8632Mem *MemOperand,
-                                      int32_t RegNum) {
+TargetX86Base<Machine>::randomizeOrPoolImmediate(OperandX8632Mem *MemOperand,
+                                                 int32_t RegNum) {
   assert(MemOperand);
   if (Ctx->getFlags().getRandomizeAndPoolImmediatesOption() == RPI_None ||
       RandomizationPoolingPaused == true) {
     // immediates randomization/pooling is turned off
     return MemOperand;
   }
 
   // If this memory operand is already a randommized one, we do
   // not randomize it again.
   if (MemOperand->getRandomized())
     return MemOperand;
 
   if (Constant *C = llvm::dyn_cast_or_null<Constant>(MemOperand->getOffset())) {
     if (C->shouldBeRandomizedOrPooled(Ctx)) {
       // The offset of this mem operand should be blinded or pooled
       Ctx->statsUpdateRPImms();
       if (Ctx->getFlags().getRandomizeAndPoolImmediatesOption() ==
           RPI_Randomize) {
         // blind the constant offset
         // FROM:
         //  offset[base, index, shift]
         // TO:
         //  insert: lea offset+cookie[base], RegTemp
         //  => -cookie[RegTemp, index, shift]
-        uint32_t Value =
-            llvm::dyn_cast<ConstantInteger32>(MemOperand->getOffset())
-                ->getValue();
+        uint32_t Value = llvm::dyn_cast<ConstantInteger32>(
+                             MemOperand->getOffset())->getValue();
         uint32_t Cookie = Ctx->getRandomizationCookie();
         Constant *Mask1 = Ctx->getConstantInt(
             MemOperand->getOffset()->getType(), Cookie + Value);
         Constant *Mask2 =
             Ctx->getConstantInt(MemOperand->getOffset()->getType(), 0 - Cookie);
 
         OperandX8632Mem *TempMemOperand = OperandX8632Mem::create(
             Func, MemOperand->getType(), MemOperand->getBase(), Mask1);
         // If we have already assigned a physical register, we must come from
         // advancedPhiLowering()=>lowerAssign(). In this case we should reuse
@@ skipping 65 matching lines @@
         return NewMemOperand;
       }
       assert("Unsupported -randomize-pool-immediates option" && false);
     }
   }
   // the offset is not eligible for blinding or pooling, return the original
   // mem operand
   return MemOperand;
 }
 
+} // end of namespace X86Internal
 } // end of namespace Ice
+
+#endif // SUBZERO_SRC_ICETARGETLOWERINGX86BASEIMPL_H
+

[Jim Stichnoth, 2015/06/22 23:04:05]

git (or someone) warns about this "trailing whitespace". :)

[John, 2015/06/22 23:09:55]

Done.

I usually add the extra newline so that

cat <file>

does not end with

...
#endif // SUBZERO_SRC_ICETARGETLOWERINGX86BASEIMPL_Hjpp@jpp...