Subzero: Reduce the amount of #ifdef'd code.

src/IceInstARM32.h

 //===- subzero/src/IceInstARM32.h - ARM32 machine instructions --*- C++ -*-===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 //
 // This file declares the InstARM32 and OperandARM32 classes and
@@ skipping 34 matching lines @@
 
   enum ShiftKind {
     kNoShift = -1,
 #define X(enum, emit) enum,
     ICEINSTARM32SHIFT_TABLE
 #undef X
   };
 
   using Operand::dump;
   void dump(const Cfg *, Ostream &Str) const override {
-    if (ALLOW_DUMP)
+    if (BuildDefs::dump())
       Str << "<OperandARM32>";
   }
 
 protected:
   OperandARM32(OperandKindARM32 Kind, Type Ty)
       : Operand(static_cast<OperandKind>(Kind), Ty) {}
 };
 
 // OperandARM32Mem represents a memory operand in any of the various ARM32
 // addressing modes.
@@ skipping 274 matching lines @@
   InstARM32UnaryopGPR(const InstARM32UnaryopGPR &) = delete;
   InstARM32UnaryopGPR &operator=(const InstARM32UnaryopGPR &) = delete;
 
 public:
   static InstARM32UnaryopGPR *create(Cfg *Func, Variable *Dest, Operand *Src,
                                      CondARM32::Cond Predicate) {
     return new (Func->allocate<InstARM32UnaryopGPR>())
         InstARM32UnaryopGPR(Func, Dest, Src, Predicate);
   }
   void emit(const Cfg *Func) const override {
-    if (!ALLOW_DUMP)
+    if (!BuildDefs::dump())
       return;
     emitUnaryopGPR(Opcode, this, Func);
   }
   void emitIAS(const Cfg *Func) const override {
     (void)Func;
     llvm_unreachable("Not yet implemented");
   }
   void dump(const Cfg *Func) const override {
-    if (!ALLOW_DUMP)
+    if (!BuildDefs::dump())
       return;
     Ostream &Str = Func->getContext()->getStrDump();
     dumpDest(Func);
     Str << " = ";
     dumpOpcodePred(Str, Opcode, getDest()->getType());
     Str << " ";
     dumpSources(Func);
   }
   static bool classof(const Inst *Inst) { return isClassof(Inst, K); }
 
@@ skipping 15 matching lines @@
   InstARM32TwoAddrGPR &operator=(const InstARM32TwoAddrGPR &) = delete;
 
 public:
   // Dest must be a register.
   static InstARM32TwoAddrGPR *create(Cfg *Func, Variable *Dest, Operand *Src,
                                      CondARM32::Cond Predicate) {
     return new (Func->allocate<InstARM32TwoAddrGPR>())
         InstARM32TwoAddrGPR(Func, Dest, Src, Predicate);
   }
   void emit(const Cfg *Func) const override {
-    if (!ALLOW_DUMP)
+    if (!BuildDefs::dump())
       return;
     emitTwoAddr(Opcode, this, Func);
   }
   void emitIAS(const Cfg *Func) const override {
     (void)Func;
     llvm::report_fatal_error("Not yet implemented");
   }
   void dump(const Cfg *Func) const override {
-    if (!ALLOW_DUMP)
+    if (!BuildDefs::dump())
       return;
     Ostream &Str = Func->getContext()->getStrDump();
     dumpDest(Func);
     Str << " = ";
     dumpOpcodePred(Str, Opcode, getDest()->getType());
     Str << " ";
     dumpSources(Func);
   }
   static bool classof(const Inst *Inst) { return isClassof(Inst, K); }
 
@@ skipping 22 matching lines @@
     return new (Func->allocate<InstARM32Movlike>())
         InstARM32Movlike(Func, Dest, Source, Predicate);
   }
   bool isRedundantAssign() const override {
     return checkForRedundantAssign(getDest(), getSrc(0));
   }
   bool isSimpleAssign() const override { return true; }
   void emit(const Cfg *Func) const override;
   void emitIAS(const Cfg *Func) const override;
   void dump(const Cfg *Func) const override {
-    if (!ALLOW_DUMP)
+    if (!BuildDefs::dump())
       return;
     Ostream &Str = Func->getContext()->getStrDump();
     dumpOpcodePred(Str, Opcode, getDest()->getType());
     Str << " ";
     dumpDest(Func);
     Str << ", ";
     dumpSources(Func);
   }
   static bool classof(const Inst *Inst) { return isClassof(Inst, K); }
 
@@ skipping 19 matching lines @@
   // Create an ordinary binary-op instruction like add, and sub.
   // Dest and Src1 must be registers.
   static InstARM32ThreeAddrGPR *create(Cfg *Func, Variable *Dest,
                                        Variable *Src1, Operand *Src2,
                                        CondARM32::Cond Predicate,
                                        bool SetFlags = false) {
     return new (Func->allocate<InstARM32ThreeAddrGPR>())
         InstARM32ThreeAddrGPR(Func, Dest, Src1, Src2, Predicate, SetFlags);
   }
   void emit(const Cfg *Func) const override {
-    if (!ALLOW_DUMP)
+    if (!BuildDefs::dump())
       return;
     emitThreeAddr(Opcode, this, Func, SetFlags);
   }
   void emitIAS(const Cfg *Func) const override {
     (void)Func;
     llvm::report_fatal_error("Not yet implemented");
   }
   void dump(const Cfg *Func) const override {
-    if (!ALLOW_DUMP)
+    if (!BuildDefs::dump())
       return;
     Ostream &Str = Func->getContext()->getStrDump();
     dumpDest(Func);
     Str << " = ";
     dumpOpcodePred(Str, Opcode, getDest()->getType());
     Str << (SetFlags ? ".s " : " ");
     dumpSources(Func);
   }
   static bool classof(const Inst *Inst) { return isClassof(Inst, K); }
 
@@ skipping 338 matching lines @@
 // Declare partial template specializations of emit() methods that
 // already have default implementations.  Without this, there is the
 // possibility of ODR violations and link errors.
 
 template <> void InstARM32Movw::emit(const Cfg *Func) const;
 template <> void InstARM32Movt::emit(const Cfg *Func) const;
 
 } // end of namespace Ice
 
 #endif // SUBZERO_SRC_ICEINSTARM32_H