Subzero: Reduce the amount of #ifdef'd code.

src/IceCfgNode.cpp

 //===- subzero/src/IceCfgNode.cpp - Basic block (node) implementation -----===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 //
 // This file implements the CfgNode class, including the complexities
@@ skipping 204 matching lines @@
 // this node, only one edge is split, and the particular choice of
 // edge is undefined.  This could happen with a switch instruction, or
 // a conditional branch that weirdly has both branches to the same
 // place.  TODO(stichnot,kschimpf): Figure out whether this is legal
 // in the LLVM IR or the PNaCl bitcode, and if so, we need to
 // establish a strong relationship among the ordering of Pred's
 // out-edge list, this node's in-edge list, and the Phi instruction's
 // operand list.
 CfgNode *CfgNode::splitIncomingEdge(CfgNode *Pred, SizeT EdgeIndex) {
   CfgNode *NewNode = Func->makeNode();
-  if (ALLOW_DUMP)
+  if (BuildDefs::dump())
     NewNode->setName("split_" + Pred->getName() + "_" + getName() + "_" +
                      std::to_string(EdgeIndex));
   // The new node is added to the end of the node list, and will later
   // need to be sorted into a reasonable topological order.
   NewNode->setNeedsPlacement(true);
   // Repoint Pred's out-edge.
   bool Found = false;
   for (auto I = Pred->OutEdges.begin(), E = Pred->OutEdges.end();
        !Found && I != E; ++I) {
     if (*I == this) {
@@ skipping 194 matching lines @@
         // If the target instruction "A=B" is part of a cycle, find
         // the "X=A" assignment in the cycle because it will have to
         // be rewritten as "X=tmp".
         for (size_t J = 0; !Found && J < NumPhis; ++J) {
           if (Desc[J].Processed)
             continue;
           Operand *OtherSrc = Desc[J].Src;
           if (Desc[J].NumPred && sameVarOrReg(Dest, OtherSrc)) {
             SizeT VarNum = Func->getNumVariables();
             Variable *Tmp = Func->makeVariable(OtherSrc->getType());
-            if (ALLOW_DUMP)
+            if (BuildDefs::dump())
               Tmp->setName(Func, "__split_" + std::to_string(VarNum));
             Assignments.push_back(InstAssign::create(Func, Tmp, OtherSrc));
             Desc[J].Src = Tmp;
             Found = true;
           }
         }
         assert(Found);
       }
       // Now that a cycle (if any) has been broken, create the actual
       // assignment.
@@ skipping 151 matching lines @@
   // set bits for global variables upon block entry.  We validate this
   // by shrinking the Live vector and then testing it against the
   // pre-shrunk version.  (The shrinking is required, but the
   // validation is not.)
   LivenessBV LiveOrig = Live;
   Live.resize(Liveness->getNumGlobalVars());
   // Non-global arguments in the entry node are allowed to be live on
   // entry.
   bool IsEntry = (Func->getEntryNode() == this);
   if (!(IsEntry || Live == LiveOrig)) {
-    if (ALLOW_DUMP) {
+    if (BuildDefs::dump()) {
       // This is a fatal liveness consistency error.  Print some
       // diagnostics and abort.
       Ostream &Str = Func->getContext()->getStrDump();
       Func->resetCurrentNode();
       Str << "LiveOrig-Live =";
       for (SizeT i = Live.size(); i < LiveOrig.size(); ++i) {
         if (LiveOrig.test(i)) {
           Str << " ";
           Liveness->getVariable(i, this)->dump(Func);
         }
@@ skipping 152 matching lines @@
 }
 
 // ======================== Dump routines ======================== //
 
 namespace {
 
 // Helper functions for emit().
 
 void emitRegisterUsage(Ostream &Str, const Cfg *Func, const CfgNode *Node,
                        bool IsLiveIn, std::vector<SizeT> &LiveRegCount) {
-  if (!ALLOW_DUMP)
+  if (!BuildDefs::dump())
     return;
   Liveness *Liveness = Func->getLiveness();
   const LivenessBV *Live;
   if (IsLiveIn) {
     Live = &Liveness->getLiveIn(Node);
     Str << "\t\t\t\t# LiveIn=";
   } else {
     Live = &Liveness->getLiveOut(Node);
     Str << "\t\t\t\t# LiveOut=";
   }
@@ skipping 21 matching lines @@
         Str << ",";
       First = false;
       Var->emit(Func);
     }
   }
   Str << "\n";
 }
 
 void emitLiveRangesEnded(Ostream &Str, const Cfg *Func, const Inst *Instr,
                          std::vector<SizeT> &LiveRegCount) {
-  if (!ALLOW_DUMP)
+  if (!BuildDefs::dump())
     return;
   bool First = true;
   Variable *Dest = Instr->getDest();
   // Normally we increment the live count for the dest register.  But
   // we shouldn't if the instruction's IsDestNonKillable flag is set,
   // because this means that the target lowering created this
   // instruction as a non-SSA assignment; i.e., a different, previous
   // instruction started the dest variable's live range.
   if (!Instr->isDestNonKillable() && Dest && Dest->hasReg())
     ++LiveRegCount[Dest->getRegNum()];
@@ skipping 15 matching lines @@
         else
           Str << ",";
         Var->emit(Func);
         First = false;
       }
     }
   }
 }
 
 void updateStats(Cfg *Func, const Inst *I) {
-  if (!ALLOW_DUMP)
+  if (!BuildDefs::dump())
     return;
   // Update emitted instruction count, plus fill/spill count for
   // Variable operands without a physical register.
   if (uint32_t Count = I->getEmitInstCount()) {
     Func->getContext()->statsUpdateEmitted(Count);
     if (Variable *Dest = I->getDest()) {
       if (!Dest->hasReg())
         Func->getContext()->statsUpdateFills();
     }
     for (SizeT S = 0; S < I->getSrcSize(); ++S) {
       if (Variable *Src = llvm::dyn_cast<Variable>(I->getSrc(S))) {
         if (!Src->hasReg())
           Func->getContext()->statsUpdateSpills();
       }
     }
   }
 }
 
 } // end of anonymous namespace
 
 void CfgNode::emit(Cfg *Func) const {
-  if (!ALLOW_DUMP)
+  if (!BuildDefs::dump())
     return;
   Func->setCurrentNode(this);
   Ostream &Str = Func->getContext()->getStrEmit();
   Liveness *Liveness = Func->getLiveness();
   bool DecorateAsm =
       Liveness && Func->getContext()->getFlags().getDecorateAsm();
   Str << getAsmName() << ":\n";
   // LiveRegCount keeps track of the number of currently live
   // variables that each register is assigned to.  Normally that would
   // be only 0 or 1, but the register allocator's AllowOverlap
@@ skipping 260 matching lines @@
     }
   }
 
   // Don't allow bundle locking across basic blocks, to keep the
   // backtracking mechanism simple.
   assert(!Helper.isInBundleLockRegion());
   assert(!Retrying);
 }
 
 void CfgNode::dump(Cfg *Func) const {
-  if (!ALLOW_DUMP)
+  if (!BuildDefs::dump())
     return;
   Func->setCurrentNode(this);
   Ostream &Str = Func->getContext()->getStrDump();
   Liveness *Liveness = Func->getLiveness();
   if (Func->isVerbose(IceV_Instructions)) {
     Str << getName() << ":\n";
   }
   // Dump list of predecessor nodes.
   if (Func->isVerbose(IceV_Preds) && !InEdges.empty()) {
     Str << "    // preds = ";
@@ skipping 89 matching lines @@
   InstIntrinsicCall *Inst = InstIntrinsicCall::create(
       Func, 5, Func->makeVariable(IceType_i64), RMWI64Name, Info->Info);
   Inst->addArg(AtomicRMWOp);
   Inst->addArg(Counter);
   Inst->addArg(One);
   Inst->addArg(OrderAcquireRelease);
   Insts.push_front(Inst);
 }
 
 } // end of namespace Ice