| Index: sim/testsuite/sim/bfin/se_all32bitopcodes.S
|
| diff --git a/sim/testsuite/sim/bfin/se_all32bitopcodes.S b/sim/testsuite/sim/bfin/se_all32bitopcodes.S
|
| index be3b3959750cbd03dd0b8bb7dca52db216220d93..f8664e6d9b4942448a7afeefbbbd8e8043c8714c 100644
|
| --- a/sim/testsuite/sim/bfin/se_all32bitopcodes.S
|
| +++ b/sim/testsuite/sim/bfin/se_all32bitopcodes.S
|
| @@ -8,131 +8,27 @@
|
| * and walk every instruction from 0x00000000 to 0xffffffff (and have 0xc000 set)
|
| */
|
|
|
| -# don't try to run normally as it takes way too long in sim
|
| +# Don't want to enable for normal `make check` as it takes way too long in
|
| +# the sim -- executes over 3 billion insns, and even at 10 MIPS, that's 10+
|
| +# minutes. Useful for directed testing, but that's about it.
|
| # mach: none
|
| # sim: --environment operating
|
| # xfail: too many invalid insns are decoded as valid
|
|
|
| #include "test.h"
|
| - .include "testutils.inc"
|
| -
|
| - start
|
| -
|
| - /* Set up exception handler */
|
| - imm32 P4, EVT3;
|
| - loadsym R1, _evx;
|
| - [P4] = R1;
|
| -
|
| - /* set up the _location */
|
| - loadsym P0, _location
|
| - loadsym P1, _table;
|
| - [P0] = P1;
|
| -
|
| - /* Enable single stepping */
|
| - R0 = 1;
|
| - SYSCFG = R0;
|
| -
|
| - /* Lower to the code we want to single step through */
|
| - loadsym P1, _usr;
|
| - RETI = P1;
|
| -
|
| - /* set up pointers to valid data (32Meg), to reduce address violations */
|
| - .macro reset_regs
|
| - imm32 r0, 0x2000000;
|
| - l0 = 0; l1 = 0; l2 = 0; l3 = 0;
|
| - p0 = r0; p1 = r0; p2 = r0; p3 = r0; p4 = r0; p5 = r0;
|
| - usp = r0; fp = r0;
|
| - i0 = r0; i1 = r0; i2 = r0; i3 = r0;
|
| - b0 = r0; b1 = r0; b2 = r0; b3 = r0;
|
| - .endm
|
| - reset_regs
|
| -
|
| - RTI;
|
|
|
| - .align 4;
|
| -_evx:
|
| - /* Make sure exception reason is single step */
|
| - R3 = SEQSTAT;
|
| - R4 = 0x3f;
|
| - R3 = R3 & R4;
|
| +#define SE_ALL_BITS 32
|
| +#include "se_allopcodes.h"
|
| + .include "testutils.inc"
|
|
|
| - /* find a match */
|
| - loadsym P5, _usr;
|
| - loadsym P4, _location;
|
| +.macro se_all_load_insn
|
| R2 = [P5];
|
| - P1 = [P4];
|
| R0 = R2 << 16;
|
| R1 = R2 >> 16;
|
| R0 = R0 | R1;
|
| +.endm
|
|
|
| -_match:
|
| - P2 = P1;
|
| - R7 = [P1++];
|
| - R6 = [P1++];
|
| - R5 = [P1++];
|
| -
|
| - /* is this the end of the table? */
|
| - R4 = 0;
|
| - CC = R4 == R7;
|
| - IF CC jump _new_instruction;
|
| -
|
| - /* is the opcode (R0) greater than the 2nd entry in the table (R6) */
|
| - /* if so look at the next line in the table */
|
| - CC = R6 < R0;
|
| - if CC jump _match;
|
| -
|
| - /* is the opcode (R0) smaller than the first entry in the table (R7) */
|
| - /* this means it's somewhere between the two lines, and should be legal */
|
| - CC = R7 <= R0;
|
| - if !CC jump _legal_instruction;
|
| -
|
| - /* is the current EXCAUSE (R3), the same as the table (R5) */
|
| - /* if not, fail */
|
| - CC = R3 == R5
|
| - if !CC jump fail_lvl;
|
| -
|
| -_match_done:
|
| - /* back up, and store the location to search next */
|
| - [P4] = P2;
|
| -
|
| - /* it matches, so fall through */
|
| - jump _next_instruction;
|
| -
|
| -_new_instruction:
|
| - jump fail_lvl;
|
| -
|
| - /* output the insn (R0) and excause (R3) if diff from last */
|
| - loadsym P0, _last_excause;
|
| - R2 = [P0];
|
| - CC = R2 == R3;
|
| - IF CC jump _next_instruction;
|
| - [P0] = R3;
|
| -
|
| -.ifdef BFIN_JTAG_xxxxx
|
| - R1 = R0;
|
| - R0 = 0x8;
|
| - call __emu_out;
|
| - R0 = R1;
|
| - call __emu_out;
|
| - R0 = R3;
|
| - call __emu_out;
|
| -.else
|
| - loadsym P0, _next_location;
|
| - P1 = [P0];
|
| - [P1++] = R0;
|
| - [P1++] = R3;
|
| - [P0] = P1;
|
| -.endif
|
| -
|
| - jump _next_instruction;
|
| -
|
| -_legal_instruction:
|
| - R4 = 0x10;
|
| - CC = R3 == R4;
|
| - IF !CC JUMP fail_lvl;
|
| - /* it wasn't in the list, and was a single step, so fall through */
|
| -
|
| -_next_instruction:
|
| +.macro se_all_next_insn
|
| /* increment, and go again. */
|
| R0 = R2;
|
|
|
| @@ -169,45 +65,14 @@ _next_instruction:
|
| 1:
|
|
|
| [P5] = R0;
|
| +.endm
|
|
|
| - /* Make sure the opcode isn't in a write buffer */
|
| - SSYNC;
|
| -
|
| - R1 = P5;
|
| - RETX = R1;
|
| -
|
| - /* set up pointers to valid data (32Meg), to reduce address violations */
|
| - reset_regs
|
| - RETS = r0;
|
| - RETN = r0;
|
| - RETE = r0;
|
| - RETI = r0;
|
| -
|
| - RTX;
|
| -
|
| -pass_lvl:
|
| - dbg_pass;
|
| -fail_lvl:
|
| - dbg_fail;
|
| -
|
| - .section .text.usr
|
| - .align 4
|
| -_usr:
|
| +.macro se_all_insn_init
|
| .dw 0xc000;
|
| .dw 0x0000;
|
| - loadsym P0, fail_lvl;
|
| - JUMP (P0);
|
| -
|
| +.endm
|
| +.macro se_all_insn_table
|
| /* this table must be sorted, and end with zero */
|
| - .data
|
| - .align 4;
|
| -_last_excause:
|
| - .dd 0xffff
|
| -_next_location:
|
| - .dd _table_end
|
| -_location:
|
| - .dd 0
|
| -_table:
|
| /* start end SEQSTAT */
|
| .dw 0x1a00, 0xc000, 0x1fff, 0xc000, 0x21, 0
|
| .dw 0x3a00, 0xc000, 0x3fff, 0xc000, 0x21, 0
|
| @@ -34301,4 +34166,6 @@ _table:
|
| .dw 0x0000, 0xe740, 0xffff, 0xe7ff, 0x21, 0
|
| .dw 0x0000, 0xf001, 0xffff, 0xffff, 0x21, 0
|
| .dw 0x0000, 0x0000, 0x0000, 0x0000, 0x00, 0
|
| -_table_end:
|
| +.endm
|
| +
|
| + se_all_test
|
|
|