Index: sim/testsuite/sim/bfin/ChangeLog |
diff --git a/sim/testsuite/sim/bfin/ChangeLog b/sim/testsuite/sim/bfin/ChangeLog |
index 72c47e0a2aa1d2c78abfddcccf6a9367fcb66168..03a98446fa73ac8637cb552d4630dc6c83c30a36 100644 |
--- a/sim/testsuite/sim/bfin/ChangeLog |
+++ b/sim/testsuite/sim/bfin/ChangeLog |
@@ -1,3 +1,77 @@ |
+2012-04-09 Robin Getz <robin.getz@analog.com> |
+ |
+ * random_0017.S, random_0018.S, random_0025.S: New ASTAT shift tests. |
+ |
+2012-04-09 Robin Getz <robin.getz@analog.com> |
+ |
+ * random_0036.S, random_0037.S: New astat tests. |
+ |
+2012-04-09 Mike Frysinger <vapier@gentoo.org> |
+ |
+ * se_all64bitg1opcodes.S: Delete xfail line. |
+ * se_all64bitg2opcodes.S: Likewise. |
+ |
+2012-04-08 Mike Frysinger <vapier@gentoo.org> |
+ |
+ * se_all16bitopcodes.S (SE_ALL_BITS): Define to 16. |
+ (SE_ALL_NEW_INSN_STUB): Define. |
+ (se_all_load_table): Delete. |
+ (se_all_new_insn_log): Likewise. |
+ * se_all32bitopcodes.S: Add more details on slowness. |
+ (SE_ALL_BITS): Define to 13. |
+ (se_all_load_table): Delete. |
+ (se_all_new_insn_stub, se_all_new_insn_log): Likewise. |
+ * se_all64bitg0opcodes.S: Add more details on slowness. |
+ (se_all_new_insn_stub): Delete. |
+ * se_all64bitg1opcodes.S: See mach to bfin. |
+ (se_all_new_insn_stub): Delete. |
+ * se_all64bitg2opcodes.S: See mach to bfin. |
+ (se_all_new_insn_stub): Delete. |
+ * se_allopcodes.h (LOAD_PFX): Define based on SE_ALL_BITS. |
+ (se_all_new_16bit_insn_log, se_all_new_32bit_insn_log): Unify |
+ into new se_all_new_insn_log helper. |
+ (se_all_load_table): New helper. |
+ (se_all_new_insn_stub): Likewise. |
+ |
+2012-03-25 Mike Frysinger <vapier@gentoo.org> |
+ |
+ * c_dsp32mac_dr_a1a0.s: Change 0x12efbc5569 to 0xefbc5569. |
+ * c_dsp32mac_dr_a1a0_iutsh.s: Change 0x12efbc556 to 0x2efbc556. |
+ * c_dsp32mac_dr_a1a0_m.s: Change 0x12efbc5569 to 0xefbc5569. |
+ * c_dsp32shift_vmaxvmax.s: Change 0xa11002001 to 0x11002001. |
+ * c_dsp32shiftim_af_s.s: Change 0x3a1230001 to 0xa1230001. |
+ |
+ * fact.s: Comment out test with too large a number (6227020800). |
+ |
+ * allinsn.exp: If preprocessing usp.S fails, set has_cpp to 0, |
+ else set it to 1. If compiling argc.c fails, set has_cc to 0, |
+ else set it to 1. When processing each src file, if has_ccp is |
+ 0 and the file ends in .S, skip it; if it has_cc is 0 and the |
+ file ends in .c, skip it. |
+ |
+2012-03-19 Mike Frysinger <vapier@gentoo.org> |
+ |
+ * se_all64bitg0opcodes.S, se_all64bitg1opcodes.S, |
+ se_all64bitg2opcodes.S: New exhaustive parallel insn tests. |
+ |
+2012-03-19 Mike Frysinger <vapier@gentoo.org> |
+ |
+ * se_allopcodes.h: New framework for testing opcode regions. |
+ * se_all16bitopcodes.S: Convert over to se_allopcodes.h. |
+ * se_all32bitopcodes.S: Likewise. |
+ |
+2012-03-19 Stuart Henderson <stuart.henderson@analog.com> |
+ |
+ * c_dsp32shiftim_amix.s: Check edge cases in shift behavior. |
+ |
+2012-03-19 Robin Getz <robin.getz@analog.com> |
+ |
+ * random_0014.S, random_0015.S, random_0016.S: New tests for shifts. |
+ |
+2012-03-18 Mike Frysinger <vapier@gentoo.org> |
+ |
+ * se_all16bitopcodes.S: Merge code from se_all32bitopcodes.S. |
+ |
2011-09-28 Mike Frysinger <vapier@gentoo.org> |
* vit_max2.s: New tests for parallel VIT_MAX insns. |