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1 #ifndef SIM_MAIN_H | 1 #ifndef SIM_MAIN_H |
2 #define SIM_MAIN_H | 2 #define SIM_MAIN_H |
3 | 3 |
4 /* General config options */ | 4 /* General config options */ |
5 | 5 |
6 #define WITH_CORE | 6 #define WITH_CORE |
7 #define WITH_MODULO_MEMORY 1 | 7 #define WITH_MODULO_MEMORY 1 |
8 #define WITH_WATCHPOINTS 1 | 8 #define WITH_WATCHPOINTS 1 |
9 | 9 |
10 | 10 |
11 /* The v850 has 32bit words, numbered 31 (MSB) to 0 (LSB) */ | 11 /* The v850 has 32bit words, numbered 31 (MSB) to 0 (LSB) */ |
12 | 12 |
13 #define WITH_TARGET_WORD_MSB 31 | 13 #define WITH_TARGET_WORD_MSB 31 |
14 | 14 |
15 | 15 |
16 #include "sim-basics.h" | 16 #include "sim-basics.h" |
17 #include "sim-signal.h" | 17 #include "sim-signal.h" |
| 18 #include "sim-fpu.h" |
18 | 19 |
19 typedef address_word sim_cia; | 20 typedef address_word sim_cia; |
20 | 21 |
21 #include "sim-base.h" | 22 #include "sim-base.h" |
22 | 23 |
23 #include "simops.h" | 24 #include "simops.h" |
24 #include "bfd.h" | 25 #include "bfd.h" |
25 | 26 |
26 | 27 |
27 typedef signed8 int8; | 28 typedef signed8 int8; |
28 typedef unsigned8 uint8; | 29 typedef unsigned8 uint8; |
29 typedef signed16 int16; | 30 typedef signed16 int16; |
30 typedef unsigned16 uint16; | 31 typedef unsigned16 uint16; |
31 typedef signed32 int32; | 32 typedef signed32 int32; |
32 typedef unsigned32 uint32; | 33 typedef unsigned32 uint32; |
33 typedef unsigned32 reg_t; | 34 typedef unsigned32 reg_t; |
34 | 35 |
35 | 36 |
36 /* The current state of the processor; registers, memory, etc. */ | 37 /* The current state of the processor; registers, memory, etc. */ |
37 | 38 |
38 typedef struct _v850_regs { | 39 typedef struct _v850_regs { |
39 reg_t regs[32]; /* general-purpose registers */ | 40 reg_t regs[32]; /* general-purpose registers */ |
40 reg_t sregs[32]; /* system registers, including psw */ | 41 reg_t sregs[32]; /* system registers, including psw */ |
41 reg_t pc; | 42 reg_t pc; |
42 int dummy_mem;» » /* where invalid accesses go */ | 43 int dummy_mem; /* where invalid accesses go */ |
| 44 reg_t mpu0_sregs[28]; /* mpu0 system registers */ |
| 45 reg_t mpu1_sregs[28]; /* mpu1 system registers */ |
| 46 reg_t fpu_sregs[28]; /* fpu system registers */ |
43 } v850_regs; | 47 } v850_regs; |
44 | 48 |
45 struct _sim_cpu | 49 struct _sim_cpu |
46 { | 50 { |
47 /* ... simulator specific members ... */ | 51 /* ... simulator specific members ... */ |
48 v850_regs reg; | 52 v850_regs reg; |
49 reg_t psw_mask; /* only allow non-reserved bits to be set */ | 53 reg_t psw_mask; /* only allow non-reserved bits to be set */ |
50 sim_event *pending_nmi; | 54 sim_event *pending_nmi; |
51 /* ... base type ... */ | 55 /* ... base type ... */ |
52 sim_cpu_base base; | 56 sim_cpu_base base; |
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115 | 119 |
116 #define COMPAT_2(CALL) \ | 120 #define COMPAT_2(CALL) \ |
117 SAVE_2; \ | 121 SAVE_2; \ |
118 PC += (CALL); \ | 122 PC += (CALL); \ |
119 nia = PC | 123 nia = PC |
120 | 124 |
121 | 125 |
122 /* new */ | 126 /* new */ |
123 #define GR ((CPU)->reg.regs) | 127 #define GR ((CPU)->reg.regs) |
124 #define SR ((CPU)->reg.sregs) | 128 #define SR ((CPU)->reg.sregs) |
| 129 #define MPU0_SR ((STATE_CPU (sd, 0))->reg.mpu0_sregs) |
| 130 #define MPU1_SR ((STATE_CPU (sd, 0))->reg.mpu1_sregs) |
| 131 #define FPU_SR ((STATE_CPU (sd, 0))->reg.fpu_sregs) |
125 | 132 |
126 /* old */ | 133 /* old */ |
127 #define State (STATE_CPU (simulator, 0)->reg) | 134 #define State (STATE_CPU (simulator, 0)->reg) |
128 #define PC (State.pc) | 135 #define PC (State.pc) |
129 #define SP» (State.regs[3]) | 136 #define SP_REGNO 3 |
| 137 #define SP (State.regs[SP_REGNO]) |
130 #define EP (State.regs[30]) | 138 #define EP (State.regs[30]) |
131 | 139 |
132 #define EIPC (State.sregs[0]) | 140 #define EIPC (State.sregs[0]) |
133 #define EIPSW (State.sregs[1]) | 141 #define EIPSW (State.sregs[1]) |
134 #define FEPC (State.sregs[2]) | 142 #define FEPC (State.sregs[2]) |
135 #define FEPSW (State.sregs[3]) | 143 #define FEPSW (State.sregs[3]) |
136 #define ECR (State.sregs[4]) | 144 #define ECR (State.sregs[4]) |
137 #define PSW (State.sregs[5]) | 145 #define PSW (State.sregs[5]) |
| 146 #define PSW_REGNO 5 |
| 147 #define EIIC (State.sregs[13]) |
| 148 #define FEIC (State.sregs[14]) |
| 149 #define DBIC (SR[15]) |
138 #define CTPC (SR[16]) | 150 #define CTPC (SR[16]) |
139 #define CTPSW (SR[17]) | 151 #define CTPSW (SR[17]) |
140 #define DBPC (State.sregs[18]) | 152 #define DBPC (State.sregs[18]) |
141 #define DBPSW (State.sregs[19]) | 153 #define DBPSW (State.sregs[19]) |
142 #define CTBP (State.sregs[20]) | 154 #define CTBP (State.sregs[20]) |
| 155 #define DIR (SR[21]) |
| 156 #define EIWR (SR[28]) |
| 157 #define FEWR (SR[29]) |
| 158 #define DBWR (SR[30]) |
| 159 #define BSEL (SR[31]) |
143 | 160 |
144 #define PSW_US BIT32 (8) | 161 #define PSW_US BIT32 (8) |
145 #define PSW_NP 0x80 | 162 #define PSW_NP 0x80 |
146 #define PSW_EP 0x40 | 163 #define PSW_EP 0x40 |
147 #define PSW_ID 0x20 | 164 #define PSW_ID 0x20 |
148 #define PSW_SAT 0x10 | 165 #define PSW_SAT 0x10 |
149 #define PSW_CY 0x8 | 166 #define PSW_CY 0x8 |
150 #define PSW_OV 0x4 | 167 #define PSW_OV 0x4 |
151 #define PSW_S 0x2 | 168 #define PSW_S 0x2 |
152 #define PSW_Z 0x1 | 169 #define PSW_Z 0x1 |
153 | 170 |
| 171 #define PSW_NPV (1<<18) |
| 172 #define PSW_DMP (1<<17) |
| 173 #define PSW_IMP (1<<16) |
| 174 |
| 175 #define ECR_EICC 0x0000ffff |
| 176 #define ECR_FECC 0xffff0000 |
| 177 |
| 178 /* FPU */ |
| 179 |
| 180 #define FPSR (FPU_SR[6]) |
| 181 #define FPSR_REGNO 6 |
| 182 #define FPEPC (FPU_SR[7]) |
| 183 #define FPST (FPU_SR[8]) |
| 184 #define FPST_REGNO 8 |
| 185 #define FPCC (FPU_SR[9]) |
| 186 #define FPCFG (FPU_SR[10]) |
| 187 #define FPCFG_REGNO 10 |
| 188 |
| 189 #define FPSR_DEM 0x00200000 |
| 190 #define FPSR_SEM 0x00100000 |
| 191 #define FPSR_RM 0x000c0000 |
| 192 #define FPSR_RN 0x00000000 |
| 193 #define FPSR_FS 0x00020000 |
| 194 #define FPSR_PR 0x00010000 |
| 195 |
| 196 #define FPSR_XC 0x0000fc00 |
| 197 #define FPSR_XCE 0x00008000 |
| 198 #define FPSR_XCV 0x00004000 |
| 199 #define FPSR_XCZ 0x00002000 |
| 200 #define FPSR_XCO 0x00001000 |
| 201 #define FPSR_XCU 0x00000800 |
| 202 #define FPSR_XCI 0x00000400 |
| 203 |
| 204 #define FPSR_XE 0x000003e0 |
| 205 #define FPSR_XEV 0x00000200 |
| 206 #define FPSR_XEZ 0x00000100 |
| 207 #define FPSR_XEO 0x00000080 |
| 208 #define FPSR_XEU 0x00000040 |
| 209 #define FPSR_XEI 0x00000020 |
| 210 |
| 211 #define FPSR_XP 0x0000001f |
| 212 #define FPSR_XPV 0x00000010 |
| 213 #define FPSR_XPZ 0x00000008 |
| 214 #define FPSR_XPO 0x00000004 |
| 215 #define FPSR_XPU 0x00000002 |
| 216 #define FPSR_XPI 0x00000001 |
| 217 |
| 218 #define FPST_PR 0x00008000 |
| 219 #define FPST_XCE 0x00002000 |
| 220 #define FPST_XCV 0x00001000 |
| 221 #define FPST_XCZ 0x00000800 |
| 222 #define FPST_XCO 0x00000400 |
| 223 #define FPST_XCU 0x00000200 |
| 224 #define FPST_XCI 0x00000100 |
| 225 |
| 226 #define FPST_XPV 0x00000010 |
| 227 #define FPST_XPZ 0x00000008 |
| 228 #define FPST_XPO 0x00000004 |
| 229 #define FPST_XPU 0x00000002 |
| 230 #define FPST_XPI 0x00000001 |
| 231 |
| 232 #define FPCFG_RM 0x00000180 |
| 233 #define FPCFG_XEV 0x00000010 |
| 234 #define FPCFG_XEZ 0x00000008 |
| 235 #define FPCFG_XEO 0x00000004 |
| 236 #define FPCFG_XEU 0x00000002 |
| 237 #define FPCFG_XEI 0x00000001 |
| 238 |
| 239 #define GET_FPCC()\ |
| 240 ((FPSR >> 24) &0xf) |
| 241 |
| 242 #define CLEAR_FPCC(bbb)\ |
| 243 (FPSR &= ~(1 << (bbb+24))) |
| 244 |
| 245 #define SET_FPCC(bbb)\ |
| 246 (FPSR |= 1 << (bbb+24)) |
| 247 |
| 248 #define TEST_FPCC(bbb)\ |
| 249 ((FPSR & (1 << (bbb+24))) != 0) |
| 250 |
| 251 #define FPSR_GET_ROUND() \ |
| 252 (((FPSR & FPSR_RM) == FPSR_RN) ? sim_fpu_round_near \ |
| 253 : ((FPSR & FPSR_RM) == 0x00040000) ? sim_fpu_round_up \ |
| 254 : ((FPSR & FPSR_RM) == 0x00080000) ? sim_fpu_round_down \ |
| 255 : sim_fpu_round_zero) |
| 256 |
| 257 |
| 258 enum FPU_COMPARE { |
| 259 FPU_CMP_F = 0, |
| 260 FPU_CMP_UN, |
| 261 FPU_CMP_EQ, |
| 262 FPU_CMP_UEQ, |
| 263 FPU_CMP_OLT, |
| 264 FPU_CMP_ULT, |
| 265 FPU_CMP_OLE, |
| 266 FPU_CMP_ULE, |
| 267 FPU_CMP_SF, |
| 268 FPU_CMP_NGLE, |
| 269 FPU_CMP_SEQ, |
| 270 FPU_CMP_NGL, |
| 271 FPU_CMP_LT, |
| 272 FPU_CMP_NGE, |
| 273 FPU_CMP_LE, |
| 274 FPU_CMP_NGT |
| 275 }; |
| 276 |
| 277 |
| 278 /* MPU */ |
| 279 #define MPM (MPU1_SR[0]) |
| 280 #define MPC (MPU1_SR[1]) |
| 281 #define MPC_REGNO 1 |
| 282 #define TID (MPU1_SR[2]) |
| 283 #define PPA (MPU1_SR[3]) |
| 284 #define PPM (MPU1_SR[4]) |
| 285 #define PPC (MPU1_SR[5]) |
| 286 #define DCC (MPU1_SR[6]) |
| 287 #define DCV0 (MPU1_SR[7]) |
| 288 #define DCV1 (MPU1_SR[8]) |
| 289 #define SPAL (MPU1_SR[10]) |
| 290 #define SPAU (MPU1_SR[11]) |
| 291 #define IPA0L (MPU1_SR[12]) |
| 292 #define IPA0U (MPU1_SR[13]) |
| 293 #define IPA1L (MPU1_SR[14]) |
| 294 #define IPA1U (MPU1_SR[15]) |
| 295 #define IPA2L (MPU1_SR[16]) |
| 296 #define IPA2U (MPU1_SR[17]) |
| 297 #define IPA3L (MPU1_SR[18]) |
| 298 #define IPA3U (MPU1_SR[19]) |
| 299 #define DPA0L (MPU1_SR[20]) |
| 300 #define DPA0U (MPU1_SR[21]) |
| 301 #define DPA1L (MPU1_SR[22]) |
| 302 #define DPA1U (MPU1_SR[23]) |
| 303 #define DPA2L (MPU1_SR[24]) |
| 304 #define DPA2U (MPU1_SR[25]) |
| 305 #define DPA3L (MPU1_SR[26]) |
| 306 #define DPA3U (MPU1_SR[27]) |
| 307 |
| 308 #define PPC_PPE 0x1 |
| 309 #define SPAL_SPE 0x1 |
| 310 #define SPAL_SPS 0x10 |
| 311 |
| 312 #define VIP (MPU0_SR[0]) |
| 313 #define VMECR (MPU0_SR[4]) |
| 314 #define VMTID (MPU0_SR[5]) |
| 315 #define VMADR (MPU0_SR[6]) |
| 316 #define VPECR (MPU0_SR[8]) |
| 317 #define VPTID (MPU0_SR[9]) |
| 318 #define VPADR (MPU0_SR[10]) |
| 319 #define VDECR (MPU0_SR[12]) |
| 320 #define VDTID (MPU0_SR[13]) |
| 321 |
| 322 #define MPM_AUE 0x2 |
| 323 #define MPM_MPE 0x1 |
| 324 |
| 325 #define VMECR_VMX 0x2 |
| 326 #define VMECR_VMR 0x4 |
| 327 #define VMECR_VMW 0x8 |
| 328 #define VMECR_VMS 0x10 |
| 329 #define VMECR_VMRMW 0x20 |
| 330 #define VMECR_VMMS 0x40 |
| 331 |
| 332 #define IPA2ADDR(IPA) ((IPA) & 0x1fffff80) |
| 333 #define IPA_IPE 0x1 |
| 334 #define IPA_IPX 0x2 |
| 335 #define IPA_IPR 0x4 |
| 336 #define IPE0 (IPA0L & IPA_IPE) |
| 337 #define IPE1 (IPA1L & IPA_IPE) |
| 338 #define IPE2 (IPA2L & IPA_IPE) |
| 339 #define IPE3 (IPA3L & IPA_IPE) |
| 340 #define IPX0 (IPA0L & IPA_IPX) |
| 341 #define IPX1 (IPA1L & IPA_IPX) |
| 342 #define IPX2 (IPA2L & IPA_IPX) |
| 343 #define IPX3 (IPA3L & IPA_IPX) |
| 344 #define IPR0 (IPA0L & IPA_IPR) |
| 345 #define IPR1 (IPA1L & IPA_IPR) |
| 346 #define IPR2 (IPA2L & IPA_IPR) |
| 347 #define IPR3 (IPA3L & IPA_IPR) |
| 348 |
| 349 #define DPA2ADDR(DPA) ((DPA) & 0x1fffff80) |
| 350 #define DPA_DPE 0x1 |
| 351 #define DPA_DPR 0x4 |
| 352 #define DPA_DPW 0x8 |
| 353 #define DPE0 (DPA0L & DPA_DPE) |
| 354 #define DPE1 (DPA1L & DPA_DPE) |
| 355 #define DPE2 (DPA2L & DPA_DPE) |
| 356 #define DPE3 (DPA3L & DPA_DPE) |
| 357 #define DPR0 (DPA0L & DPA_DPR) |
| 358 #define DPR1 (DPA1L & DPA_DPR) |
| 359 #define DPR2 (DPA2L & DPA_DPR) |
| 360 #define DPR3 (DPA3L & DPA_DPR) |
| 361 #define DPW0 (DPA0L & DPA_DPW) |
| 362 #define DPW1 (DPA1L & DPA_DPW) |
| 363 #define DPW2 (DPA2L & DPA_DPW) |
| 364 #define DPW3 (DPA3L & DPA_DPW) |
| 365 |
| 366 #define DCC_DCE0 0x1 |
| 367 #define DCC_DCE1 0x10000 |
| 368 |
| 369 #define PPA2ADDR(PPA) ((PPA) & 0x1fffff80) |
| 370 #define PPC_PPC 0xfffffffe |
| 371 #define PPC_PPE 0x1 |
| 372 #define PPC_PPM 0x0000fff8 |
| 373 |
| 374 |
154 #define SEXT3(x) ((((x)&0x7)^(~0x3))+0x4) | 375 #define SEXT3(x) ((((x)&0x7)^(~0x3))+0x4) |
155 | 376 |
156 /* sign-extend a 4-bit number */ | 377 /* sign-extend a 4-bit number */ |
157 #define SEXT4(x) ((((x)&0xf)^(~0x7))+0x8) | 378 #define SEXT4(x) ((((x)&0xf)^(~0x7))+0x8) |
158 | 379 |
159 /* sign-extend a 5-bit number */ | 380 /* sign-extend a 5-bit number */ |
160 #define SEXT5(x) ((((x)&0x1f)^(~0xf))+0x10) | 381 #define SEXT5(x) ((((x)&0x1f)^(~0xf))+0x10) |
161 | 382 |
162 /* sign-extend a 9-bit number */ | 383 /* sign-extend a 9-bit number */ |
163 #define SEXT9(x) ((((x)&0x1ff)^(~0xff))+0x100) | 384 #define SEXT9(x) ((((x)&0x1ff)^(~0xff))+0x100) |
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337 if (TRACE_MEMORY_P (CPU)) { \ | 558 if (TRACE_MEMORY_P (CPU)) { \ |
338 trace_module = TRACE_MEMORY_IDX; \ | 559 trace_module = TRACE_MEMORY_IDX; \ |
339 trace_pc = cia; \ | 560 trace_pc = cia; \ |
340 trace_name = itable[MY_INDEX].name; \ | 561 trace_name = itable[MY_INDEX].name; \ |
341 trace_values[0] = (ADDR); \ | 562 trace_values[0] = (ADDR); \ |
342 trace_num_values = 1; \ | 563 trace_num_values = 1; \ |
343 trace_result (1, (RESULT)); \ | 564 trace_result (1, (RESULT)); \ |
344 } \ | 565 } \ |
345 } while (0) | 566 } while (0) |
346 | 567 |
| 568 #define TRACE_FP_INPUT_FPU1(V0) \ |
| 569 do { \ |
| 570 if (TRACE_FPU_P (CPU)) \ |
| 571 { \ |
| 572 unsigned64 f0; \ |
| 573 sim_fpu_to64 (&f0, (V0)); \ |
| 574 trace_input_fp1 (SD, CPU, TRACE_FPU_IDX, f0); \ |
| 575 } \ |
| 576 } while (0) |
| 577 |
| 578 #define TRACE_FP_INPUT_FPU2(V0, V1) \ |
| 579 do { \ |
| 580 if (TRACE_FPU_P (CPU)) \ |
| 581 { \ |
| 582 unsigned64 f0, f1; \ |
| 583 sim_fpu_to64 (&f0, (V0)); \ |
| 584 sim_fpu_to64 (&f1, (V1)); \ |
| 585 trace_input_fp2 (SD, CPU, TRACE_FPU_IDX, f0, f1); \ |
| 586 } \ |
| 587 } while (0) |
| 588 |
| 589 #define TRACE_FP_INPUT_FPU3(V0, V1, V2) \ |
| 590 do { \ |
| 591 if (TRACE_FPU_P (CPU)) \ |
| 592 { \ |
| 593 unsigned64 f0, f1, f2; \ |
| 594 sim_fpu_to64 (&f0, (V0)); \ |
| 595 sim_fpu_to64 (&f1, (V1)); \ |
| 596 sim_fpu_to64 (&f2, (V2)); \ |
| 597 trace_input_fp3 (SD, CPU, TRACE_FPU_IDX, f0, f1, f2); \ |
| 598 } \ |
| 599 } while (0) |
| 600 |
| 601 #define TRACE_FP_INPUT_BOOL1_FPU2(V0, V1, V2) \ |
| 602 do { \ |
| 603 if (TRACE_FPU_P (CPU)) \ |
| 604 { \ |
| 605 int d0 = (V0); \ |
| 606 unsigned64 f1, f2; \ |
| 607 TRACE_DATA *data = CPU_TRACE_DATA (CPU); \ |
| 608 TRACE_IDX (data) = TRACE_FPU_IDX; \ |
| 609 sim_fpu_to64 (&f1, (V1)); \ |
| 610 sim_fpu_to64 (&f2, (V2)); \ |
| 611 save_data (SD, data, trace_fmt_bool, sizeof (d0), &d0); \ |
| 612 save_data (SD, data, trace_fmt_fp, sizeof (fp_word), &f1); \ |
| 613 save_data (SD, data, trace_fmt_fp, sizeof (fp_word), &f2); \ |
| 614 } \ |
| 615 } while (0) |
| 616 |
| 617 #define TRACE_FP_INPUT_WORD2(V0, V1) \ |
| 618 do { \ |
| 619 if (TRACE_FPU_P (CPU)) \ |
| 620 trace_input_word2 (SD, CPU, TRACE_FPU_IDX, (V0), (V1)); \ |
| 621 } while (0) |
| 622 |
| 623 #define TRACE_FP_RESULT_FPU1(R0) \ |
| 624 do { \ |
| 625 if (TRACE_FPU_P (CPU)) \ |
| 626 { \ |
| 627 unsigned64 f0; \ |
| 628 sim_fpu_to64 (&f0, (R0)); \ |
| 629 trace_result_fp1 (SD, CPU, TRACE_FPU_IDX, f0); \ |
| 630 } \ |
| 631 } while (0) |
| 632 |
| 633 #define TRACE_FP_RESULT_WORD1(R0) TRACE_FP_RESULT_WORD(R0) |
| 634 |
| 635 #define TRACE_FP_RESULT_WORD2(R0, R1) \ |
| 636 do { \ |
| 637 if (TRACE_FPU_P (CPU)) \ |
| 638 trace_result_word2 (SD, CPU, TRACE_FPU_IDX, (R0), (R1)); \ |
| 639 } while (0) |
| 640 |
347 #else | 641 #else |
348 #define trace_input(NAME, IN1, IN2) | 642 #define trace_input(NAME, IN1, IN2) |
349 #define trace_output(RESULT) | 643 #define trace_output(RESULT) |
350 #define trace_result(HAS_RESULT, RESULT) | 644 #define trace_result(HAS_RESULT, RESULT) |
351 | 645 |
352 #define TRACE_ALU_INPUT0() | 646 #define TRACE_ALU_INPUT0() |
353 #define TRACE_ALU_INPUT1(IN0) | 647 #define TRACE_ALU_INPUT1(IN0) |
354 #define TRACE_ALU_INPUT2(IN0, IN1) | 648 #define TRACE_ALU_INPUT2(IN0, IN1) |
355 #define TRACE_ALU_INPUT2(IN0, IN1) | 649 #define TRACE_ALU_INPUT2(IN0, IN1) |
356 #define TRACE_ALU_INPUT2(IN0, IN1 INS2) | 650 #define TRACE_ALU_INPUT2(IN0, IN1 INS2) |
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381 unsigned long int sfi, | 675 unsigned long int sfi, |
382 signed32 /*signed long int*/ * quotient_ptr, | 676 signed32 /*signed long int*/ * quotient_ptr, |
383 signed32 /*signed long int*/ * remainder_ptr, | 677 signed32 /*signed long int*/ * remainder_ptr, |
384 int *overflow_ptr | 678 int *overflow_ptr |
385 ); | 679 ); |
386 extern int type1_regs[]; | 680 extern int type1_regs[]; |
387 extern int type2_regs[]; | 681 extern int type2_regs[]; |
388 extern int type3_regs[]; | 682 extern int type3_regs[]; |
389 | 683 |
390 #endif | 684 #endif |
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