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Side by Side Diff: sim/testsuite/sim/bfin/se_all16bitopcodes.S

Issue 11969036: Merge GDB 7.5.1 (Closed) Base URL: http://git.chromium.org/native_client/nacl-gdb.git@master
Patch Set: Created 7 years, 11 months ago
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1 /* 1 /*
2 * Blackfin testcase for testing illegal/legal 16-bit opcodes from userspace 2 * Blackfin testcase for testing illegal/legal 16-bit opcodes from userspace
3 * we track all instructions which cause some sort of exception when run from 3 * we track all instructions which cause some sort of exception when run from
4 * userspace, this is normally EXCAUSE : 4 * userspace, this is normally EXCAUSE :
5 * - 0x21 : illegal instruction 5 * - 0x21 : illegal instruction
6 * - 0x22 : illegal instruction combination 6 * - 0x22 : illegal instruction combination
7 * - 0x2e : use of supervisor resource from userspace 7 * - 0x2e : use of supervisor resource from userspace
8 * and walk every instruction from 0x0000 to 0xbfff 8 * and walk every instruction from 0x0000 to 0xbfff
9 */ 9 */
10 10
11 # mach: bfin 11 # mach: bfin
12 # sim: --environment operating 12 # sim: --environment operating
13 13
14 #include "test.h" 14 #include "test.h"
15
16 #define SE_ALL_BITS 16
17 #define SE_ALL_NEW_INSN_STUB
18 #include "se_allopcodes.h"
15 .include "testutils.inc" 19 .include "testutils.inc"
16 20
17 » start 21 .macro se_all_load_insn
22 » R2 = W[P5];
23 » R0 = R2;
24 .endm
18 25
19 » /* Set up exception handler */ 26 .macro se_all_next_insn
20 » imm32 P4, EVT3; 27 » /* increment, and go again. */
21 » loadsym R1, _evx; 28 » R0 = R2;
22 » [P4] = R1;
23 29
24 /* set up the _location */
25 loadsym P0, _location
26 loadsym P1, _table;
27 [P0] = P1;
28
29 /* Enable single stepping */
30 R0 = 1;
31 SYSCFG = R0;
32
33 /* Lower to the code we want to single step through */
34 loadsym R1, _usr;
35 RETI = R1;
36
37 /* set up pointers to valid data (32Meg), to reduce address violations * /
38 init_p_regs 0x2000000;
39 init_i_regs 0x2000000;
40 init_b_regs 0x2000000;
41 init_l_regs 0;
42 imm32 fp, 0x2000000;
43 usp = p0;
44
45 RTI;
46
47 .align 4;
48 _usr:
49 .dd 0x0000;
50 jump fail_lvl;
51
52 _evx:
53 /* Make sure exception reason is single step */
54 R3 = SEQSTAT;
55 R4 = 0x3f;
56 R3 = R3 & R4;
57
58 /* find a match */
59 loadsym P0, _usr;
60 loadsym P2, _location;
61 P1 = [P2];
62 R0 = W[P0];
63
64 _match:
65 R7 = W[P1++];
66 R6 = W[P1++];
67 R5 = W[P1++];
68
69 /* is this the end of the table? */
70 R4 = 0;
71 CC = R4 == R7;
72 IF CC jump _legal_instruction;
73
74 /* is the opcode (R0) greater than the 2nd entry in the table (R6) */
75 /* if so look at the next line in the table */
76 CC = R6 < R0;
77 if CC jump _match;
78
79 /* is the opcode (R0) smaller than the first entry in the table (R7) */
80 /* this means it's somewhere between the two lines, and should be legal */
81 CC = R7 <= R0;
82 if !CC jump _legal_instruction;
83
84 /* is the current EXCAUSE (R3), the same as the table (R5) */
85 /* if not, fail */
86 CC = R3 == R5
87 if !CC jump fail_lvl;
88
89 _match_done:
90 /* back up, and store the location to search next */
91 R0 = P1;
92 /* 3 back, * word/byte) */
93 R0 += (-3 * 2);
94 [P2] = R0;
95
96 /* it matches, so fall through */
97 jump _next_instruction;
98
99 _legal_instruction:
100 R4 = 0x10;
101 CC = R3 == R4;
102 IF !CC JUMP fail_lvl;
103 /* it wasn't in the list, and was a single step, so fall through */
104
105 _next_instruction:
106 /* increment, and go again. */
107 loadsym P0, _usr;
108 R0 = W[P0];
109 R0 += 1; 30 R0 += 1;
110 » W[P0] = R0; 31 » /* finish once we hit the 32bit limit */
111 R1 = 0xC000 (Z); 32 R1 = 0xC000 (Z);
112 CC = R1 == R0; 33 CC = R1 == R0;
113 IF CC JUMP pass_lvl; 34 IF CC JUMP pass_lvl;
114 35
115 » /* Make sure the opcode isn't in a write buffer */ 36 » W[P5] = R0;
116 » SSYNC; 37 .endm
117 38
118 » loadsym R1, _usr 39 .macro se_all_new_insn_stub
119 » RETX = R1; 40 » jump _legal_instruction;
41 .endm
120 42
121 » /* set up pointers to valid data (32Meg), to reduce address violations * / 43 .macro se_all_insn_init
122 » init_p_regs 0x2000000; 44 » .dw 0x0000;
123 » init_i_regs 0x2000000; 45 .endm
124 » init_b_regs 0x2000000; 46 .macro se_all_insn_table
125 » init_l_regs 0;
126 » imm32 fp, 0x2000000;
127 » usp = p0;
128 » RETS = p0;
129 » RETN = p0;
130 » RETE = p0;
131 » RETI = p0;
132 » RTX;
133
134 pass_lvl:
135 » dbg_pass;
136 fail_lvl:
137 » dbg_fail;
138
139
140 /* this table must be sorted, and end with zero */ 47 /* this table must be sorted, and end with zero */
141 .data
142 .align 4;
143 _location:
144 .dd 0
145 _table:
146 /* start end SEQSTAT */ 48 /* start end SEQSTAT */
147 .dw 0x0001, 0x000f, 0x21 49 .dw 0x0001, 0x000f, 0x21
148 .dw 0x0011, 0x0013, 0x2e 50 .dw 0x0011, 0x0013, 0x2e
149 .ifndef BFIN_JTAG 51 .ifndef BFIN_JTAG
150 .dw 0x0014, 0x0014, 0x2e /* anomaly - RTX works when emul ator attached */ 52 .dw 0x0014, 0x0014, 0x2e /* anomaly - RTX works when emul ator attached */
151 .endif 53 .endif
152 .dw 0x0015, 0x001F, 0x21 54 .dw 0x0015, 0x001F, 0x21
153 .dw 0x0021, 0x0022, 0x21 55 .dw 0x0021, 0x0022, 0x21
154 .dw 0x0026, 0x0026, 0x21 56 .dw 0x0026, 0x0026, 0x21
155 .ifndef BFIN_JTAG 57 .ifndef BFIN_JTAG
(...skipping 279 matching lines...) Expand 10 before | Expand all | Expand 10 after
435 .dw 0x9980, 0x99ff, 0x21 337 .dw 0x9980, 0x99ff, 0x21
436 .dw 0x9a40, 0x9a7f, 0x21 338 .dw 0x9a40, 0x9a7f, 0x21
437 .dw 0x9ac0, 0x9aff, 0x21 339 .dw 0x9ac0, 0x9aff, 0x21
438 .dw 0x9b40, 0x9bff, 0x21 340 .dw 0x9b40, 0x9bff, 0x21
439 .dw 0x9c60, 0x9c7f, 0x21 341 .dw 0x9c60, 0x9c7f, 0x21
440 .dw 0x9ce0, 0x9cff, 0x21 342 .dw 0x9ce0, 0x9cff, 0x21
441 .dw 0x9d60, 0x9d7f, 0x21 343 .dw 0x9d60, 0x9d7f, 0x21
442 .dw 0x9ef0, 0x9eff, 0x21 344 .dw 0x9ef0, 0x9eff, 0x21
443 .dw 0x9f70, 0x9f7f, 0x21 345 .dw 0x9f70, 0x9f7f, 0x21
444 .dw 0x0000, 0x0000, 0x00 346 .dw 0x0000, 0x0000, 0x00
347 .endm
348
349 se_all_test
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