sim/testsuite/sim/bfin/random_0018.S - Issue 11969036: Merge GDB 7.5.1

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Side by Side Diff: sim/testsuite/sim/bfin/random_0018.S

Issue 11969036: Merge GDB 7.5.1 (Closed) Base URL: http://git.chromium.org/native_client/nacl-gdb.git@master

Patch Set: Created 7 years, 11 months ago

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	1 # mach: bfin

	2 #include "test.h"

	3 .include "testutils.inc"

	4

	5 start

	6

	7 dmm32 ASTAT, (0x40204090 \| _AV1S \| _AV0S \| _AV0 \| _AQ \| _AN \| _AZ);

	8 imm32 R1, 0x33e91405;

	9 imm32 R4, 0x3fa1377c;

	10 R4.H = R1.H >>> 0x1d;

	11 checkreg R4, 0x9f48377c;

	12 checkreg ASTAT, (0x40204090 \| _VS \| _V \| _AV1S \| _AV0S \| _AV0 \| _AQ \| _V _COPY \| _AN);

	13

	14 dmm32 ASTAT, (0x64800010 \| _VS \| _AV1S \| _AV0S \| _AQ \| _CC \| _AC0_COPY);

	15 imm32 R0, 0xf64722bc;

	16 R0.L = R0.L >>> 0xd (S);

	17 checkreg R0, 0xf6470001;

	18 checkreg ASTAT, (0x64800010 \| _VS \| _AV1S \| _AV0S \| _AQ \| _CC \| _AC0_COP Y);

	19

	20 dmm32 ASTAT, (0x70300e10 \| _VS \| _AQ \| _AC0_COPY \| _AN);

	21 imm32 R5, 0x2a8771ff;

	22 R5 = R5 >>> 0x1d (V);

	23 checkreg R5, 0x54388ff8;

	24 checkreg ASTAT, (0x70300e10 \| _VS \| _V \| _AQ \| _V_COPY \| _AC0_COPY \| _AN );

	25

	26 dmm32 ASTAT, (0x04600000 \| _VS \| _AV1S \| _AC0 \| _AQ \| _CC \| _AC0_COPY);

	27 imm32 R6, 0x0c3a7fff;

	28 imm32 R7, 0x03460f23;

	29 R6.H = R7.L >>> 0x1f (S);

	30 checkreg R6, 0x1e467fff;

	31 checkreg ASTAT, (0x04600000 \| _VS \| _AV1S \| _AC0 \| _AQ \| _CC \| _AC0_COPY );

	32

	33 dmm32 ASTAT, (0x40704010 \| _VS \| _V \| _AV1S \| _AV0S \| _AC0 \| _CC \| _V_CO PY \| _AC0_COPY \| _AN);

	34 imm32 R3, 0xfa2cee19;

	35 imm32 R5, 0xfa2cee17;

	36 R3.L = R5.H >>> 0xd (S);

	37 checkreg R3, 0xfa2cffff;

	38 checkreg ASTAT, (0x40704010 \| _VS \| _AV1S \| _AV0S \| _AC0 \| _CC \| _AC0_CO PY \| _AN);

	39

	40 dmm32 ASTAT, (0x20308c90 \| _VS \| _AV1S \| _AV0S \| _CC \| _AN);

	41 imm32 R2, 0xd4b70c2f;

	42 imm32 R5, 0x0279838b;

	43 R5.H = R2.H >>> 0x1f (S);

	44 checkreg R5, 0xa96e838b;

	45 checkreg ASTAT, (0x20308c90 \| _VS \| _AV1S \| _AV0S \| _CC \| _AN);

	46

	47 dmm32 ASTAT, (0x10a08690 \| _VS \| _V \| _AV0S \| _AC1 \| _AC0 \| _AQ \| _V_COP Y \| _AC0_COPY \| _AN);

	48 imm32 R4, 0x5cae64fc;

	49 imm32 R6, 0x288e1461;

	50 R4.H = R6.L >>> 0x1e (S);

	51 checkreg R4, 0x518464fc;

	52 checkreg ASTAT, (0x10a08690 \| _VS \| _AV0S \| _AC1 \| _AC0 \| _AQ \| _AC0_COP Y);

	53

	54 dmm32 ASTAT, (0x48908010 \| _VS \| _AV1S \| _AV0S \| _AC1 \| _AC0 \| _AQ \| _CC );

	55 imm32 R1, 0x4f8f004a;

	56 imm32 R5, 0x7fff70c1;

	57 R5.L = R1.L >>> 0x1e (S);

	58 checkreg R5, 0x7fff0128;

	59 checkreg ASTAT, (0x48908010 \| _VS \| _AV1S \| _AV0S \| _AC1 \| _AC0 \| _AQ \| _CC);

	60

	61 dmm32 ASTAT, (0x00f00490 \| _VS \| _AV0S \| _AV0 \| _AQ \| _CC \| _AC0_COPY \| _AN);

	62 dmm32 A0.w, 0x32b127c8;

	63 dmm32 A0.x, 0x0000001a;

	64 A0 = A0 >>> 0x6;

	65 checkreg A0.w, 0x68cac49f;

	66 checkreg A0.x, 0x00000000;

	67 checkreg ASTAT, (0x00f00490 \| _VS \| _AV0S \| _AQ \| _CC \| _AC0_COPY);

	68

	69 pass

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