sim/testsuite/sim/bfin/random_0014.S - Issue 11969036: Merge GDB 7.5.1

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Side by Side Diff: sim/testsuite/sim/bfin/random_0014.S

Issue 11969036: Merge GDB 7.5.1 (Closed) Base URL: http://git.chromium.org/native_client/nacl-gdb.git@master

Patch Set: Created 7 years, 11 months ago

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	1 # Test a few corner cases with various shift insns

	2 # mach: bfin

	3 #include "test.h"

	4 .include "testutils.inc"

	5

	6 start

	7

	8 dmm32 ASTAT, (0x38404290 \| _VS \| _V \| _AC1 \| _AC0 \| _V_COPY \| _AC0_COPY \| _AN);

	9 dmm32 A0.w, 0xf53d356e;

	10 dmm32 A0.x, 0xffffffff;

	11 imm32 R5, 0xaa156b54;

	12 A0 = ASHIFT A0 BY R5.L;

	13 checkreg A0.w, 0x56e00000;

	14 checkreg A0.x, 0xffffffd3;

	15 checkreg ASTAT, (0x38404290 \| _VS \| _V \| _AC1 \| _AC0 \| _V_COPY \| _AC0_CO PY \| _AN);

	16

	17 dmm32 ASTAT, (0x28e00410 \| _VS \| _V \| _AV1S \| _AV1 \| _AC1 \| _V_COPY);

	18 dmm32 A0.w, 0x1dfd2a85;

	19 dmm32 A0.x, 0xffffffbe;

	20 imm32 R2, 0x4b7cf707;

	21 A0 = LSHIFT A0 BY R2.L;

	22 checkreg A0.w, 0xfe954280;

	23 checkreg A0.x, 0x0000000e;

	24 checkreg ASTAT, (0x28e00410 \| _VS \| _V \| _AV1S \| _AV1 \| _AC1 \| _V_COPY);

	25

	26 dmm32 ASTAT, (0x60404e00 \| _VS \| _V \| _AV1S \| _AV0S \| _AC0 \| _AQ \| _V_CO PY \| _AC0_COPY \| _AN);

	27 dmm32 A1.w, 0xd4aa6e10;

	28 dmm32 A1.x, 0xffffffff;

	29 imm32 R4, 0xb4bb3054;

	30 A1 = ASHIFT A1 BY R4.L;

	31 checkreg A1.w, 0xe1000000;

	32 checkreg A1.x, 0xffffffa6;

	33 checkreg ASTAT, (0x60404e00 \| _VS \| _V \| _AV1S \| _AV0S \| _AC0 \| _AQ \| _V _COPY \| _AC0_COPY \| _AN);

	34

	35 dmm32 ASTAT, (0x00608810 \| _V \| _AV1S \| _AV0S \| _V_COPY \| _AC0_COPY \| _A N);

	36 dmm32 A1.w, 0x0dbadb4f;

	37 dmm32 A1.x, 0x00000035;

	38 imm32 R3, 0x3cc3f7db;

	39 A1 = LSHIFT A1 BY R3.L;

	40 checkreg A1.w, 0x78000000;

	41 checkreg A1.x, 0xffffffda;

	42 checkreg ASTAT, (0x00608810 \| _V \| _AV1S \| _AV0S \| _V_COPY \| _AC0_COPY \| _AN);

	43

	44 dmm32 ASTAT, (0x14900e10 \| _VS \| _AC0 \| _CC \| _AC0_COPY);

	45 imm32 R0, 0x6286ee56;

	46 imm32 R7, 0x5cd969c5;

	47 R0 = ASHIFT R0 BY R7.L;

	48 checkreg R0, 0x50ddcac0;

	49 checkreg ASTAT, (0x14900e10 \| _VS \| _V \| _AC0 \| _CC \| _V_COPY \| _AC0_COP Y);

	50

	51 dmm32 ASTAT, (0x28904a90 \| _VS \| _V \| _AV0S \| _V_COPY \| _AZ);

	52 imm32 R0, 0x00000000;

	53 imm32 R5, 0x00008000;

	54 imm32 R6, 0x03488f9a;

	55 R0.L = ASHIFT R5.L BY R6.L;

	56 checkreg ASTAT, (0x28904a90 \| _VS \| _V \| _AV0S \| _V_COPY \| _AZ);

	57

	58 dmm32 ASTAT, (0x3c10c890 \| _VS \| _AV1S \| _AV0S \| _AC0 \| _AQ \| _AC0_COPY) ;

	59 imm32 R1, 0x29162006;

	60 imm32 R3, 0xffff0345;

	61 imm32 R4, 0x8ff5e6bb;

	62 R1.H = ASHIFT R4.H BY R3.L;

	63 checkreg R1, 0xfea02006;

	64 checkreg ASTAT, (0x3c10c890 \| _VS \| _V \| _AV1S \| _AV0S \| _AC0 \| _AQ \| _V _COPY \| _AC0_COPY \| _AN);

	65

	66 dmm32 ASTAT, (0x78600e00 \| _VS \| _AV1S \| _AV0S \| _AC0 \| _AQ \| _CC);

	67 imm32 R0, 0xd5b1804d;

	68 imm32 R1, 0x522c817d;

	69 imm32 R5, 0xfca6f990;

	70 R1.H = ASHIFT R5.H BY R0.L;

	71 checkreg R1, 0xc000817d;

	72 checkreg ASTAT, (0x78600e00 \| _VS \| _V \| _AV1S \| _AV0S \| _AC0 \| _AQ \| _C C \| _V_COPY \| _AN);

	73

	74 dmm32 ASTAT, (0x64b04890 \| _VS \| _V \| _AV0S \| _AV0 \| _AC1 \| _AQ \| _CC \| _V_COPY \| _AC0_COPY \| _AN);

	75 imm32 R4, 0x80000000;

	76 imm32 R6, 0x4e840a3e;

	77 imm32 R7, 0x20102e48;

	78 R6.L = ASHIFT R4.H BY R7.L;

	79 checkreg R6, 0x4e840000;

	80 checkreg ASTAT, (0x64b04890 \| _VS \| _V \| _AV0S \| _AV0 \| _AC1 \| _AQ \| _CC \| _V_COPY \| _AC0_COPY \| _AZ);

	81

	82 pass

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