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Issue 11969036: Merge GDB 7.5.1 (Closed) Base URL: http://git.chromium.org/native_client/nacl-gdb.git@master
Patch Set: Created 7 years, 11 months ago
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1 //Original:/testcases/core/c_dsp32shiftim_amix/c_dsp32shiftim_amix.dsp 1 //Original:/testcases/core/c_dsp32shiftim_amix/c_dsp32shiftim_amix.dsp
2 # mach: bfin 2 # mach: bfin
3 3
4 .include "testutils.inc" 4 .include "testutils.inc"
5 start 5 start
6 6
7 7
8 // Spec Reference: dsp32shiftimm ashift: mix 8 // Spec Reference: dsp32shiftimm ashift: mix
9 9
10 10
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107 CHECKREG r6, 0x80fe00f0; 107 CHECKREG r6, 0x80fe00f0;
108 CHECKREG r7, 0x81fc01e0; 108 CHECKREG r7, 0x81fc01e0;
109 109
110 imm32 r0, 0xc80fe00f; 110 imm32 r0, 0xc80fe00f;
111 imm32 r2, 0xe40fe00f; 111 imm32 r2, 0xe40fe00f;
112 R6 = R0 << 4 (S); /* r6 = 0x80000000 zero bubble tru MSB */ 112 R6 = R0 << 4 (S); /* r6 = 0x80000000 zero bubble tru MSB */
113 R7 = R2 << 5 (S); /* r7 = 0x80000000 */ 113 R7 = R2 << 5 (S); /* r7 = 0x80000000 */
114 CHECKREG r6, 0x80000000; 114 CHECKREG r6, 0x80000000;
115 CHECKREG r7, 0x80000000; 115 CHECKREG r7, 0x80000000;
116 116
117 imm32 r0, 0xFFFFFFF4;
118 imm32 r2, 0xFFF00001;
119 R6 = R0 << 31 (S); /* r6 = 0x80000000 */
120 R7 = R2 << 31 (S); /* r7 = 0x80000000 */
121 CHECKREG r6, 0x80000000;
122 CHECKREG r7, 0x80000000;
123
117 124
118 // Ashift : NEGATIVE data, count (-)=right (half reg) Working ok 125 // Ashift : NEGATIVE data, count (-)=right (half reg) Working ok
119 imm32 r0, 0x80f080f0; 126 imm32 r0, 0x80f080f0;
120 imm32 r1, -1; 127 imm32 r1, -1;
121 imm32 r2, 0x80f080f0; 128 imm32 r2, 0x80f080f0;
122 imm32 r3, -2; 129 imm32 r3, -2;
123 R4.H = R0.H >>> 1; 130 R4.H = R0.H >>> 1;
124 R4.L = R0.L >>> 1; /* r4 = 0xc078c078 */ 131 R4.L = R0.L >>> 1; /* r4 = 0xc078c078 */
125 R5.H = R2.H >>> 2; 132 R5.H = R2.H >>> 2;
126 R5.L = R2.L >>> 2; /* r4 = 0xe03ce03c */ 133 R5.L = R2.L >>> 2; /* r4 = 0xe03ce03c */
127 CHECKREG r4, 0xc078c078; 134 CHECKREG r4, 0xc078c078;
128 CHECKREG r5, 0xe03ce03c; 135 CHECKREG r5, 0xe03ce03c;
129 R6 = R0 >>> 1 (V); /* r6 = 0xc078c078 */ 136 R6 = R0 >>> 1 (V); /* r6 = 0xc078c078 */
130 R7 = R2 >>> 2 (V); /* r7 = 0xe03ce03c */ 137 R7 = R2 >>> 2 (V); /* r7 = 0xe03ce03c */
131 CHECKREG r6, 0xc078c078; 138 CHECKREG r6, 0xc078c078;
132 CHECKREG r7, 0xe03ce03c; 139 CHECKREG r7, 0xe03ce03c;
133 140
134 imm32 r1, -3; 141 imm32 r1, -3;
135 imm32 r3, -4; 142 imm32 r3, -4;
136 R6 = R0 >>> 3; /* r6 = 0xf01e101e */ 143 R6 = R0 >>> 3; /* r6 = 0xf01e101e */
137 R7 = R2 >>> 4; /* r7 = 0xf80f080f */ 144 R7 = R2 >>> 4; /* r7 = 0xf80f080f */
138 CHECKREG r6, 0xf01e101e; 145 CHECKREG r6, 0xf01e101e;
139 CHECKREG r7, 0xf80f080f; 146 CHECKREG r7, 0xf80f080f;
140 147
141 148
142 pass 149 pass
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