Merge GDB 7.5.1

sim/sh/interp.c

 /* Simulator for the Renesas (formerly Hitachi) / SuperH Inc. SH architecture.
 
    Written by Steve Chamberlain of Cygnus Support.
    sac@cygnus.com
 
    This file is part of SH sim
 
 
                 THIS SOFTWARE IS NOT COPYRIGHTED
 
@@ skipping 844 matching lines @@
 #ifdef ACE_FAST
 
 #define MA(n)
 #define L(x)
 #define TL(x)
 #define TB(x)
 
 #else
 
 #define MA(n) \
-  do { memstalls += ((((int) PC & 3) != 0) ? (n) : ((n) - 1)); } while (0)
+  do { memstalls += ((((long) PC & 3) != 0) ? (n) : ((n) - 1)); } while (0)
 
 #define L(x)   thislock = x;
 #define TL(x)  if ((x) == prevlock) stalls++;
 #define TB(x,y)  if ((x) == prevlock || (y) == prevlock) stalls++;
 
 #endif
 
 #if defined(__GO32__)
 int sim_memory_size = 19;
 #else
@@ skipping 1473 matching lines @@
       break;
     case SIM_SH_BANK_IVN_REGNUM:
       saved_state.asregs.regstack[gdb_bank_number].regs[REGBANK_IVN] = val;
       break;
     case SIM_SH_BANK_MACH_REGNUM:
       saved_state.asregs.regstack[gdb_bank_number].regs[REGBANK_MACH] = val;
       break;
     default:
       return 0;
     }
-  return -1;
+  return length;
 }
 
 int
 sim_fetch_register (sd, rn, memory, length)
      SIM_DESC sd;
      int rn;
      unsigned char *memory;
      int length;
 {
   int val;
@@ skipping 154 matching lines @@
     case SIM_SH_BANK_IVN_REGNUM:
       val = saved_state.asregs.regstack[gdb_bank_number].regs[REGBANK_IVN];
       break;
     case SIM_SH_BANK_MACH_REGNUM:
       val = saved_state.asregs.regstack[gdb_bank_number].regs[REGBANK_MACH];
       break;
     default:
       return 0;
     }
   * (int *) memory = swap (val);
-  return -1;
+  return length;
 }
 
 int
 sim_trace (sd)
      SIM_DESC sd;
 {
   tracing = 1;
   sim_resume (sd, 0, 0);
   tracing = 0;
   return 1;
@@ skipping 241 matching lines @@
      host_callback *p;
 {
   callback = p;
 }
 
 char **
 sim_complete_command (SIM_DESC sd, char *text, char *word)
 {
   return NULL;
 }