Merge GDB 7.5.1

sim/rx/load.c

 /* load.c --- loading object files into the RX simulator.
 
 Copyright (C) 2005, 2007-2012 Free Software Foundation, Inc.
 Contributed by Red Hat, Inc.
 
 This file is part of the GNU simulators.
 
 This program is free software; you can redistribute it and/or modify
 it under the terms of the GNU General Public License as published by
 the Free Software Foundation; either version 3 of the License, or
@@ skipping 10 matching lines @@
 
 #include "config.h"
 #include <stdlib.h>
 #include <stdio.h>
 #include <string.h>
 
 #include "bfd.h"
 #include "libbfd.h"
 #include "cpu.h"
 #include "mem.h"
+#include "load.h"
 #include "elf/internal.h"
 #include "elf/common.h"
 
+/* Helper function for invoking a GDB-specified printf.  */
+static void
+xprintf (host_callback *callback, const char *fmt, ...)
+{
+  va_list ap;
+
+  va_start (ap, fmt);
+
+  (*callback->vprintf_filtered) (callback, fmt, ap);
+
+  va_end (ap);
+}
+
+/* Given a file offset, look up the section name.  */
+static const char *
+find_section_name_by_offset (bfd *abfd, file_ptr filepos)
+{
+  asection *s;
+
+  for (s = abfd->sections; s; s = s->next)
+    if (s->filepos == filepos)
+      return bfd_get_section_name (abfd, s);
+
+  return "(unknown)";
+}
+
 /* A note about endianness and swapping...
 
    The RX chip is CISC-like in that the opcodes are variable length
    and are read as a stream of bytes.  However, the chip itself shares
    the code prefetch block with the data fetch block, so when it's
    configured for big endian mode, the memory fetched for opcodes is
    word-swapped.  To compensate for this, the ELF file has the code
    sections pre-swapped.  Our BFD knows this, and for the convenience
    of all the other tools, hides this swapping at a very low level.
    I.e.  it swaps words on the way out and on the way back in.
 
    Fortunately the iovector routines are unaffected by this, so we
    can use them to read in the segments directly, without having
    to worry about byte swapping anything.
 
    However, our opcode decoder and disassemblers need to swap the data
    after reading it from the chip memory, just like the chip does.
    All in all, the code words are swapped four times between the
    assembler and our decoder.
 
    If the chip is running in little-endian mode, no swapping is done
    anywhere.  Note also that the *operands* within opcodes are always
    encoded in little-endian format.  */
 
 void
-rx_load (bfd *prog)
+rx_load (bfd *prog, host_callback *callback)
 {
   unsigned long highest_addr_loaded = 0;
   Elf_Internal_Phdr * phdrs;
   long sizeof_phdrs;
   int num_headers;
   int i;
 
   rx_big_endian = bfd_big_endian (prog);
 
   /* Note we load by ELF program header not by BFD sections.
@@ skipping 28 matching lines @@
       file_ptr offset;
 
       size = p->p_filesz;
       if (size <= 0)
         continue;
 
       base = p->p_paddr;
       if (verbose > 1)
         fprintf (stderr, "[load segment: lma=%08x vma=%08x size=%08x]\n",
                  (int) base, (int) p->p_vaddr, (int) size);
+      if (callback)
+        xprintf (callback,
+                 "Loading section %s, size %#lx lma %08lx vma %08lx\n",
+                 find_section_name_by_offset (prog, p->p_offset),
+                 size, base, p->p_vaddr);
 
       buf = malloc (size);
       if (buf == NULL)
         {
           fprintf (stderr, "Failed to allocate buffer to hold program segment\n");
           continue;
         }
       
       offset = p->p_offset;
       if (prog->iovec->bseek (prog, offset, SEEK_SET) != 0)
@@ skipping 24 matching lines @@
       heaptop = heapbottom = 0;
     }
 
   reset_decoder ();
 
   if (verbose > 1)
     fprintf (stderr, "[start pc=%08x %s]\n",
              (unsigned int) regs.r_pc,
              rx_big_endian ? "BE" : "LE");
 }