sim/bfin/machs.h - Issue 11969036: Merge GDB 7.5.1

Side by Side Diff

Use n/p to move between diff chunks; N/P to move between comments. Draft comments are only viewable by you.

Keyboard Shortcuts

	File
u :	up to issue
j / k :	jump to file after / before current file
J / K :	jump to next file with a comment after / before current file
	Side-by-side diff
i :	toggle intra-line diffs
e :	expand all comments
c :	collapse all comments
s :	toggle showing all comments
n / p :	next / previous diff chunk or comment
N / P :	next / previous comment
<Up> / <Down> :	next / previous line

	Issue
u :	up to list of issues
j / k :	jump to patch after / before current patch
o / <Enter> :	open current patch in side-by-side view
i :	open current patch in unified diff view

	Issue List
j / k :	jump to issue after / before current issue
o / <Enter> :	open current issue

Side by Side Diff: sim/bfin/machs.h

Issue 11969036: Merge GDB 7.5.1 (Closed) Base URL: http://git.chromium.org/native_client/nacl-gdb.git@master

Patch Set: Created 7 years, 11 months ago

Use n/p to move between diff chunks; N/P to move between comments. Draft comments are only viewable by you.

Jump to:

View unified diff | Download patch

OLD	NEW
1 /* Simulator for Analog Devices Blackfin processors.	1 /* Simulator for Analog Devices Blackfin processors.

2	2

3 Copyright (C) 2005-2012 Free Software Foundation, Inc.	3 Copyright (C) 2005-2012 Free Software Foundation, Inc.

4 Contributed by Analog Devices, Inc.	4 Contributed by Analog Devices, Inc.

5	5

6 This file is part of simulators.	6 This file is part of simulators.

7	7

8 This program is free software; you can redistribute it and/or modify	8 This program is free software; you can redistribute it and/or modify

9 it under the terms of the GNU General Public License as published by	9 it under the terms of the GNU General Public License as published by

10 the Free Software Foundation; either version 3 of the License, or	10 the Free Software Foundation; either version 3 of the License, or

(...skipping 64 matching lines...) Expand 10 before \| Expand all \| Expand 10 after Loading...
75 #define BFIN_MMR_DMAC1_BASE 0xFFC01C00	75 #define BFIN_MMR_DMAC1_BASE 0xFFC01C00

76 #define BFIN_MMR_EBIU_AMC_SIZE (4 * 3)	76 #define BFIN_MMR_EBIU_AMC_SIZE (4 * 3)

77 #define BF50X_MMR_EBIU_AMC_SIZE 0x28	77 #define BF50X_MMR_EBIU_AMC_SIZE 0x28

78 #define BF54X_MMR_EBIU_AMC_SIZE (4 * 7)	78 #define BF54X_MMR_EBIU_AMC_SIZE (4 * 7)

79 #define BFIN_MMR_EBIU_DDRC_SIZE 0xb0	79 #define BFIN_MMR_EBIU_DDRC_SIZE 0xb0

80 #define BFIN_MMR_EBIU_SDC_SIZE (4 * 4)	80 #define BFIN_MMR_EBIU_SDC_SIZE (4 * 4)

81 #define BFIN_MMR_EMAC_BASE 0xFFC03000	81 #define BFIN_MMR_EMAC_BASE 0xFFC03000

82 #define BFIN_MMR_EMAC_SIZE 0x200	82 #define BFIN_MMR_EMAC_SIZE 0x200

83 #define BFIN_MMR_EPPI_SIZE 0x40	83 #define BFIN_MMR_EPPI_SIZE 0x40

84 #define BFIN_MMR_GPIO_SIZE (17 * 4)	84 #define BFIN_MMR_GPIO_SIZE (17 * 4)

	85 #define BFIN_MMR_GPIO2_SIZE (8 * 4)

85 #define BFIN_MMR_GPTIMER_SIZE (4 * 4)	86 #define BFIN_MMR_GPTIMER_SIZE (4 * 4)

86 #define BFIN_MMR_NFC_SIZE 0x50	87 #define BFIN_MMR_NFC_SIZE 0x50

87 /* XXX: Not exactly true; it's two sets of 4 regs near each other:	88 /* XXX: Not exactly true; it's two sets of 4 regs near each other:

88 0xFFC03600 0x10 - Control	89 0xFFC03600 0x10 - Control

89 0xFFC03680 0x10 - Data */	90 0xFFC03680 0x10 - Data */

90 #define BFIN_MMR_OTP_SIZE 0xa0	91 #define BFIN_MMR_OTP_SIZE 0xa0

	92 #define BFIN_MMR_PINT_SIZE 0x28

91 #define BFIN_MMR_PLL_BASE 0xFFC00000	93 #define BFIN_MMR_PLL_BASE 0xFFC00000

92 #define BFIN_MMR_PLL_SIZE (4 * 6)	94 #define BFIN_MMR_PLL_SIZE (4 * 6)

93 #define BFIN_MMR_PPI_SIZE (4 * 5)	95 #define BFIN_MMR_PPI_SIZE (4 * 5)

94 #define BFIN_MMR_RTC_SIZE (4 * 6)	96 #define BFIN_MMR_RTC_SIZE (4 * 6)

95 #define BFIN_MMR_SIC_BASE 0xFFC00100	97 #define BFIN_MMR_SIC_BASE 0xFFC00100

96 #define BFIN_MMR_SIC_SIZE 0x100	98 #define BFIN_MMR_SIC_SIZE 0x100

97 #define BFIN_MMR_SPI_SIZE (4 * 7)	99 #define BFIN_MMR_SPI_SIZE (4 * 7)

98 #define BFIN_MMR_TWI_SIZE 0x90	100 #define BFIN_MMR_TWI_SIZE 0x90

99 #define BFIN_MMR_WDOG_SIZE (4 * 3)	101 #define BFIN_MMR_WDOG_SIZE (4 * 3)

100 #define BFIN_MMR_UART_SIZE 0x30	102 #define BFIN_MMR_UART_SIZE 0x30

101 #define BFIN_MMR_UART2_SIZE 0x30	103 #define BFIN_MMR_UART2_SIZE 0x30

102	104

103 #endif	105 #endif

OLD	NEW

« no previous file with comments | « sim/bfin/interp.c ('k') | sim/bfin/machs.c » ('j') | no next file with comments »