Merge GDB 7.5.1

sim/bfin/machs.c

 /* Simulator for Analog Devices Blackfin processors.
 
    Copyright (C) 2005-2012 Free Software Foundation, Inc.
-   Contributed by Analog Devices, Inc.
+   Contributed by Analog Devices, Inc. and Mike Frysinger.
 
    This file is part of simulators.
 
    This program is free software; you can redistribute it and/or modify
    it under the terms of the GNU General Public License as published by
    the Free Software Foundation; either version 3 of the License, or
    (at your option) any later version.
 
    This program is distributed in the hope that it will be useful,
    but WITHOUT ANY WARRANTY; without even the implied warranty of
@@ skipping 863 matching lines @@
 #define bf54x_chipid 0x27de
 #define bf542_chipid bf54x_chipid
 #define bf544_chipid bf54x_chipid
 #define bf547_chipid bf54x_chipid
 #define bf548_chipid bf54x_chipid
 #define bf549_chipid bf54x_chipid
 static const struct bfin_memory_layout bf54x_mem[] =
 {
   LAYOUT (0xFFC00800, 0x60, read_write),        /* SPORT0 stub XXX: not on BF542/4 */
   LAYOUT (0xFFC00900, 0x60, read_write),        /* SPORT1 stub */
-  LAYOUT (0xFFC01400, 0x200, read_write),       /* PORT/GPIO stub */
   LAYOUT (0xFFC02500, 0x60, read_write),        /* SPORT2 stub */
   LAYOUT (0xFFC02600, 0x60, read_write),        /* SPORT3 stub */
   LAYOUT (0xFFC03800, 0x70, read_write),        /* ATAPI stub */
   LAYOUT (0xFFC03900, 0x100, read_write),       /* RSI stub */
   LAYOUT (0xFFC03C00, 0x500, read_write),       /* MUSB stub */
   LAYOUT (0xFEB00000, 0x20000, read_write_exec),        /* L2 */
   LAYOUT (0xFF800000, 0x4000, read_write),      /* Data A */
   LAYOUT (0xFF804000, 0x4000, read_write),      /* Data A Cache */
   LAYOUT (0xFF900000, 0x4000, read_write),      /* Data B */
   LAYOUT (0xFF904000, 0x4000, read_write),      /* Data B Cache */
   LAYOUT (0xFFA00000, 0x8000, read_write_exec), /* Inst A [1] */
   LAYOUT (0xFFA08000, 0x4000, read_write_exec), /* Inst B [1] */
   LAYOUT (0xFFA10000, 0x4000, read_write_exec), /* Inst Cache [1] */
 };
 #define bf542_mem bf54x_mem
 #define bf544_mem bf54x_mem
 #define bf547_mem bf54x_mem
 #define bf548_mem bf54x_mem
 #define bf549_mem bf54x_mem
 static const struct bfin_dev_layout bf542_dev[] =
 {
   DEVICE (0xFFC00200, BFIN_MMR_WDOG_SIZE,      "bfin_wdog@0"),
   DEVICE (0xFFC00300, BFIN_MMR_RTC_SIZE,       "bfin_rtc"),
   DEVICE (0xFFC00400, BFIN_MMR_UART2_SIZE,     "bfin_uart2@0"),
   DEVICE (0xFFC00500, BFIN_MMR_SPI_SIZE,       "bfin_spi@0"),
   DEVICE (0xFFC00700, BFIN_MMR_TWI_SIZE,       "bfin_twi@0"),
   DEVICE (0xFFC00A00, BF54X_MMR_EBIU_AMC_SIZE, "bfin_ebiu_amc"),
   DEVICE (0xFFC00A20, BFIN_MMR_EBIU_DDRC_SIZE, "bfin_ebiu_ddrc"),
  _DEVICE (0xFFC01300, BFIN_MMR_EPPI_SIZE,      "bfin_eppi@1", 1),
+  DEVICE (0xFFC01400, BFIN_MMR_PINT_SIZE,      "bfin_pint@0"),
+  DEVICE (0xFFC01430, BFIN_MMR_PINT_SIZE,      "bfin_pint@1"),
+ _DEVICE (0xFFC01460, BFIN_MMR_PINT_SIZE,      "bfin_pint@2", 2),
+ _DEVICE (0xFFC01490, BFIN_MMR_PINT_SIZE,      "bfin_pint@3", 2),
+  DEVICE (0xFFC014C0, BFIN_MMR_GPIO2_SIZE,     "bfin_gpio2@0"),
+  DEVICE (0xFFC014E0, BFIN_MMR_GPIO2_SIZE,     "bfin_gpio2@1"),
+  DEVICE (0xFFC01500, BFIN_MMR_GPIO2_SIZE,     "bfin_gpio2@2"),
+  DEVICE (0xFFC01520, BFIN_MMR_GPIO2_SIZE,     "bfin_gpio2@3"),
+  DEVICE (0xFFC01540, BFIN_MMR_GPIO2_SIZE,     "bfin_gpio2@4"),
+  DEVICE (0xFFC01560, BFIN_MMR_GPIO2_SIZE,     "bfin_gpio2@5"),
+  DEVICE (0xFFC01580, BFIN_MMR_GPIO2_SIZE,     "bfin_gpio2@6"),
+  DEVICE (0xFFC015A0, BFIN_MMR_GPIO2_SIZE,     "bfin_gpio2@7"),
+  DEVICE (0xFFC015C0, BFIN_MMR_GPIO2_SIZE,     "bfin_gpio2@8"),
+  DEVICE (0xFFC015E0, BFIN_MMR_GPIO2_SIZE,     "bfin_gpio2@9"),
   DEVICE (0xFFC01600, BFIN_MMR_GPTIMER_SIZE,   "bfin_gptimer@0"),
   DEVICE (0xFFC01610, BFIN_MMR_GPTIMER_SIZE,   "bfin_gptimer@1"),
   DEVICE (0xFFC01620, BFIN_MMR_GPTIMER_SIZE,   "bfin_gptimer@2"),
   DEVICE (0xFFC01630, BFIN_MMR_GPTIMER_SIZE,   "bfin_gptimer@3"),
   DEVICE (0xFFC01640, BFIN_MMR_GPTIMER_SIZE,   "bfin_gptimer@4"),
   DEVICE (0xFFC01650, BFIN_MMR_GPTIMER_SIZE,   "bfin_gptimer@5"),
   DEVICE (0xFFC01660, BFIN_MMR_GPTIMER_SIZE,   "bfin_gptimer@6"),
   DEVICE (0xFFC01670, BFIN_MMR_GPTIMER_SIZE,   "bfin_gptimer@7"),
   DEVICE (0xFFC02000, BFIN_MMR_UART2_SIZE,     "bfin_uart2@1"),
  _DEVICE (0xFFC02100, BFIN_MMR_UART2_SIZE,     "bfin_uart2@2", 1),
@@ skipping 10 matching lines @@
   DEVICE (0xFFC00400, BFIN_MMR_UART2_SIZE,     "bfin_uart2@0"),
   DEVICE (0xFFC00500, BFIN_MMR_SPI_SIZE,       "bfin_spi@0"),
   DEVICE (0xFFC00600, BFIN_MMR_GPTIMER_SIZE,   "bfin_gptimer@8"),
   DEVICE (0xFFC00610, BFIN_MMR_GPTIMER_SIZE,   "bfin_gptimer@9"),
   DEVICE (0xFFC00620, BFIN_MMR_GPTIMER_SIZE,   "bfin_gptimer@10"),
   DEVICE (0xFFC00700, BFIN_MMR_TWI_SIZE,       "bfin_twi@0"),
   DEVICE (0xFFC00A00, BF54X_MMR_EBIU_AMC_SIZE, "bfin_ebiu_amc"),
   DEVICE (0xFFC00A20, BFIN_MMR_EBIU_DDRC_SIZE, "bfin_ebiu_ddrc"),
  _DEVICE (0xFFC01000, BFIN_MMR_EPPI_SIZE,      "bfin_eppi@0", 1),
  _DEVICE (0xFFC01300, BFIN_MMR_EPPI_SIZE,      "bfin_eppi@1", 1),
+  DEVICE (0xFFC01400, BFIN_MMR_PINT_SIZE,      "bfin_pint@0"),
+  DEVICE (0xFFC01430, BFIN_MMR_PINT_SIZE,      "bfin_pint@1"),
+ _DEVICE (0xFFC01460, BFIN_MMR_PINT_SIZE,      "bfin_pint@2", 2),
+ _DEVICE (0xFFC01490, BFIN_MMR_PINT_SIZE,      "bfin_pint@3", 2),
+  DEVICE (0xFFC014C0, BFIN_MMR_GPIO2_SIZE,     "bfin_gpio2@0"),
+  DEVICE (0xFFC014E0, BFIN_MMR_GPIO2_SIZE,     "bfin_gpio2@1"),
+  DEVICE (0xFFC01500, BFIN_MMR_GPIO2_SIZE,     "bfin_gpio2@2"),
+  DEVICE (0xFFC01520, BFIN_MMR_GPIO2_SIZE,     "bfin_gpio2@3"),
+  DEVICE (0xFFC01540, BFIN_MMR_GPIO2_SIZE,     "bfin_gpio2@4"),
+  DEVICE (0xFFC01560, BFIN_MMR_GPIO2_SIZE,     "bfin_gpio2@5"),
+  DEVICE (0xFFC01580, BFIN_MMR_GPIO2_SIZE,     "bfin_gpio2@6"),
+  DEVICE (0xFFC015A0, BFIN_MMR_GPIO2_SIZE,     "bfin_gpio2@7"),
+  DEVICE (0xFFC015C0, BFIN_MMR_GPIO2_SIZE,     "bfin_gpio2@8"),
+  DEVICE (0xFFC015E0, BFIN_MMR_GPIO2_SIZE,     "bfin_gpio2@9"),
   DEVICE (0xFFC01600, BFIN_MMR_GPTIMER_SIZE,   "bfin_gptimer@0"),
   DEVICE (0xFFC01610, BFIN_MMR_GPTIMER_SIZE,   "bfin_gptimer@1"),
   DEVICE (0xFFC01620, BFIN_MMR_GPTIMER_SIZE,   "bfin_gptimer@2"),
   DEVICE (0xFFC01630, BFIN_MMR_GPTIMER_SIZE,   "bfin_gptimer@3"),
   DEVICE (0xFFC01640, BFIN_MMR_GPTIMER_SIZE,   "bfin_gptimer@4"),
   DEVICE (0xFFC01650, BFIN_MMR_GPTIMER_SIZE,   "bfin_gptimer@5"),
   DEVICE (0xFFC01660, BFIN_MMR_GPTIMER_SIZE,   "bfin_gptimer@6"),
   DEVICE (0xFFC01670, BFIN_MMR_GPTIMER_SIZE,   "bfin_gptimer@7"),
   DEVICE (0xFFC02000, BFIN_MMR_UART2_SIZE,     "bfin_uart2@1"),
  _DEVICE (0xFFC02100, BFIN_MMR_UART2_SIZE,     "bfin_uart2@2", 1),
@@ skipping 11 matching lines @@
   DEVICE (0xFFC00400, BFIN_MMR_UART2_SIZE,     "bfin_uart2@0"),
   DEVICE (0xFFC00500, BFIN_MMR_SPI_SIZE,       "bfin_spi@0"),
   DEVICE (0xFFC00600, BFIN_MMR_GPTIMER_SIZE,   "bfin_gptimer@8"),
   DEVICE (0xFFC00610, BFIN_MMR_GPTIMER_SIZE,   "bfin_gptimer@9"),
   DEVICE (0xFFC00620, BFIN_MMR_GPTIMER_SIZE,   "bfin_gptimer@10"),
   DEVICE (0xFFC00700, BFIN_MMR_TWI_SIZE,       "bfin_twi@0"),
   DEVICE (0xFFC00A00, BF54X_MMR_EBIU_AMC_SIZE, "bfin_ebiu_amc"),
   DEVICE (0xFFC00A20, BFIN_MMR_EBIU_DDRC_SIZE, "bfin_ebiu_ddrc"),
  _DEVICE (0xFFC01000, BFIN_MMR_EPPI_SIZE,      "bfin_eppi@0", 1),
  _DEVICE (0xFFC01300, BFIN_MMR_EPPI_SIZE,      "bfin_eppi@1", 1),
+  DEVICE (0xFFC01400, BFIN_MMR_PINT_SIZE,      "bfin_pint@0"),
+  DEVICE (0xFFC01430, BFIN_MMR_PINT_SIZE,      "bfin_pint@1"),
+ _DEVICE (0xFFC01460, BFIN_MMR_PINT_SIZE,      "bfin_pint@2", 2),
+ _DEVICE (0xFFC01490, BFIN_MMR_PINT_SIZE,      "bfin_pint@3", 2),
+  DEVICE (0xFFC014C0, BFIN_MMR_GPIO2_SIZE,     "bfin_gpio2@0"),
+  DEVICE (0xFFC014E0, BFIN_MMR_GPIO2_SIZE,     "bfin_gpio2@1"),
+  DEVICE (0xFFC01500, BFIN_MMR_GPIO2_SIZE,     "bfin_gpio2@2"),
+  DEVICE (0xFFC01520, BFIN_MMR_GPIO2_SIZE,     "bfin_gpio2@3"),
+  DEVICE (0xFFC01540, BFIN_MMR_GPIO2_SIZE,     "bfin_gpio2@4"),
+  DEVICE (0xFFC01560, BFIN_MMR_GPIO2_SIZE,     "bfin_gpio2@5"),
+  DEVICE (0xFFC01580, BFIN_MMR_GPIO2_SIZE,     "bfin_gpio2@6"),
+  DEVICE (0xFFC015A0, BFIN_MMR_GPIO2_SIZE,     "bfin_gpio2@7"),
+  DEVICE (0xFFC015C0, BFIN_MMR_GPIO2_SIZE,     "bfin_gpio2@8"),
+  DEVICE (0xFFC015E0, BFIN_MMR_GPIO2_SIZE,     "bfin_gpio2@9"),
   DEVICE (0xFFC01600, BFIN_MMR_GPTIMER_SIZE,   "bfin_gptimer@0"),
   DEVICE (0xFFC01610, BFIN_MMR_GPTIMER_SIZE,   "bfin_gptimer@1"),
   DEVICE (0xFFC01620, BFIN_MMR_GPTIMER_SIZE,   "bfin_gptimer@2"),
   DEVICE (0xFFC01630, BFIN_MMR_GPTIMER_SIZE,   "bfin_gptimer@3"),
   DEVICE (0xFFC01640, BFIN_MMR_GPTIMER_SIZE,   "bfin_gptimer@4"),
   DEVICE (0xFFC01650, BFIN_MMR_GPTIMER_SIZE,   "bfin_gptimer@5"),
   DEVICE (0xFFC01660, BFIN_MMR_GPTIMER_SIZE,   "bfin_gptimer@6"),
   DEVICE (0xFFC01670, BFIN_MMR_GPTIMER_SIZE,   "bfin_gptimer@7"),
   DEVICE (0xFFC02000, BFIN_MMR_UART2_SIZE,     "bfin_uart2@1"),
  _DEVICE (0xFFC02100, BFIN_MMR_UART2_SIZE,     "bfin_uart2@2", 1),
   DEVICE (0xFFC02200, BFIN_MMR_TWI_SIZE,       "bfin_twi@1"),
   DEVICE (0xFFC02300, BFIN_MMR_SPI_SIZE,       "bfin_spi@1"),
  _DEVICE (0xFFC02400, BFIN_MMR_SPI_SIZE,       "bfin_spi@2", 1),
  _DEVICE (0xFFC02900, BFIN_MMR_EPPI_SIZE,      "bfin_eppi@2", 1),
  _DEVICE (0xFFC03100, BFIN_MMR_UART2_SIZE,     "bfin_uart2@3", 1),
   DEVICE (0xFFC03B00, BFIN_MMR_NFC_SIZE,       "bfin_nfc"),
 };
 #define bf548_dev bf547_dev
 #define bf549_dev bf547_dev
 static const struct bfin_dmac_layout bf54x_dmac[] =
 {
   { BFIN_MMR_DMAC0_BASE, 12, },
   { BFIN_MMR_DMAC1_BASE, 12, },
 };
 #define bf542_dmac bf54x_dmac
 #define bf544_dmac bf54x_dmac
 #define bf547_dmac bf54x_dmac
 #define bf548_dmac bf54x_dmac
 #define bf549_dmac bf54x_dmac
+#define PINT_PIQS(p, b, g) \
+  PORT (p, "piq0@"#b,  g, "p0"), \
+  PORT (p, "piq1@"#b,  g, "p1"), \
+  PORT (p, "piq2@"#b,  g, "p2"), \
+  PORT (p, "piq3@"#b,  g, "p3"), \
+  PORT (p, "piq4@"#b,  g, "p4"), \
+  PORT (p, "piq5@"#b,  g, "p5"), \
+  PORT (p, "piq6@"#b,  g, "p6"), \
+  PORT (p, "piq7@"#b,  g, "p7"), \
+  PORT (p, "piq8@"#b,  g, "p8"), \
+  PORT (p, "piq9@"#b,  g, "p9"), \
+  PORT (p, "piq10@"#b, g, "p10"), \
+  PORT (p, "piq11@"#b, g, "p11"), \
+  PORT (p, "piq12@"#b, g, "p12"), \
+  PORT (p, "piq13@"#b, g, "p13"), \
+  PORT (p, "piq14@"#b, g, "p14"), \
+  PORT (p, "piq15@"#b, g, "p15")
 static const struct bfin_port_layout bf54x_port[] =
 {
   SIC (0,  0, "bfin_pll",          "pll"),
   SIC (0,  1, "bfin_dmac@0",       "stat"),
   SIC (0,  2, "bfin_eppi@0",       "stat"),
   SIC (0,  3, "bfin_sport@0",      "stat"),
   SIC (0,  4, "bfin_sport@1",      "stat"),
   SIC (0,  5, "bfin_spi@0",        "stat"),
   SIC (0,  6, "bfin_uart2@0",      "stat"),
   SIC (0,  7, "bfin_rtc",          "rtc"),
   SIC (0,  8, "bfin_dma@12",       "di"),
   SIC (0,  9, "bfin_dma@0",        "di"),
   SIC (0, 10, "bfin_dma@1",        "di"),
   SIC (0, 11, "bfin_dma@2",        "di"),
   SIC (0, 12, "bfin_dma@3",        "di"),
   SIC (0, 13, "bfin_dma@4",        "di"),
   SIC (0, 14, "bfin_dma@6",        "di"),
   SIC (0, 15, "bfin_dma@7",        "di"),
   SIC (0, 16, "bfin_gptimer@8",    "stat"),
   SIC (0, 17, "bfin_gptimer@9",    "stat"),
   SIC (0, 18, "bfin_gptimer@10",   "stat"),
   SIC (0, 19, "bfin_pint@0",       "stat"),
+  PINT_PIQS ("bfin_pint@0", 0, "bfin_gpio2@0"),
+  PINT_PIQS ("bfin_pint@0", 1, "bfin_gpio2@1"),
   SIC (0, 20, "bfin_pint@1",       "stat"),
+  PINT_PIQS ("bfin_pint@1", 0, "bfin_gpio2@0"),
+  PINT_PIQS ("bfin_pint@1", 1, "bfin_gpio2@1"),
   SIC (0, 21, "bfin_dma@256",      "di"),       /* mdma0 */
   SIC (0, 21, "bfin_dma@257",      "di"),       /* mdma0 */
   SIC (0, 22, "bfin_dma@258",      "di"),       /* mdma1 */
   SIC (0, 22, "bfin_dma@259",      "di"),       /* mdma1 */
   SIC (0, 23, "bfin_wdog@0",       "gpi"),
   SIC (0, 24, "bfin_dmac@1",       "stat"),
   SIC (0, 25, "bfin_sport@2",      "stat"),
   SIC (0, 26, "bfin_sport@3",      "stat"),
   SIC (0, 27, "bfin_mxvr",         "data"),
   SIC (0, 28, "bfin_spi@1",        "stat"),
@@ skipping 61 matching lines @@
 /*SIC (2, 21, reserved),*/
   SIC (2, 22, "bfin_gptimer@0",    "stat"),
   SIC (2, 23, "bfin_gptimer@1",    "stat"),
   SIC (2, 24, "bfin_gptimer@2",    "stat"),
   SIC (2, 25, "bfin_gptimer@3",    "stat"),
   SIC (2, 26, "bfin_gptimer@4",    "stat"),
   SIC (2, 27, "bfin_gptimer@5",    "stat"),
   SIC (2, 28, "bfin_gptimer@6",    "stat"),
   SIC (2, 29, "bfin_gptimer@7",    "stat"),
   SIC (2, 30, "bfin_pint@2",       "stat"),
+  PINT_PIQS ("bfin_pint@2", 0, "bfin_gpio2@2"),
+  PINT_PIQS ("bfin_pint@2", 1, "bfin_gpio2@3"),
+  PINT_PIQS ("bfin_pint@2", 2, "bfin_gpio2@4"),
+  PINT_PIQS ("bfin_pint@2", 3, "bfin_gpio2@5"),
+  PINT_PIQS ("bfin_pint@2", 4, "bfin_gpio2@6"),
+  PINT_PIQS ("bfin_pint@2", 5, "bfin_gpio2@7"),
+  PINT_PIQS ("bfin_pint@2", 6, "bfin_gpio2@8"),
+  PINT_PIQS ("bfin_pint@2", 7, "bfin_gpio2@9"),
   SIC (2, 31, "bfin_pint@3",       "stat"),
+  PINT_PIQS ("bfin_pint@3", 0, "bfin_gpio2@2"),
+  PINT_PIQS ("bfin_pint@3", 1, "bfin_gpio2@3"),
+  PINT_PIQS ("bfin_pint@3", 2, "bfin_gpio2@4"),
+  PINT_PIQS ("bfin_pint@3", 3, "bfin_gpio2@5"),
+  PINT_PIQS ("bfin_pint@3", 4, "bfin_gpio2@6"),
+  PINT_PIQS ("bfin_pint@3", 5, "bfin_gpio2@7"),
+  PINT_PIQS ("bfin_pint@3", 6, "bfin_gpio2@8"),
+  PINT_PIQS ("bfin_pint@3", 7, "bfin_gpio2@9"),
 };
 #define bf542_port bf54x_port
 #define bf544_port bf54x_port
 #define bf547_port bf54x_port
 #define bf548_port bf54x_port
 #define bf549_port bf54x_port
 
 /* This is only Core A of course ...  */
 #define bf561_chipid 0x27bb
 static const struct bfin_memory_layout bf561_mem[] =
@@ skipping 411 matching lines @@
   BFROM (538, 5, 0x1000000),
   BFROM (538, 4, 0x1000000),
   BFROM (538, 3, 0x1000000),
   BFROM (538, 2, 0x1000000),
   BFROM (538, 1, 0x1000000),
   BFROM (538, 0, 0x1000000),
   BFROM_STUB,
 };
 static const struct bfrom bf54x_roms[] =
 {
-  BFROM (54x, 4, 0),
-  BFROM (54x, 2, 0),
-  BFROM (54x, 1, 0),
-  BFROM (54x, 0, 0),
-  BFROMA (0xffa14000, 54x_l1, 4, 0),
-  BFROMA (0xffa14000, 54x_l1, 2, 0),
-  BFROMA (0xffa14000, 54x_l1, 1, 0),
-  BFROMA (0xffa14000, 54x_l1, 0, 0),
+  BFROM (54x, 4, 0x1000),
+  BFROM (54x, 2, 0x1000),
+  BFROM (54x, 1, 0x1000),
+  BFROM (54x, 0, 0x1000),
+  BFROMA (0xffa14000, 54x_l1, 4, 0x10000),
+  BFROMA (0xffa14000, 54x_l1, 2, 0x10000),
+  BFROMA (0xffa14000, 54x_l1, 1, 0x10000),
+  BFROMA (0xffa14000, 54x_l1, 0, 0x10000),
   BFROM_STUB,
 };
 static const struct bfrom bf561_roms[] =
 {
   /* XXX: No idea what the actual wrap limit is here.  */
-  BFROM (561, 5, 0),
+  BFROM (561, 5, 0x1000),
   BFROM_STUB,
 };
 static const struct bfrom bf59x_roms[] =
 {
   BFROM (59x, 1, 0x1000000),
   BFROM (59x, 0, 0x1000000),
-  BFROMA (0xffa10000, 59x_l1, 1, 0),
+  BFROMA (0xffa10000, 59x_l1, 1, 0x10000),
   BFROM_STUB,
 };
 
 static void
 bfin_model_map_bfrom (SIM_DESC sd, SIM_CPU *cpu)
 {
   const struct bfin_model_data *mdata = CPU_MODEL_DATA (cpu);
   const struct bfin_board_data *board = STATE_BOARD_DATA (sd);
   int mnum = mdata->model_num;
   const struct bfrom *bfrom;
   unsigned int sirev;
 
   if (mnum >= 500 && mnum <= 509)
     bfrom = bf50x_roms;
   else if (mnum >= 510 && mnum <= 519)
     bfrom = bf51x_roms;
   else if (mnum >= 520 && mnum <= 529)
     bfrom = (mnum & 1) ? bf527_roms : bf526_roms;
   else if (mnum >= 531 && mnum <= 533)
     bfrom = bf533_roms;
   else if (mnum == 535)
-    /* Stub.  */;
+    return; /* Stub.  */
   else if (mnum >= 534 && mnum <= 537)
     bfrom = bf537_roms;
   else if (mnum >= 538 && mnum <= 539)
     bfrom = bf538_roms;
   else if (mnum >= 540 && mnum <= 549)
     bfrom = bf54x_roms;
   else if (mnum == 561)
     bfrom = bf561_roms;
   else if (mnum >= 590 && mnum <= 599)
     bfrom = bf59x_roms;
@@ skipping 177 matching lines @@
   bu32 value, *reg;
 
   reg = bfin_get_reg (cpu, rn);
   if (reg)
     value = *reg;
   else if (rn == SIM_BFIN_ASTAT_REGNUM)
     value = ASTAT;
   else if (rn == SIM_BFIN_CC_REGNUM)
     value = CCREG;
   else
-    return 0; // will be an error in gdb
+    return -1;
 
   /* Handle our KSP/USP shadowing in SP.  While in supervisor mode, we
      have the normal SP/USP behavior.  User mode is tricky though.  */
   if (STATE_ENVIRONMENT (CPU_STATE (cpu)) == OPERATING_ENVIRONMENT
       && cec_is_user_mode (cpu))
     {
       if (rn == SIM_BFIN_SP_REGNUM)
         value = KSPREG;
       else if (rn == SIM_BFIN_USP_REGNUM)
         value = SPREG;
     }
 
   bfin_store_unsigned_integer (buf, 4, value);
 
-  return -1; // disables size checking in gdb
+  return 4;
 }
 
 static int
 bfin_reg_store (SIM_CPU *cpu, int rn, unsigned char *buf, int len)
 {
   bu32 value, *reg;
 
   value = bfin_extract_unsigned_integer (buf, 4);
   reg = bfin_get_reg (cpu, rn);
 
   if (reg)
     /* XXX: Need register trace ?  */
     *reg = value;
   else if (rn == SIM_BFIN_ASTAT_REGNUM)
     SET_ASTAT (value);
   else if (rn == SIM_BFIN_CC_REGNUM)
     SET_CCREG (value);
   else
-    return 0; // will be an error in gdb
+    return -1;
 
-  return -1; // disables size checking in gdb
+  return 4;
 }
 
 static sim_cia
 bfin_pc_get (SIM_CPU *cpu)
 {
   return PCREG;
 }
 
 static void
 bfin_pc_set (SIM_CPU *cpu, sim_cia newpc)
@@ skipping 102 matching lines @@
 
     case OPTION_MACH_HW_BOARD_FILE:
       board->hw_file = xstrdup (arg);
       return SIM_RC_OK;
 
     default:
       sim_io_eprintf (sd, "Unknown Blackfin option %d\n", opt);
       return SIM_RC_FAIL;
     }
 }