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Side by Side Diff: sim/bfin/dv-bfin_sic.c

Issue 11969036: Merge GDB 7.5.1 (Closed) Base URL: http://git.chromium.org/native_client/nacl-gdb.git@master
Patch Set: Created 7 years, 11 months ago
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1 /* Blackfin System Interrupt Controller (SIC) model. 1 /* Blackfin System Interrupt Controller (SIC) model.
2 2
3 Copyright (C) 2010-2012 Free Software Foundation, Inc. 3 Copyright (C) 2010-2012 Free Software Foundation, Inc.
4 Contributed by Analog Devices, Inc. 4 Contributed by Analog Devices, Inc.
5 5
6 This file is part of simulators. 6 This file is part of simulators.
7 7
8 This program is free software; you can redistribute it and/or modify 8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by 9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the License, or 10 the Free Software Foundation; either version 3 of the License, or
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919 case 540 ... 549: 919 case 540 ... 549:
920 set_hw_io_read_buffer (me, bfin_sic_54x_io_read_buffer); 920 set_hw_io_read_buffer (me, bfin_sic_54x_io_read_buffer);
921 set_hw_io_write_buffer (me, bfin_sic_54x_io_write_buffer); 921 set_hw_io_write_buffer (me, bfin_sic_54x_io_write_buffer);
922 set_hw_ports (me, bfin_sic3_ports); 922 set_hw_ports (me, bfin_sic3_ports);
923 set_hw_port_event (me, bfin_sic_54x_port_event); 923 set_hw_port_event (me, bfin_sic_54x_port_event);
924 mmr_names = bf54x_mmr_names; 924 mmr_names = bf54x_mmr_names;
925 925
926 /* Initialize the SIC. */ 926 /* Initialize the SIC. */
927 sic->bf54x.imask0 = sic->bf54x.imask1 = sic->bf54x.imask2 = 0; 927 sic->bf54x.imask0 = sic->bf54x.imask1 = sic->bf54x.imask2 = 0;
928 sic->bf54x.isr0 = sic->bf54x.isr1 = sic->bf54x.isr2 = 0; 928 sic->bf54x.isr0 = sic->bf54x.isr1 = sic->bf54x.isr2 = 0;
929 sic->bf54x.iwr0 = sic->bf54x.iwr1 = sic->bf54x.iwr1 = 0xFFFFFFFF; 929 sic->bf54x.iwr0 = sic->bf54x.iwr1 = sic->bf54x.iwr2 = 0xFFFFFFFF;
930 sic->bf54x.iar0 = 0x10000000; 930 sic->bf54x.iar0 = 0x10000000;
931 sic->bf54x.iar1 = 0x33322221; 931 sic->bf54x.iar1 = 0x33322221;
932 sic->bf54x.iar2 = 0x66655444; 932 sic->bf54x.iar2 = 0x66655444;
933 sic->bf54x.iar3 = 0x00000000; 933 sic->bf54x.iar3 = 0x00000000;
934 sic->bf54x.iar4 = 0x32222220; 934 sic->bf54x.iar4 = 0x32222220;
935 sic->bf54x.iar5 = 0x44433333; 935 sic->bf54x.iar5 = 0x44433333;
936 sic->bf54x.iar6 = 0x00444664; 936 sic->bf54x.iar6 = 0x00444664;
937 sic->bf54x.iar7 = 0x00000000; 937 sic->bf54x.iar7 = 0x00000000;
938 sic->bf54x.iar8 = 0x44111111; 938 sic->bf54x.iar8 = 0x44111111;
939 sic->bf54x.iar9 = 0x44444444; 939 sic->bf54x.iar9 = 0x44444444;
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979 default: 979 default:
980 hw_abort (me, "no support for SIC on this Blackfin model yet"); 980 hw_abort (me, "no support for SIC on this Blackfin model yet");
981 } 981 }
982 } 982 }
983 983
984 const struct hw_descriptor dv_bfin_sic_descriptor[] = 984 const struct hw_descriptor dv_bfin_sic_descriptor[] =
985 { 985 {
986 {"bfin_sic", bfin_sic_finish,}, 986 {"bfin_sic", bfin_sic_finish,},
987 {NULL, NULL}, 987 {NULL, NULL},
988 }; 988 };
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