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| 1 /* Blackfin General Purpose Ports (GPIO) model |
| 2 For "new style" GPIOs on BF54x parts. |
| 3 |
| 4 Copyright (C) 2010-2012 Free Software Foundation, Inc. |
| 5 Contributed by Analog Devices, Inc. and Mike Frysinger. |
| 6 |
| 7 This file is part of simulators. |
| 8 |
| 9 This program is free software; you can redistribute it and/or modify |
| 10 it under the terms of the GNU General Public License as published by |
| 11 the Free Software Foundation; either version 3 of the License, or |
| 12 (at your option) any later version. |
| 13 |
| 14 This program is distributed in the hope that it will be useful, |
| 15 but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 17 GNU General Public License for more details. |
| 18 |
| 19 You should have received a copy of the GNU General Public License |
| 20 along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
| 21 |
| 22 #include "config.h" |
| 23 |
| 24 #include "sim-main.h" |
| 25 #include "devices.h" |
| 26 #include "dv-bfin_gpio2.h" |
| 27 |
| 28 struct bfin_gpio |
| 29 { |
| 30 bu32 base; |
| 31 |
| 32 /* Only accessed indirectly via dir_{set,clear}. */ |
| 33 bu16 dir; |
| 34 |
| 35 /* Make sure hardware MMRs are aligned. */ |
| 36 bu16 _pad; |
| 37 |
| 38 /* Order after here is important -- matches hardware MMR layout. */ |
| 39 bu16 BFIN_MMR_16(fer); |
| 40 bu16 BFIN_MMR_16(data); |
| 41 bu16 BFIN_MMR_16(set); |
| 42 bu16 BFIN_MMR_16(clear); |
| 43 bu16 BFIN_MMR_16(dir_set); |
| 44 bu16 BFIN_MMR_16(dir_clear); |
| 45 bu16 BFIN_MMR_16(inen); |
| 46 bu32 mux; |
| 47 }; |
| 48 #define mmr_base() offsetof(struct bfin_gpio, fer) |
| 49 #define mmr_offset(mmr) (offsetof(struct bfin_gpio, mmr) - mmr_base()) |
| 50 |
| 51 static const char * const mmr_names[] = |
| 52 { |
| 53 "PORTIO_FER", "PORTIO", "PORTIO_SET", "PORTIO_CLEAR", "PORTIO_DIR_SET", |
| 54 "PORTIO_DIR_CLEAR", "PORTIO_INEN", "PORTIO_MUX", |
| 55 }; |
| 56 #define mmr_name(off) mmr_names[(off) / 4] |
| 57 |
| 58 static unsigned |
| 59 bfin_gpio_io_write_buffer (struct hw *me, const void *source, int space, |
| 60 address_word addr, unsigned nr_bytes) |
| 61 { |
| 62 struct bfin_gpio *port = hw_data (me); |
| 63 bu32 mmr_off; |
| 64 bu32 value; |
| 65 bu16 *value16p; |
| 66 bu32 *value32p; |
| 67 void *valuep; |
| 68 |
| 69 if (nr_bytes == 4) |
| 70 value = dv_load_4 (source); |
| 71 else |
| 72 value = dv_load_2 (source); |
| 73 mmr_off = addr - port->base; |
| 74 valuep = (void *)((unsigned long)port + mmr_base() + mmr_off); |
| 75 value16p = valuep; |
| 76 value32p = valuep; |
| 77 |
| 78 HW_TRACE_WRITE (); |
| 79 |
| 80 if (mmr_off == mmr_offset (mux)) |
| 81 dv_bfin_mmr_require_32 (me, addr, nr_bytes, true); |
| 82 else |
| 83 dv_bfin_mmr_require_16 (me, addr, nr_bytes, true); |
| 84 |
| 85 switch (mmr_off) |
| 86 { |
| 87 case mmr_offset(fer): |
| 88 case mmr_offset(data): |
| 89 case mmr_offset(inen): |
| 90 *value16p = value; |
| 91 break; |
| 92 case mmr_offset(clear): |
| 93 /* We want to clear the related data MMR. */ |
| 94 dv_w1c_2 (&port->data, value, -1); |
| 95 break; |
| 96 case mmr_offset(set): |
| 97 /* We want to set the related data MMR. */ |
| 98 port->data |= value; |
| 99 break; |
| 100 case mmr_offset(dir_clear): |
| 101 dv_w1c_2 (&port->dir, value, -1); |
| 102 break; |
| 103 case mmr_offset(dir_set): |
| 104 port->dir |= value; |
| 105 break; |
| 106 case mmr_offset(mux): |
| 107 *value32p = value; |
| 108 break; |
| 109 default: |
| 110 dv_bfin_mmr_invalid (me, addr, nr_bytes, true); |
| 111 break; |
| 112 } |
| 113 |
| 114 /* If tweaking output pins, make sure we send updated port info. */ |
| 115 switch (mmr_off) |
| 116 { |
| 117 case mmr_offset(data): |
| 118 case mmr_offset(set): |
| 119 case mmr_offset(clear): |
| 120 case mmr_offset(dir_set): |
| 121 { |
| 122 int i; |
| 123 bu32 bit; |
| 124 |
| 125 for (i = 0; i < 16; ++i) |
| 126 { |
| 127 bit = (1 << i); |
| 128 |
| 129 if (!(port->inen & bit)) |
| 130 hw_port_event (me, i, !!(port->data & bit)); |
| 131 } |
| 132 |
| 133 break; |
| 134 } |
| 135 } |
| 136 |
| 137 return nr_bytes; |
| 138 } |
| 139 |
| 140 static unsigned |
| 141 bfin_gpio_io_read_buffer (struct hw *me, void *dest, int space, |
| 142 address_word addr, unsigned nr_bytes) |
| 143 { |
| 144 struct bfin_gpio *port = hw_data (me); |
| 145 bu32 mmr_off; |
| 146 bu16 *value16p; |
| 147 bu32 *value32p; |
| 148 void *valuep; |
| 149 |
| 150 mmr_off = addr - port->base; |
| 151 valuep = (void *)((unsigned long)port + mmr_base() + mmr_off); |
| 152 value16p = valuep; |
| 153 value32p = valuep; |
| 154 |
| 155 HW_TRACE_READ (); |
| 156 |
| 157 if (mmr_off == mmr_offset (mux)) |
| 158 dv_bfin_mmr_require_32 (me, addr, nr_bytes, false); |
| 159 else |
| 160 dv_bfin_mmr_require_16 (me, addr, nr_bytes, false); |
| 161 |
| 162 switch (mmr_off) |
| 163 { |
| 164 case mmr_offset(data): |
| 165 case mmr_offset(clear): |
| 166 case mmr_offset(set): |
| 167 dv_store_2 (dest, port->data); |
| 168 break; |
| 169 case mmr_offset(dir_clear): |
| 170 case mmr_offset(dir_set): |
| 171 dv_store_2 (dest, port->dir); |
| 172 break; |
| 173 case mmr_offset(fer): |
| 174 case mmr_offset(inen): |
| 175 dv_store_2 (dest, *value16p); |
| 176 break; |
| 177 case mmr_offset(mux): |
| 178 dv_store_4 (dest, *value32p); |
| 179 break; |
| 180 default: |
| 181 dv_bfin_mmr_invalid (me, addr, nr_bytes, false); |
| 182 break; |
| 183 } |
| 184 |
| 185 return nr_bytes; |
| 186 } |
| 187 |
| 188 static const struct hw_port_descriptor bfin_gpio_ports[] = |
| 189 { |
| 190 { "p0", 0, 0, bidirect_port, }, |
| 191 { "p1", 1, 0, bidirect_port, }, |
| 192 { "p2", 2, 0, bidirect_port, }, |
| 193 { "p3", 3, 0, bidirect_port, }, |
| 194 { "p4", 4, 0, bidirect_port, }, |
| 195 { "p5", 5, 0, bidirect_port, }, |
| 196 { "p6", 6, 0, bidirect_port, }, |
| 197 { "p7", 7, 0, bidirect_port, }, |
| 198 { "p8", 8, 0, bidirect_port, }, |
| 199 { "p9", 9, 0, bidirect_port, }, |
| 200 { "p10", 10, 0, bidirect_port, }, |
| 201 { "p11", 11, 0, bidirect_port, }, |
| 202 { "p12", 12, 0, bidirect_port, }, |
| 203 { "p13", 13, 0, bidirect_port, }, |
| 204 { "p14", 14, 0, bidirect_port, }, |
| 205 { "p15", 15, 0, bidirect_port, }, |
| 206 { NULL, 0, 0, 0, }, |
| 207 }; |
| 208 |
| 209 static void |
| 210 bfin_gpio_port_event (struct hw *me, int my_port, struct hw *source, |
| 211 int source_port, int level) |
| 212 { |
| 213 struct bfin_gpio *port = hw_data (me); |
| 214 bu32 bit = (1 << my_port); |
| 215 |
| 216 /* Normalize the level value. A simulated device can send any value |
| 217 it likes to us, but in reality we only care about 0 and 1. This |
| 218 lets us assume only those two values below. */ |
| 219 level = !!level; |
| 220 |
| 221 HW_TRACE ((me, "pin %i set to %i", my_port, level)); |
| 222 |
| 223 /* Only screw with state if this pin is set as an input, and the |
| 224 input is actually enabled, and it isn't in peripheral mode. */ |
| 225 if ((port->dir & bit) || !(port->inen & bit) || !(port->fer & bit)) |
| 226 { |
| 227 HW_TRACE ((me, "ignoring level due to DIR=%i INEN=%i FER=%i", |
| 228 !!(port->dir & bit), !!(port->inen & bit), |
| 229 !!(port->fer & bit))); |
| 230 return; |
| 231 } |
| 232 |
| 233 hw_port_event (me, my_port, level); |
| 234 } |
| 235 |
| 236 static void |
| 237 attach_bfin_gpio_regs (struct hw *me, struct bfin_gpio *port) |
| 238 { |
| 239 address_word attach_address; |
| 240 int attach_space; |
| 241 unsigned attach_size; |
| 242 reg_property_spec reg; |
| 243 |
| 244 if (hw_find_property (me, "reg") == NULL) |
| 245 hw_abort (me, "Missing \"reg\" property"); |
| 246 |
| 247 if (!hw_find_reg_array_property (me, "reg", 0, ®)) |
| 248 hw_abort (me, "\"reg\" property must contain three addr/size entries"); |
| 249 |
| 250 hw_unit_address_to_attach_address (hw_parent (me), |
| 251 ®.address, |
| 252 &attach_space, &attach_address, me); |
| 253 hw_unit_size_to_attach_size (hw_parent (me), ®.size, &attach_size, me); |
| 254 |
| 255 if (attach_size != BFIN_MMR_GPIO2_SIZE) |
| 256 hw_abort (me, "\"reg\" size must be %#x", BFIN_MMR_GPIO2_SIZE); |
| 257 |
| 258 hw_attach_address (hw_parent (me), |
| 259 0, attach_space, attach_address, attach_size, me); |
| 260 |
| 261 port->base = attach_address; |
| 262 } |
| 263 |
| 264 static void |
| 265 bfin_gpio_finish (struct hw *me) |
| 266 { |
| 267 struct bfin_gpio *port; |
| 268 |
| 269 port = HW_ZALLOC (me, struct bfin_gpio); |
| 270 |
| 271 set_hw_data (me, port); |
| 272 set_hw_io_read_buffer (me, bfin_gpio_io_read_buffer); |
| 273 set_hw_io_write_buffer (me, bfin_gpio_io_write_buffer); |
| 274 set_hw_ports (me, bfin_gpio_ports); |
| 275 set_hw_port_event (me, bfin_gpio_port_event); |
| 276 |
| 277 attach_bfin_gpio_regs (me, port); |
| 278 } |
| 279 |
| 280 const struct hw_descriptor dv_bfin_gpio2_descriptor[] = |
| 281 { |
| 282 {"bfin_gpio2", bfin_gpio_finish,}, |
| 283 {NULL, NULL}, |
| 284 }; |
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