Merge GDB 7.5.1

sim/bfin/bfin-sim.h

 /* Simulator for Analog Devices Blackfin processors.
 
    Copyright (C) 2005-2012 Free Software Foundation, Inc.
    Contributed by Analog Devices, Inc.
 
    This file is part of simulators.
 
    This program is free software; you can redistribute it and/or modify
    it under the terms of the GNU General Public License as published by
    the Free Software Foundation; either version 3 of the License, or
@@ skipping 26 matching lines @@
 
 /* For dealing with parallel instructions, we must avoid changing our register
    file until all parallel insns have been simulated.  This queue of stores
    can be used to delay a modification.
    XXX: Should go and convert all 32 bit insns to use this.  */
 struct store {
   bu32 *addr;
   bu32 val;
 };
 
+enum bfin_parallel_group {
+  BFIN_PARALLEL_NONE,
+  BFIN_PARALLEL_GROUP0, /* 32bit slot.  */
+  BFIN_PARALLEL_GROUP1, /* 16bit group1.  */
+  BFIN_PARALLEL_GROUP2, /* 16bit group2.  */
+};
+
 /* The KSP/USP handling wrt SP may not follow the hardware exactly (the hw
    looks at current mode and uses either SP or USP based on that.  We instead
    always operate on SP and mirror things in KSP and USP.  During a CEC
    transition, we take care of syncing the values.  This lowers the simulation
    complexity and speeds things up a bit.  */
 struct bfin_cpu_state
 {
   bu32 dpregs[16], iregs[4], mregs[4], bregs[4], lregs[4], cycles[3];
   bu32 ax[2], aw[2];
   bu32 lt[2], lc[2], lb[2];
@@ skipping 14 matching lines @@
 
   /* Used by the CEC to figure out where to return to.  */
   bu32 insn_len;
 
   /* How many cycles did this insn take to complete ?  */
   bu32 cycle_delay;
 
   /* The pc currently being interpreted in parallel insns.  */
   bu32 multi_pc;
 
+  /* Some insns are valid in group1, and others in group2, so we
+     need to keep track of the exact slot we're processing.  */
+  enum bfin_parallel_group group;
+
   /* Needed for supporting the DISALGNEXCPT instruction */
   int dis_algn_expt;
 
   /* See notes above for struct store.  */
   struct store stores[20];
   int n_stores;
 
 #if (WITH_HW)
   /* Cache heavily used CPU-specific device pointers.  */
   void *cec_cache;
@@ skipping 28 matching lines @@
 #define SYSCFGREG       (BFIN_CPU_STATE.syscfg)
 #define RETSREG         (BFIN_CPU_STATE.rets)
 #define RETIREG         (BFIN_CPU_STATE.reti)
 #define RETXREG         (BFIN_CPU_STATE.retx)
 #define RETNREG         (BFIN_CPU_STATE.retn)
 #define RETEREG         (BFIN_CPU_STATE.rete)
 #define PCREG           (BFIN_CPU_STATE.pc)
 #define EMUDAT_INREG    (BFIN_CPU_STATE.emudat[0])
 #define EMUDAT_OUTREG   (BFIN_CPU_STATE.emudat[1])
 #define INSN_LEN        (BFIN_CPU_STATE.insn_len)
+#define PARALLEL_GROUP  (BFIN_CPU_STATE.group)
 #define CYCLE_DELAY     (BFIN_CPU_STATE.cycle_delay)
 #define DIS_ALGN_EXPT   (BFIN_CPU_STATE.dis_algn_expt)
 
 #define EXCAUSE_SHIFT           0
 #define EXCAUSE_MASK            (0x3f << EXCAUSE_SHIFT)
 #define EXCAUSE                 ((SEQSTATREG & EXCAUSE_MASK) >> EXCAUSE_SHIFT)
 #define HWERRCAUSE_SHIFT        14
 #define HWERRCAUSE_MASK         (0x1f << HWERRCAUSE_SHIFT)
 #define HWERRCAUSE              ((SEQSTATREG & HWERRCAUSE_MASK) >> HWERRCAUSE_SHIFT)
 
@@ skipping 202 matching lines @@
 #define BFIN_ASYNC_BASE           0x20000000
 #define BFIN_SYSTEM_MMR_BASE      0xFFC00000
 #define BFIN_CORE_MMR_BASE        0xFFE00000
 #define BFIN_L1_SRAM_SCRATCH      0xFFB00000
 #define BFIN_L1_SRAM_SCRATCH_SIZE 0x1000
 #define BFIN_L1_SRAM_SCRATCH_END  (BFIN_L1_SRAM_SCRATCH + BFIN_L1_SRAM_SCRATCH_SIZE)
 
 #define BFIN_L1_CACHE_BYTES       32
 
 #endif