Merge GDB 7.5.1

sim/bfin/bfin-sim.c

 /* Simulator for Analog Devices Blackfin processors.
 
    Copyright (C) 2005-2012 Free Software Foundation, Inc.
    Contributed by Analog Devices, Inc.
 
    This file is part of simulators.
 
    This program is free software; you can redistribute it and/or modify
    it under the terms of the GNU General Public License as published by
    the Free Software Foundation; either version 3 of the License, or
@@ skipping 34 matching lines @@
 
 static __attribute__ ((noreturn)) void
 illegal_instruction_combination (SIM_CPU *cpu)
 {
   TRACE_INSN (cpu, "ILLEGAL INSTRUCTION COMBINATION");
   while (1)
     cec_exception (cpu, VEC_ILGAL_I);
 }
 
 static __attribute__ ((noreturn)) void
+illegal_instruction_or_combination (SIM_CPU *cpu)
+{
+  if (PARALLEL_GROUP != BFIN_PARALLEL_NONE)
+    illegal_instruction_combination (cpu);
+  else
+    illegal_instruction (cpu);
+}
+
+static __attribute__ ((noreturn)) void
 unhandled_instruction (SIM_CPU *cpu, const char *insn)
 {
   SIM_DESC sd = CPU_STATE (cpu);
   bu16 iw0, iw1;
   bu32 iw2;
 
   TRACE_EVENTS (cpu, "unhandled instruction");
 
   iw0 = IFETCH (PCREG);
   iw1 = IFETCH (PCREG + 2);
@@ skipping 151 matching lines @@
   else
     x = constant_formats[cf].issigned ? SIGNEXTEND (x, constant_formats[cf].nbits) : x;
 
   if (constant_formats[cf].offset)
     x += constant_formats[cf].offset;
 
   if (constant_formats[cf].scale)
     x <<= constant_formats[cf].scale;
 
   if (constant_formats[cf].decimal)
-    {
-      if (constant_formats[cf].leading)
-        {
-          char ps[10];
-          sprintf (ps, "%%%ii", constant_formats[cf].leading);
-          sprintf (buf, ps, x);
-        }
-      else
-        sprintf (buf, "%i", x);
-    }
+    sprintf (buf, "%*i", constant_formats[cf].leading, x);
   else
     {
       if (constant_formats[cf].issigned && x < 0)
         sprintf (buf, "-0x%x", abs (x));
       else
         sprintf (buf, "0x%x", x);
     }
 
   return buf;
 }
@@ skipping 495 matching lines @@
       break;
     }
   SET_ASTATREG (an, val >> (size - 1));
   SET_ASTATREG (az, val == 0);
   if (size != 40)
     SET_ASTATREG (v, 0);
   return val;
 }
 
 static bu64
-lshift (SIM_CPU *cpu, bu64 val, int cnt, int size, bool saturate)
+lshift (SIM_CPU *cpu, bu64 val, int cnt, int size, bool saturate, bool overflow)
 {
-  int i, j, real_cnt = cnt > size ? size : cnt;
+  int v_i, real_cnt = cnt > size ? size : cnt;
   bu64 sgn = ~((val >> (size - 1)) - 1);
   int mask_cnt = size - 1;
-  bu64 masked, new_val = val, tmp;
+  bu64 masked, new_val = val;
   bu64 mask = ~0;
 
   mask <<= mask_cnt;
   sgn <<= mask_cnt;
   masked = val & mask;
 
   if (real_cnt > 16)
     new_val <<= 16, real_cnt -= 16;
 
   new_val <<= real_cnt;
 
   masked = new_val & mask;
 
   /* If an operation would otherwise cause a positive value to overflow
      and become negative, instead, saturation limits the result to the
      maximum positive value for the size register being used.
 
      Conversely, if an operation would otherwise cause a negative value
      to overflow and become positive, saturation limits the result to the
      maximum negative value for the register size.
 
      However, it's a little more complex than looking at sign bits, we need
      to see if we are shifting the sign information away...  */
-  tmp = val & ((~mask << 1) | 1);
-
-  j = 0;
-  for (i = 1; i <= real_cnt && saturate; i++)
-    {
-      if ((tmp & ((bu64)1 << (size - 1))) !=
-          (((val >> mask_cnt) & 0x1) << mask_cnt))
-        j++;
-      tmp <<= 1;
-    }
-  saturate &= (!sgn && (new_val & (1 << mask_cnt)))
-              || (sgn && !(new_val & (1 << mask_cnt)));
+  if (((val << cnt) >> size) == 0
+      || (((val << cnt) >> size) == ~(~0 << cnt)
+          && ((new_val >> (size - 1)) & 0x1)))
+    v_i = 0;
+  else
+    v_i = 1;
 
   switch (size)
     {
     case 16:
-      if (j || (saturate && (new_val & mask)))
-        new_val = sgn == 0 ? 0x7fff : 0x8000, saturate = 1;
       new_val &= 0xFFFF;
+      if (saturate && (v_i || ((val >> (size - 1)) != (new_val >> (size - 1)))))
+        {
+          new_val = (val >> (size - 1)) == 0 ? 0x7fff : 0x8000;
+          v_i = 1;
+        }
       break;
     case 32:
       new_val &= 0xFFFFFFFF;
       masked &= 0xFFFFFFFF;
-      if (j || (saturate && ((sgn != masked) || (!sgn && new_val == 0))))
-        new_val = sgn == 0 ? 0x7fffffff : 0x80000000, saturate = 1;
+      sgn &= 0xFFFFFFFF;
+      if (saturate
+          && (v_i
+              || (sgn != masked)
+              || (!sgn && new_val == 0 && val != 0)))
+        {
+          new_val = sgn == 0 ? 0x7fffffff : 0x80000000;
+          v_i = 1;
+        }
       break;
     case 40:
       new_val &= 0xFFFFFFFFFFull;
       masked &= 0xFFFFFFFFFFull;
       break;
     default:
       illegal_instruction (cpu);
       break;
     }
 
   SET_ASTATREG (an, new_val >> (size - 1));
   SET_ASTATREG (az, new_val == 0);
-  SET_ASTATREG (v, !!(saturate || j));
-  if (saturate || j)
-    SET_ASTATREG (vs, 1);
+  if (size != 40)
+    {
+      SET_ASTATREG (v, overflow && v_i);
+      if (overflow && v_i)
+        SET_ASTATREG (vs, 1);
+    }
+
   return new_val;
 }
 
 static bu32
 algn (bu32 l, bu32 h, bu32 aln)
 {
   if (aln == 0)
     return l;
   else
     return (l >> (8 * aln)) | (h << (32 - 8 * aln));
@@ skipping 926 matching lines @@
     {
       PROFILE_COUNT_INSN (cpu, pc, BFIN_INSN_ProgCtrl_nop);
       TRACE_INSN (cpu, "NOP;");
     }
   else if (prgfunc == 1 && poprnd == 0)
     {
       bu32 newpc = RETSREG;
       PROFILE_COUNT_INSN (cpu, pc, BFIN_INSN_ProgCtrl_branch);
       TRACE_INSN (cpu, "RTS;");
       IFETCH_CHECK (newpc);
-      if (INSN_LEN == 8)
+      if (PARALLEL_GROUP != BFIN_PARALLEL_NONE)
         illegal_instruction_combination (cpu);
       TRACE_BRANCH (cpu, pc, newpc, -1, "RTS");
       SET_PCREG (newpc);
       BFIN_CPU_STATE.did_jump = true;
       CYCLE_DELAY = 5;
     }
   else if (prgfunc == 1 && poprnd == 1)
     {
       PROFILE_COUNT_INSN (cpu, pc, BFIN_INSN_ProgCtrl_branch);
       TRACE_INSN (cpu, "RTI;");
       /* Do not do IFETCH_CHECK here -- LSB has special meaning.  */
-      if (INSN_LEN == 8)
+      if (PARALLEL_GROUP != BFIN_PARALLEL_NONE)
         illegal_instruction_combination (cpu);
       cec_return (cpu, -1);
       CYCLE_DELAY = 5;
     }
   else if (prgfunc == 1 && poprnd == 2)
     {
       bu32 newpc = RETXREG;
       PROFILE_COUNT_INSN (cpu, pc, BFIN_INSN_ProgCtrl_branch);
       TRACE_INSN (cpu, "RTX;");
       /* XXX: Not sure if this is what the hardware does.  */
       IFETCH_CHECK (newpc);
-      if (INSN_LEN == 8)
+      if (PARALLEL_GROUP != BFIN_PARALLEL_NONE)
         illegal_instruction_combination (cpu);
       cec_return (cpu, IVG_EVX);
       CYCLE_DELAY = 5;
     }
   else if (prgfunc == 1 && poprnd == 3)
     {
       bu32 newpc = RETNREG;
       PROFILE_COUNT_INSN (cpu, pc, BFIN_INSN_ProgCtrl_branch);
       TRACE_INSN (cpu, "RTN;");
       /* XXX: Not sure if this is what the hardware does.  */
       IFETCH_CHECK (newpc);
-      if (INSN_LEN == 8)
+      if (PARALLEL_GROUP != BFIN_PARALLEL_NONE)
         illegal_instruction_combination (cpu);
       cec_return (cpu, IVG_NMI);
       CYCLE_DELAY = 5;
     }
   else if (prgfunc == 1 && poprnd == 4)
     {
       PROFILE_COUNT_INSN (cpu, pc, BFIN_INSN_ProgCtrl_branch);
       TRACE_INSN (cpu, "RTE;");
-      if (INSN_LEN == 8)
+      if (PARALLEL_GROUP != BFIN_PARALLEL_NONE)
         illegal_instruction_combination (cpu);
       cec_return (cpu, IVG_EMU);
       CYCLE_DELAY = 5;
     }
   else if (prgfunc == 2 && poprnd == 0)
     {
       SIM_DESC sd = CPU_STATE (cpu);
       sim_events *events = STATE_EVENTS (sd);
 
       PROFILE_COUNT_INSN (cpu, pc, BFIN_INSN_ProgCtrl_sync);
       /* XXX: in supervisor mode, utilizes wake up sources
          in user mode, it's a NOP ...  */
       TRACE_INSN (cpu, "IDLE;");
 
-      if (INSN_LEN == 8)
+      if (PARALLEL_GROUP != BFIN_PARALLEL_NONE)
         illegal_instruction_combination (cpu);
 
       /* Timewarp !  */
       if (events->queue)
         CYCLE_DELAY = events->time_from_event;
       else
         abort (); /* XXX: Should this ever happen ?  */
     }
   else if (prgfunc == 2 && poprnd == 3)
     {
       PROFILE_COUNT_INSN (cpu, pc, BFIN_INSN_ProgCtrl_sync);
       /* Just NOP it.  */
       TRACE_INSN (cpu, "CSYNC;");
-      if (INSN_LEN == 8)
+      if (PARALLEL_GROUP != BFIN_PARALLEL_NONE)
         illegal_instruction_combination (cpu);
       CYCLE_DELAY = 10;
     }
   else if (prgfunc == 2 && poprnd == 4)
     {
       PROFILE_COUNT_INSN (cpu, pc, BFIN_INSN_ProgCtrl_sync);
       /* Just NOP it.  */
       TRACE_INSN (cpu, "SSYNC;");
-      if (INSN_LEN == 8)
+      if (PARALLEL_GROUP != BFIN_PARALLEL_NONE)
         illegal_instruction_combination (cpu);
 
       /* Really 10+, but no model info for this.  */
       CYCLE_DELAY = 10;
     }
   else if (prgfunc == 2 && poprnd == 5)
     {
       PROFILE_COUNT_INSN (cpu, pc, BFIN_INSN_ProgCtrl_cec);
       TRACE_INSN (cpu, "EMUEXCPT;");
-      if (INSN_LEN == 8)
+      if (PARALLEL_GROUP != BFIN_PARALLEL_NONE)
         illegal_instruction_combination (cpu);
       cec_exception (cpu, VEC_SIM_TRAP);
     }
   else if (prgfunc == 3 && poprnd < 8)
     {
       PROFILE_COUNT_INSN (cpu, pc, BFIN_INSN_ProgCtrl_cec);
       TRACE_INSN (cpu, "CLI R%i;", poprnd);
-      if (INSN_LEN == 8)
+      if (PARALLEL_GROUP != BFIN_PARALLEL_NONE)
         illegal_instruction_combination (cpu);
       SET_DREG (poprnd, cec_cli (cpu));
     }
   else if (prgfunc == 4 && poprnd < 8)
     {
       PROFILE_COUNT_INSN (cpu, pc, BFIN_INSN_ProgCtrl_cec);
       TRACE_INSN (cpu, "STI R%i;", poprnd);
-      if (INSN_LEN == 8)
+      if (PARALLEL_GROUP != BFIN_PARALLEL_NONE)
         illegal_instruction_combination (cpu);
       cec_sti (cpu, DREG (poprnd));
       CYCLE_DELAY = 3;
     }
   else if (prgfunc == 5 && poprnd < 8)
     {
       bu32 newpc = PREG (poprnd);
       PROFILE_COUNT_INSN (cpu, pc, BFIN_INSN_ProgCtrl_branch);
       TRACE_INSN (cpu, "JUMP (%s);", get_preg_name (poprnd));
       IFETCH_CHECK (newpc);
-      if (INSN_LEN == 8)
+      if (PARALLEL_GROUP != BFIN_PARALLEL_NONE)
         illegal_instruction_combination (cpu);
       TRACE_BRANCH (cpu, pc, newpc, -1, "JUMP (Preg)");
       SET_PCREG (newpc);
       BFIN_CPU_STATE.did_jump = true;
       PROFILE_BRANCH_TAKEN (cpu);
       CYCLE_DELAY = 5;
     }
   else if (prgfunc == 6 && poprnd < 8)
     {
       bu32 newpc = PREG (poprnd);
       PROFILE_COUNT_INSN (cpu, pc, BFIN_INSN_ProgCtrl_branch);
       TRACE_INSN (cpu, "CALL (%s);", get_preg_name (poprnd));
       IFETCH_CHECK (newpc);
-      if (INSN_LEN == 8)
+      if (PARALLEL_GROUP != BFIN_PARALLEL_NONE)
         illegal_instruction_combination (cpu);
       TRACE_BRANCH (cpu, pc, newpc, -1, "CALL (Preg)");
       /* If we're at the end of a hardware loop, RETS is going to be
          the top of the loop rather than the next instruction.  */
       SET_RETSREG (hwloop_get_next_pc (cpu, pc, 2));
       SET_PCREG (newpc);
       BFIN_CPU_STATE.did_jump = true;
       PROFILE_BRANCH_TAKEN (cpu);
       CYCLE_DELAY = 5;
     }
   else if (prgfunc == 7 && poprnd < 8)
     {
       bu32 newpc = pc + PREG (poprnd);
       PROFILE_COUNT_INSN (cpu, pc, BFIN_INSN_ProgCtrl_branch);
       TRACE_INSN (cpu, "CALL (PC + %s);", get_preg_name (poprnd));
       IFETCH_CHECK (newpc);
-      if (INSN_LEN == 8)
+      if (PARALLEL_GROUP != BFIN_PARALLEL_NONE)
         illegal_instruction_combination (cpu);
       TRACE_BRANCH (cpu, pc, newpc, -1, "CALL (PC + Preg)");
       SET_RETSREG (hwloop_get_next_pc (cpu, pc, 2));
       SET_PCREG (newpc);
       BFIN_CPU_STATE.did_jump = true;
       PROFILE_BRANCH_TAKEN (cpu);
       CYCLE_DELAY = 5;
     }
   else if (prgfunc == 8 && poprnd < 8)
     {
       bu32 newpc = pc + PREG (poprnd);
       PROFILE_COUNT_INSN (cpu, pc, BFIN_INSN_ProgCtrl_branch);
       TRACE_INSN (cpu, "JUMP (PC + %s);", get_preg_name (poprnd));
       IFETCH_CHECK (newpc);
-      if (INSN_LEN == 8)
+      if (PARALLEL_GROUP != BFIN_PARALLEL_NONE)
         illegal_instruction_combination (cpu);
       TRACE_BRANCH (cpu, pc, newpc, -1, "JUMP (PC + Preg)");
       SET_PCREG (newpc);
       BFIN_CPU_STATE.did_jump = true;
       PROFILE_BRANCH_TAKEN (cpu);
       CYCLE_DELAY = 5;
     }
   else if (prgfunc == 9)
     {
       int raise = uimm4 (poprnd);
       PROFILE_COUNT_INSN (cpu, pc, BFIN_INSN_ProgCtrl_cec);
       TRACE_INSN (cpu, "RAISE %s;", uimm4_str (raise));
-      if (INSN_LEN == 8)
+      if (PARALLEL_GROUP != BFIN_PARALLEL_NONE)
         illegal_instruction_combination (cpu);
       cec_require_supervisor (cpu);
       if (raise == IVG_IVHW)
         cec_hwerr (cpu, HWERR_RAISE_5);
       else
         cec_latch (cpu, raise);
       CYCLE_DELAY = 3; /* XXX: Only if IVG is unmasked.  */
     }
   else if (prgfunc == 10)
     {
       int excpt = uimm4 (poprnd);
       PROFILE_COUNT_INSN (cpu, pc, BFIN_INSN_ProgCtrl_cec);
       TRACE_INSN (cpu, "EXCPT %s;", uimm4_str (excpt));
-      if (INSN_LEN == 8)
+      if (PARALLEL_GROUP != BFIN_PARALLEL_NONE)
         illegal_instruction_combination (cpu);
       cec_exception (cpu, excpt);
       CYCLE_DELAY = 3;
     }
   else if (prgfunc == 11 && poprnd < 6)
     {
       bu32 addr = PREG (poprnd);
       bu8 byte;
       PROFILE_COUNT_INSN (cpu, pc, BFIN_INSN_ProgCtrl_atomic);
       TRACE_INSN (cpu, "TESTSET (%s);", get_preg_name (poprnd));
-      if (INSN_LEN == 8)
+      if (PARALLEL_GROUP != BFIN_PARALLEL_NONE)
         illegal_instruction_combination (cpu);
       byte = GET_WORD (addr);
       SET_CCREG (byte == 0);
       PUT_BYTE (addr, byte | 0x80);
       /* Also includes memory stalls, but we don't model that.  */
       CYCLE_DELAY = 2;
     }
   else
-    illegal_instruction (cpu);
+    illegal_instruction_or_combination (cpu);
 }
 
 static void
 decode_CaCTRL_0 (SIM_CPU *cpu, bu16 iw0)
 {
   /* CaCTRL
      +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
      | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 |.a.|.op....|.reg.......|
      +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
   int a   = ((iw0 >> CaCTRL_a_bits) & CaCTRL_a_mask);
   int op  = ((iw0 >> CaCTRL_op_bits) & CaCTRL_op_mask);
   int reg = ((iw0 >> CaCTRL_reg_bits) & CaCTRL_reg_mask);
   bu32 preg = PREG (reg);
   const char * const sinsn[] = { "PREFETCH", "FLUSHINV", "FLUSH", "IFLUSH", };
 
   PROFILE_COUNT_INSN (cpu, pc, BFIN_INSN_CaCTRL);
   TRACE_EXTRACT (cpu, "%s: a:%i op:%i reg:%i", __func__, a, op, reg);
   TRACE_INSN (cpu, "%s [%s%s];", sinsn[op], get_preg_name (reg), a ? "++" : "");
 
-  if (INSN_LEN == 8)
+  if (PARALLEL_GROUP != BFIN_PARALLEL_NONE)
     /* None of these can be part of a parallel instruction.  */
     illegal_instruction_combination (cpu);
 
   /* No cache simulation, so these are (mostly) all NOPs.
      XXX: The hardware takes care of masking to cache lines, but need
      to check behavior of the post increment.  Should we be aligning
      the value to the cache line before adding the cache line size, or
      do we just add the cache line size ?  */
   if (op == 0)
     {   /* PREFETCH  */
@@ skipping 29 matching lines @@
   const char *reg_name = get_allreg_name (grp, reg);
   bu32 value;
   bu32 sp = SPREG;
 
   PROFILE_COUNT_INSN (cpu, pc, BFIN_INSN_PushPopReg);
   TRACE_EXTRACT (cpu, "%s: W:%i grp:%i reg:%i", __func__, W, grp, reg);
   TRACE_DECODE (cpu, "%s: reg:%s", __func__, reg_name);
 
   /* Can't push/pop reserved registers  */
   if (reg_is_reserved (grp, reg))
-    illegal_instruction (cpu);
+    illegal_instruction_or_combination (cpu);
 
   if (W == 0)
     {
       /* Dreg and Preg are not supported by this instruction.  */
       if (grp == 0 || grp == 1)
-        illegal_instruction (cpu);
+        illegal_instruction_or_combination (cpu);
       TRACE_INSN (cpu, "%s = [SP++];", reg_name);
       /* Can't pop USP while in userspace.  */
-      if (INSN_LEN == 8 || (grp == 7 && reg == 0 && cec_is_user_mode(cpu)))
+      if (PARALLEL_GROUP != BFIN_PARALLEL_NONE
+          || (grp == 7 && reg == 0 && cec_is_user_mode(cpu)))
         illegal_instruction_combination (cpu);
       /* XXX: The valid register check is in reg_write(), so we might
               incorrectly do a GET_LONG() here ...  */
       value = GET_LONG (sp);
       reg_write (cpu, grp, reg, value);
       if (grp == 7 && reg == 3)
         cec_pop_reti (cpu);
 
       sp += 4;
     }
   else
     {
       TRACE_INSN (cpu, "[--SP] = %s;", reg_name);
-      if (INSN_LEN == 8)
+      if (PARALLEL_GROUP != BFIN_PARALLEL_NONE)
         illegal_instruction_combination (cpu);
 
       sp -= 4;
       value = reg_read (cpu, grp, reg);
       if (grp == 7 && reg == 3)
         cec_push_reti (cpu);
 
       PUT_LONG (sp, value);
     }
 
@@ skipping 14 matching lines @@
   int W  = ((iw0 >> PushPopMultiple_W_bits) & PushPopMultiple_W_mask);
   int dr = ((iw0 >> PushPopMultiple_dr_bits) & PushPopMultiple_dr_mask);
   int pr = ((iw0 >> PushPopMultiple_pr_bits) & PushPopMultiple_pr_mask);
   int i;
   bu32 sp = SPREG;
 
   PROFILE_COUNT_INSN (cpu, pc, BFIN_INSN_PushPopMultiple);
   TRACE_EXTRACT (cpu, "%s: d:%i p:%i W:%i dr:%i pr:%i",
                  __func__, d, p, W, dr, pr);
 
+  if (PARALLEL_GROUP != BFIN_PARALLEL_NONE)
+    illegal_instruction_combination (cpu);
+
   if ((d == 0 && p == 0) || (p && imm5 (pr) > 5)
       || (d && !p && pr) || (p && !d && dr))
     illegal_instruction (cpu);
 
   if (W == 1)
     {
       if (d && p)
         TRACE_INSN (cpu, "[--SP] = (R7:%i, P5:%i);", dr, pr);
       else if (d)
         TRACE_INSN (cpu, "[--SP] = (R7:%i);", dr);
@@ skipping 60 matching lines @@
   int dst = ((iw0 >> CCmv_dst_bits) & CCmv_dst_mask);
   int cond = T ? CCREG : ! CCREG;
 
   PROFILE_COUNT_INSN (cpu, pc, BFIN_INSN_ccMV);
   TRACE_EXTRACT (cpu, "%s: T:%i d:%i s:%i dst:%i src:%i",
                  __func__, T, d, s, dst, src);
 
   TRACE_INSN (cpu, "IF %sCC %s = %s;", T ? "" : "! ",
               get_allreg_name (d, dst),
               get_allreg_name (s, src));
-  if (INSN_LEN == 8)
+  if (PARALLEL_GROUP != BFIN_PARALLEL_NONE)
     illegal_instruction_combination (cpu);
 
   if (cond)
     reg_write (cpu, d, dst, reg_read (cpu, s, src));
 }
 
 static void
 decode_CCflag_0 (SIM_CPU *cpu, bu16 iw0)
 {
   /* CCflag
@@ skipping 10 matching lines @@
   TRACE_EXTRACT (cpu, "%s: I:%i opc:%i G:%i y:%i x:%i",
                  __func__, I, opc, G, y, x);
 
   if (opc > 4)
     {
       bs64 acc0 = get_extended_acc (cpu, 0);
       bs64 acc1 = get_extended_acc (cpu, 1);
       bs64 diff = acc0 - acc1;
 
       if (x != 0 || y != 0)
-        illegal_instruction (cpu);
+        illegal_instruction_or_combination (cpu);
 
       if (opc == 5 && I == 0 && G == 0)
         {
           TRACE_INSN (cpu, "CC = A0 == A1;");
-          if (INSN_LEN == 8)
+          if (PARALLEL_GROUP != BFIN_PARALLEL_NONE)
             illegal_instruction_combination (cpu);
           SET_CCREG (acc0 == acc1);
         }
       else if (opc == 6 && I == 0 && G == 0)
         {
           TRACE_INSN (cpu, "CC = A0 < A1");
-          if (INSN_LEN == 8)
+          if (PARALLEL_GROUP != BFIN_PARALLEL_NONE)
             illegal_instruction_combination (cpu);
           SET_CCREG (acc0 < acc1);
         }
       else if (opc == 7 && I == 0 && G == 0)
         {
           TRACE_INSN (cpu, "CC = A0 <= A1");
-          if (INSN_LEN == 8)
+          if (PARALLEL_GROUP != BFIN_PARALLEL_NONE)
             illegal_instruction_combination (cpu);
           SET_CCREG (acc0 <= acc1);
         }
       else
-        illegal_instruction (cpu);
+        illegal_instruction_or_combination (cpu);
 
       SET_ASTATREG (az, diff == 0);
       SET_ASTATREG (an, diff < 0);
       SET_ASTATREG (ac0, (bu40)acc1 <= (bu40)acc0);
     }
   else
     {
       int issigned = opc < 3;
       const char *sign = issigned ? "" : " (IU)";
       bu32 srcop = G ? PREG (x) : DREG (x);
@@ skipping 44 matching lines @@
       if (I)
         TRACE_INSN (cpu, "CC = %c%i %s %s%s;", s, x, op,
                     issigned ? imm3_str (y) : uimm3_str (y), sign);
       else
         {
           TRACE_DECODE (cpu, "%s %c%i:%x %c%i:%x", __func__,
                         s, x, srcop,  d, y, dstop);
           TRACE_INSN (cpu, "CC = %c%i %s %c%i%s;", s, x, op, d, y, sign);
         }
 
+      if (PARALLEL_GROUP != BFIN_PARALLEL_NONE)
+        illegal_instruction_combination (cpu);
+
       SET_CCREG (cc);
       /* Pointer compares only touch CC.  */
       if (!G)
         {
           SET_ASTATREG (az, az);
           SET_ASTATREG (an, an);
           SET_ASTATREG (ac0, ac0);
         }
     }
 }
 
 static void
 decode_CC2dreg_0 (SIM_CPU *cpu, bu16 iw0)
 {
   /* CC2dreg
      +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
      | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 |.op....|.reg.......|
      +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
   int op  = ((iw0 >> CC2dreg_op_bits) & CC2dreg_op_mask);
   int reg = ((iw0 >> CC2dreg_reg_bits) & CC2dreg_reg_mask);
 
   PROFILE_COUNT_INSN (cpu, pc, BFIN_INSN_CC2dreg);
   TRACE_EXTRACT (cpu, "%s: op:%i reg:%i", __func__, op, reg);
 
   if (op == 0)
     {
       TRACE_INSN (cpu, "R%i = CC;", reg);
-      if (INSN_LEN == 8)
+      if (PARALLEL_GROUP != BFIN_PARALLEL_NONE)
         illegal_instruction_combination (cpu);
       SET_DREG (reg, CCREG);
     }
   else if (op == 1)
     {
       TRACE_INSN (cpu, "CC = R%i;", reg);
-      if (INSN_LEN == 8)
+      if (PARALLEL_GROUP != BFIN_PARALLEL_NONE)
         illegal_instruction_combination (cpu);
       SET_CCREG (DREG (reg) != 0);
     }
   else if (op == 3 && reg == 0)
     {
       TRACE_INSN (cpu, "CC = !CC;");
-      if (INSN_LEN == 8)
+      if (PARALLEL_GROUP != BFIN_PARALLEL_NONE)
         illegal_instruction_combination (cpu);
       SET_CCREG (!CCREG);
     }
   else
-    illegal_instruction (cpu);
+    illegal_instruction_or_combination (cpu);
 }
 
 static void
 decode_CC2stat_0 (SIM_CPU *cpu, bu16 iw0)
 {
   /* CC2stat
      +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
      | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |.D.|.op....|.cbit..............|
      +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
   int D    = ((iw0 >> CC2stat_D_bits) & CC2stat_D_mask);
   int op   = ((iw0 >> CC2stat_op_bits) & CC2stat_op_mask);
   int cbit = ((iw0 >> CC2stat_cbit_bits) & CC2stat_cbit_mask);
   bu32 pval;
 
   const char * const op_names[] = { "", "|", "&", "^" } ;
 
   PROFILE_COUNT_INSN (cpu, pc, BFIN_INSN_CC2stat);
   TRACE_EXTRACT (cpu, "%s: D:%i op:%i cbit:%i", __func__, D, op, cbit);
 
   TRACE_INSN (cpu, "%s %s= %s;", D ? astat_names[cbit] : "CC",
               op_names[op], D ? "CC" : astat_names[cbit]);
 
+  if (PARALLEL_GROUP != BFIN_PARALLEL_NONE)
+    illegal_instruction_combination (cpu);
+
   /* CC = CC; is invalid.  */
   if (cbit == 5)
     illegal_instruction (cpu);
 
-  if (INSN_LEN == 8)
-    illegal_instruction_combination (cpu);
-
   pval = !!(ASTAT & (1 << cbit));
   if (D == 0)
     switch (op)
       {
       case 0: SET_CCREG (pval); break;
       case 1: SET_CCREG (CCREG | pval); break;
       case 2: SET_CCREG (CCREG & pval); break;
       case 3: SET_CCREG (CCREG ^ pval); break;
       }
   else
@@ skipping 23 matching lines @@
   int cond = T ? CCREG : ! CCREG;
   int pcrel = pcrel10 (offset);
 
   PROFILE_COUNT_INSN (cpu, pc, BFIN_INSN_BRCC);
   TRACE_EXTRACT (cpu, "%s: T:%i B:%i offset:%#x", __func__, T, B, offset);
   TRACE_DECODE (cpu, "%s: pcrel10:%#x", __func__, pcrel);
 
   TRACE_INSN (cpu, "IF %sCC JUMP %#x%s;", T ? "" : "! ",
               pcrel, B ? " (bp)" : "");
 
-  if (INSN_LEN == 8)
+  if (PARALLEL_GROUP != BFIN_PARALLEL_NONE)
     illegal_instruction_combination (cpu);
 
   if (cond)
     {
       bu32 newpc = pc + pcrel;
       TRACE_BRANCH (cpu, pc, newpc, -1, "Conditional JUMP");
       SET_PCREG (newpc);
       BFIN_CPU_STATE.did_jump = true;
       PROFILE_BRANCH_TAKEN (cpu);
       CYCLE_DELAY = B ? 5 : 9;
@@ skipping 15 matching lines @@
   int offset = ((iw0 >> UJump_offset_bits) & UJump_offset_mask);
   int pcrel = pcrel12 (offset);
   bu32 newpc = pc + pcrel;
 
   PROFILE_COUNT_INSN (cpu, pc, BFIN_INSN_UJUMP);
   TRACE_EXTRACT (cpu, "%s: offset:%#x", __func__, offset);
   TRACE_DECODE (cpu, "%s: pcrel12:%#x", __func__, pcrel);
 
   TRACE_INSN (cpu, "JUMP.S %#x;", pcrel);
 
-  if (INSN_LEN == 8)
+  if (PARALLEL_GROUP != BFIN_PARALLEL_NONE)
     illegal_instruction_combination (cpu);
 
   TRACE_BRANCH (cpu, pc, newpc, -1, "JUMP.S");
 
   SET_PCREG (newpc);
   BFIN_CPU_STATE.did_jump = true;
   PROFILE_BRANCH_TAKEN (cpu);
   CYCLE_DELAY = 5;
 }
 
@@ skipping 11 matching lines @@
   const char *srcreg_name = get_allreg_name (gs, src);
   const char *dstreg_name = get_allreg_name (gd, dst);
 
   PROFILE_COUNT_INSN (cpu, pc, BFIN_INSN_REGMV);
   TRACE_EXTRACT (cpu, "%s: gd:%i gs:%i dst:%i src:%i",
                  __func__, gd, gs, dst, src);
   TRACE_DECODE (cpu, "%s: dst:%s src:%s", __func__, dstreg_name, srcreg_name);
 
   TRACE_INSN (cpu, "%s = %s;", dstreg_name, srcreg_name);
 
+  if (PARALLEL_GROUP != BFIN_PARALLEL_NONE)
+    illegal_instruction_combination (cpu);
+
   /* Reserved slots cannot be a src/dst.  */
   if (reg_is_reserved (gs, src) || reg_is_reserved (gd, dst))
     goto invalid_move;
 
   /* Standard register moves.  */
   if ((gs < 2)                                          /* Dregs/Pregs src  */
       || (gd < 2)                                       /* Dregs/Pregs dst  */
       || (gs == 4 && src < 4)                           /* Accumulators src  */
       || (gd == 4 && dst < 4 && (gs < 4))               /* Accumulators dst  */
       || (gs == 7 && src == 7 && !(gd == 4 && dst < 4)) /* EMUDAT src  */
@@ skipping 28 matching lines @@
      +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
      | 0 | 1 | 0 | 0 | 0 | 0 |.opc...........|.src.......|.dst.......|
      +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
   int src = ((iw0 >> ALU2op_src_bits) & ALU2op_src_mask);
   int opc = ((iw0 >> ALU2op_opc_bits) & ALU2op_opc_mask);
   int dst = ((iw0 >> ALU2op_dst_bits) & ALU2op_dst_mask);
 
   PROFILE_COUNT_INSN (cpu, pc, BFIN_INSN_ALU2op);
   TRACE_EXTRACT (cpu, "%s: opc:%i src:%i dst:%i", __func__, opc, src, dst);
 
+  if (PARALLEL_GROUP != BFIN_PARALLEL_NONE)
+    illegal_instruction_combination (cpu);
+
   if (opc == 0)
     {
       TRACE_INSN (cpu, "R%i >>>= R%i;", dst, src);
       SET_DREG (dst, ashiftrt (cpu, DREG (dst), DREG (src), 32));
     }
   else if (opc == 1)
     {
       bu32 val;
       TRACE_INSN (cpu, "R%i >>= R%i;", dst, src);
       if (DREG (src) <= 0x1F)
         val = lshiftrt (cpu, DREG (dst), DREG (src), 32);
       else
         val = 0;
       SET_DREG (dst, val);
     }
   else if (opc == 2)
     {
       TRACE_INSN (cpu, "R%i <<= R%i;", dst, src);
-      SET_DREG (dst, lshift (cpu, DREG (dst), DREG (src), 32, 0));
+      SET_DREG (dst, lshift (cpu, DREG (dst), DREG (src), 32, 0, 0));
     }
   else if (opc == 3)
     {
       TRACE_INSN (cpu, "R%i *= R%i;", dst, src);
       SET_DREG (dst, DREG (dst) * DREG (src));
       CYCLE_DELAY = 3;
     }
   else if (opc == 4)
     {
       TRACE_INSN (cpu, "R%i = (R%i + R%i) << 1;", dst, dst, src);
@@ skipping 69 matching lines @@
      +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
   int src = ((iw0 >> PTR2op_src_bits) & PTR2op_dst_mask);
   int opc = ((iw0 >> PTR2op_opc_bits) & PTR2op_opc_mask);
   int dst = ((iw0 >> PTR2op_dst_bits) & PTR2op_dst_mask);
   const char *src_name = get_preg_name (src);
   const char *dst_name = get_preg_name (dst);
 
   PROFILE_COUNT_INSN (cpu, pc, BFIN_INSN_PTR2op);
   TRACE_EXTRACT (cpu, "%s: opc:%i src:%i dst:%i", __func__, opc, src, dst);
 
+  if (PARALLEL_GROUP != BFIN_PARALLEL_NONE)
+    illegal_instruction_combination (cpu);
+
   if (opc == 0)
     {
       TRACE_INSN (cpu, "%s -= %s", dst_name, src_name);
       SET_PREG (dst, PREG (dst) - PREG (src));
     }
   else if (opc == 1)
     {
       TRACE_INSN (cpu, "%s = %s << 2", dst_name, src_name);
       SET_PREG (dst, PREG (src) << 2);
     }
@@ skipping 39 matching lines @@
   int uimm = uimm5 (src);
   const char *uimm_str = uimm5_str (uimm);
 
   PROFILE_COUNT_INSN (cpu, pc, BFIN_INSN_LOGI2op);
   TRACE_EXTRACT (cpu, "%s: opc:%i src:%i dst:%i", __func__, opc, src, dst);
   TRACE_DECODE (cpu, "%s: uimm5:%#x", __func__, uimm);
 
   if (opc == 0)
     {
       TRACE_INSN (cpu, "CC = ! BITTST (R%i, %s);", dst, uimm_str);
-      if (INSN_LEN == 8)
+      if (PARALLEL_GROUP != BFIN_PARALLEL_NONE)
         illegal_instruction_combination (cpu);
       SET_CCREG ((~DREG (dst) >> uimm) & 1);
     }
   else if (opc == 1)
     {
       TRACE_INSN (cpu, "CC = BITTST (R%i, %s);", dst, uimm_str);
-      if (INSN_LEN == 8)
+      if (PARALLEL_GROUP != BFIN_PARALLEL_NONE)
         illegal_instruction_combination (cpu);
       SET_CCREG ((DREG (dst) >> uimm) & 1);
     }
   else if (opc == 2)
     {
       TRACE_INSN (cpu, "BITSET (R%i, %s);", dst, uimm_str);
-      if (INSN_LEN == 8)
+      if (PARALLEL_GROUP != BFIN_PARALLEL_NONE)
         illegal_instruction_combination (cpu);
       SET_DREG (dst, DREG (dst) | (1 << uimm));
       setflags_logical (cpu, DREG (dst));
     }
   else if (opc == 3)
     {
       TRACE_INSN (cpu, "BITTGL (R%i, %s);", dst, uimm_str);
-      if (INSN_LEN == 8)
+      if (PARALLEL_GROUP != BFIN_PARALLEL_NONE)
         illegal_instruction_combination (cpu);
       SET_DREG (dst, DREG (dst) ^ (1 << uimm));
       setflags_logical (cpu, DREG (dst));
     }
   else if (opc == 4)
     {
       TRACE_INSN (cpu, "BITCLR (R%i, %s);", dst, uimm_str);
-      if (INSN_LEN == 8)
+      if (PARALLEL_GROUP != BFIN_PARALLEL_NONE)
         illegal_instruction_combination (cpu);
       SET_DREG (dst, DREG (dst) & ~(1 << uimm));
       setflags_logical (cpu, DREG (dst));
     }
   else if (opc == 5)
     {
       TRACE_INSN (cpu, "R%i >>>= %s;", dst, uimm_str);
-      if (INSN_LEN == 8)
+      if (PARALLEL_GROUP != BFIN_PARALLEL_NONE)
         illegal_instruction_combination (cpu);
       SET_DREG (dst, ashiftrt (cpu, DREG (dst), uimm, 32));
     }
   else if (opc == 6)
     {
       TRACE_INSN (cpu, "R%i >>= %s;", dst, uimm_str);
-      if (INSN_LEN == 8)
+      if (PARALLEL_GROUP != BFIN_PARALLEL_NONE)
         illegal_instruction_combination (cpu);
       SET_DREG (dst, lshiftrt (cpu, DREG (dst), uimm, 32));
     }
   else if (opc == 7)
     {
       TRACE_INSN (cpu, "R%i <<= %s;", dst, uimm_str);
-      if (INSN_LEN == 8)
+      if (PARALLEL_GROUP != BFIN_PARALLEL_NONE)
         illegal_instruction_combination (cpu);
-      SET_DREG (dst, lshift (cpu, DREG (dst), uimm, 32, 0));
+      SET_DREG (dst, lshift (cpu, DREG (dst), uimm, 32, 0, 0));
     }
 }
 
 static void
 decode_COMP3op_0 (SIM_CPU *cpu, bu16 iw0)
 {
   /* COMP3op
      +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
      | 0 | 1 | 0 | 1 |.opc.......|.dst.......|.src1......|.src0......|
      +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
   int opc  = ((iw0 >> COMP3op_opc_bits) & COMP3op_opc_mask);
   int dst  = ((iw0 >> COMP3op_dst_bits) & COMP3op_dst_mask);
   int src0 = ((iw0 >> COMP3op_src0_bits) & COMP3op_src0_mask);
   int src1 = ((iw0 >> COMP3op_src1_bits) & COMP3op_src1_mask);
 
   PROFILE_COUNT_INSN (cpu, pc, BFIN_INSN_COMP3op);
   TRACE_EXTRACT (cpu, "%s: opc:%i dst:%i src1:%i src0:%i",
                  __func__, opc, dst, src1, src0);
 
+  if (PARALLEL_GROUP != BFIN_PARALLEL_NONE)
+    illegal_instruction_combination (cpu);
+
   if (opc == 0)
     {
       TRACE_INSN (cpu, "R%i = R%i + R%i;", dst, src0, src1);
       SET_DREG (dst, add32 (cpu, DREG (src0), DREG (src1), 1, 0));
     }
   else if (opc == 1)
     {
       TRACE_INSN (cpu, "R%i = R%i - R%i;", dst, src0, src1);
       SET_DREG (dst, sub32 (cpu, DREG (src0), DREG (src1), 1, 0, 0));
     }
@@ skipping 43 matching lines @@
      +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
   int op  = ((iw0 >> COMPI2opD_op_bits) & COMPI2opD_op_mask);
   int dst = ((iw0 >> COMPI2opD_dst_bits) & COMPI2opD_dst_mask);
   int src = ((iw0 >> COMPI2opD_src_bits) & COMPI2opD_src_mask);
   int imm = imm7 (src);
 
   PROFILE_COUNT_INSN (cpu, pc, BFIN_INSN_COMPI2opD);
   TRACE_EXTRACT (cpu, "%s: op:%i src:%i dst:%i", __func__, op, src, dst);
   TRACE_DECODE (cpu, "%s: imm7:%#x", __func__, imm);
 
+  if (PARALLEL_GROUP != BFIN_PARALLEL_NONE)
+    illegal_instruction_combination (cpu);
+
   if (op == 0)
     {
       TRACE_INSN (cpu, "R%i = %s (X);", dst, imm7_str (imm));
       SET_DREG (dst, imm);
     }
   else if (op == 1)
     {
       TRACE_INSN (cpu, "R%i += %s;", dst, imm7_str (imm));
       SET_DREG (dst, add32 (cpu, DREG (dst), imm, 1, 0));
     }
 }
 
 static void
 decode_COMPI2opP_0 (SIM_CPU *cpu, bu16 iw0)
 {
   /* COMPI2opP
      +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
      | 0 | 1 | 1 | 0 | 1 |.op|.src.......................|.dst.......|
      +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
   int op  = ((iw0 >> COMPI2opP_op_bits) & COMPI2opP_op_mask);
   int src = ((iw0 >> COMPI2opP_src_bits) & COMPI2opP_src_mask);
   int dst = ((iw0 >> COMPI2opP_dst_bits) & COMPI2opP_dst_mask);
   int imm = imm7 (src);
   const char *dst_name = get_preg_name (dst);
 
   PROFILE_COUNT_INSN (cpu, pc, BFIN_INSN_COMPI2opP);
   TRACE_EXTRACT (cpu, "%s: op:%i src:%i dst:%i", __func__, op, src, dst);
   TRACE_DECODE (cpu, "%s: imm:%#x", __func__, imm);
 
+  if (PARALLEL_GROUP != BFIN_PARALLEL_NONE)
+    illegal_instruction_combination (cpu);
+
   if (op == 0)
     {
       TRACE_INSN (cpu, "%s = %s;", dst_name, imm7_str (imm));
       SET_PREG (dst, imm);
     }
   else if (op == 1)
     {
       TRACE_INSN (cpu, "%s += %s;", dst_name, imm7_str (imm));
       SET_PREG (dst, PREG (dst) + imm);
     }
@@ skipping 12 matching lines @@
   int ptr = ((iw0 >> LDSTpmod_ptr_bits) & LDSTpmod_ptr_mask);
   int reg = ((iw0 >> LDSTpmod_reg_bits) & LDSTpmod_reg_mask);
   const char *ptr_name = get_preg_name (ptr);
   const char *idx_name = get_preg_name (idx);
   bu32 addr, val;
 
   PROFILE_COUNT_INSN (cpu, pc, BFIN_INSN_LDSTpmod);
   TRACE_EXTRACT (cpu, "%s: W:%i aop:%i reg:%i idx:%i ptr:%i",
                  __func__, W, aop, reg, idx, ptr);
 
+  if (PARALLEL_GROUP == BFIN_PARALLEL_GROUP2)
+    illegal_instruction_combination (cpu);
+
   if (aop == 1 && W == 0 && idx == ptr)
     {
       TRACE_INSN (cpu, "R%i.L = W[%s];", reg, ptr_name);
       addr = PREG (ptr);
       val = GET_WORD (addr);
       STORE (DREG (reg), (DREG (reg) & 0xFFFF0000) | val);
     }
   else if (aop == 2 && W == 0 && idx == ptr)
     {
       TRACE_INSN (cpu, "R%i.H = W[%s];", reg, ptr_name);
@@ skipping 76 matching lines @@
     }
   else if (aop == 2 && W == 1)
     {
       TRACE_INSN (cpu, "W[%s ++ %s] = R%i.H;", ptr_name, idx_name, reg);
       addr = PREG (ptr);
       PUT_WORD (addr, DREG (reg) >> 16);
       if (ptr != idx)
         STORE (PREG (ptr), addr + PREG (idx));
     }
   else
-    illegal_instruction (cpu);
+    illegal_instruction_or_combination (cpu);
 }
 
 static void
 decode_dagMODim_0 (SIM_CPU *cpu, bu16 iw0)
 {
   /* dagMODim
      +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
      | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 0 |.br| 1 | 1 |.op|.m.....|.i.....|
      +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
   int i  = ((iw0 >> DagMODim_i_bits) & DagMODim_i_mask);
   int m  = ((iw0 >> DagMODim_m_bits) & DagMODim_m_mask);
   int br = ((iw0 >> DagMODim_br_bits) & DagMODim_br_mask);
   int op = ((iw0 >> DagMODim_op_bits) & DagMODim_op_mask);
 
   PROFILE_COUNT_INSN (cpu, pc, BFIN_INSN_dagMODim);
   TRACE_EXTRACT (cpu, "%s: br:%i op:%i m:%i i:%i", __func__, br, op, m, i);
 
+  if (PARALLEL_GROUP == BFIN_PARALLEL_GROUP2)
+    illegal_instruction_combination (cpu);
+
   if (op == 0 && br == 1)
     {
       TRACE_INSN (cpu, "I%i += M%i (BREV);", i, m);
       SET_IREG (i, add_brev (IREG (i), MREG (m)));
     }
   else if (op == 0)
     {
       TRACE_INSN (cpu, "I%i += M%i;", i, m);
       dagadd (cpu, i, MREG (m));
     }
   else if (op == 1 && br == 0)
     {
       TRACE_INSN (cpu, "I%i -= M%i;", i, m);
       dagsub (cpu, i, MREG (m));
     }
   else
-    illegal_instruction (cpu);
+    illegal_instruction_or_combination (cpu);
 }
 
 static void
 decode_dagMODik_0 (SIM_CPU *cpu, bu16 iw0)
 {
   /* dagMODik
      +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
      | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 1 | 0 |.op....|.i.....|
      +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
   int i  = ((iw0 >> DagMODik_i_bits) & DagMODik_i_mask);
   int op = ((iw0 >> DagMODik_op_bits) & DagMODik_op_mask);
 
   PROFILE_COUNT_INSN (cpu, pc, BFIN_INSN_dagMODik);
   TRACE_EXTRACT (cpu, "%s: op:%i i:%i", __func__, op, i);
 
+  if (PARALLEL_GROUP == BFIN_PARALLEL_GROUP2)
+    illegal_instruction_combination (cpu);
+
   if (op == 0)
     {
       TRACE_INSN (cpu, "I%i += 2;", i);
       dagadd (cpu, i, 2);
     }
   else if (op == 1)
     {
       TRACE_INSN (cpu, "I%i -= 2;", i);
       dagsub (cpu, i, 2);
     }
   else if (op == 2)
     {
       TRACE_INSN (cpu, "I%i += 4;", i);
       dagadd (cpu, i, 4);
     }
   else if (op == 3)
     {
       TRACE_INSN (cpu, "I%i -= 4;", i);
       dagsub (cpu, i, 4);
     }
   else
-    illegal_instruction (cpu);
+    illegal_instruction_or_combination (cpu);
 }
 
 static void
 decode_dspLDST_0 (SIM_CPU *cpu, bu16 iw0)
 {
   /* dspLDST
      +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
      | 1 | 0 | 0 | 1 | 1 | 1 |.W.|.aop...|.m.....|.i.....|.reg.......|
      +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
   int i   = ((iw0 >> DspLDST_i_bits) & DspLDST_i_mask);
@@ skipping 142 matching lines @@
       STORE (DREG (reg), GET_LONG (addr));
     }
   else if (aop == 3 && W == 1)
     {
       TRACE_INSN (cpu, "[I%i ++ M%i] = R%i;", i, m, reg);
       addr = IREG (i);
       dagadd (cpu, i, MREG (m));
       PUT_LONG (addr, DREG (reg));
     }
   else
-    illegal_instruction (cpu);
+    illegal_instruction_or_combination (cpu);
 }
 
 static void
 decode_LDST_0 (SIM_CPU *cpu, bu16 iw0)
 {
   /* LDST
      +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
      | 1 | 0 | 0 | 1 |.sz....|.W.|.aop...|.Z.|.ptr.......|.reg.......|
      +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
   int Z   = ((iw0 >> LDST_Z_bits) & LDST_Z_mask);
   int W   = ((iw0 >> LDST_W_bits) & LDST_W_mask);
   int sz  = ((iw0 >> LDST_sz_bits) & LDST_sz_mask);
   int aop = ((iw0 >> LDST_aop_bits) & LDST_aop_mask);
   int reg = ((iw0 >> LDST_reg_bits) & LDST_reg_mask);
   int ptr = ((iw0 >> LDST_ptr_bits) & LDST_ptr_mask);
   const char * const posts[] = { "++", "--", "" };
   const char *post = posts[aop];
   const char *ptr_name = get_preg_name (ptr);
 
   PROFILE_COUNT_INSN (cpu, pc, BFIN_INSN_LDST);
   TRACE_EXTRACT (cpu, "%s: sz:%i W:%i aop:%i Z:%i ptr:%i reg:%i",
                  __func__, sz, W, aop, Z, ptr, reg);
 
-  if (aop == 3)
-    illegal_instruction (cpu);
+  if (aop == 3 || PARALLEL_GROUP == BFIN_PARALLEL_GROUP2)
+    illegal_instruction_or_combination (cpu);
 
   if (W == 0)
     {
       if (sz == 0 && Z == 0)
         {
           TRACE_INSN (cpu, "R%i = [%s%s];", reg, ptr_name, post);
           SET_DREG (reg, GET_LONG (PREG (ptr)));
         }
       else if (sz == 0 && Z == 1)
         {
@@ skipping 16 matching lines @@
         {
           TRACE_INSN (cpu, "R%i = B[%s%s] (Z);", reg, ptr_name, post);
           SET_DREG (reg, GET_BYTE (PREG (ptr)));
         }
       else if (sz == 2 && Z == 1)
         {
           TRACE_INSN (cpu, "R%i = B[%s%s] (X);", reg, ptr_name, post);
           SET_DREG (reg, (bs32) (bs8) GET_BYTE (PREG (ptr)));
         }
       else
-        illegal_instruction (cpu);
+        illegal_instruction_or_combination (cpu);
     }
   else
     {
       if (sz == 0 && Z == 0)
         {
           TRACE_INSN (cpu, "[%s%s] = R%i;", ptr_name, post, reg);
           PUT_LONG (PREG (ptr), DREG (reg));
         }
       else if (sz == 0 && Z == 1)
         {
           TRACE_INSN (cpu, "[%s%s] = %s;", ptr_name, post, get_preg_name (reg));
           PUT_LONG (PREG (ptr), PREG (reg));
         }
       else if (sz == 1 && Z == 0)
         {
           TRACE_INSN (cpu, "W[%s%s] = R%i;", ptr_name, post, reg);
           PUT_WORD (PREG (ptr), DREG (reg));
         }
       else if (sz == 2 && Z == 0)
         {
           TRACE_INSN (cpu, "B[%s%s] = R%i;", ptr_name, post, reg);
           PUT_BYTE (PREG (ptr), DREG (reg));
         }
       else
-        illegal_instruction (cpu);
+        illegal_instruction_or_combination (cpu);
     }
 
   if (aop == 0)
     SET_PREG (ptr, PREG (ptr) + (1 << (2 - sz)));
   if (aop == 1)
     SET_PREG (ptr, PREG (ptr) - (1 << (2 - sz)));
 }
 
 static void
 decode_LDSTiiFP_0 (SIM_CPU *cpu, bu16 iw0)
@@ skipping 11 matching lines @@
   bu32 imm = negimm5s4 (offset);
   bu32 ea = FPREG + imm;
   const char *imm_str = negimm5s4_str (offset);
   const char *reg_name = get_allreg_name (grp, reg);
 
   PROFILE_COUNT_INSN (cpu, pc, BFIN_INSN_LDSTiiFP);
   TRACE_EXTRACT (cpu, "%s: W:%i offset:%#x grp:%i reg:%i", __func__,
                  W, offset, grp, reg);
   TRACE_DECODE (cpu, "%s: negimm5s4:%#x", __func__, imm);
 
+  if (PARALLEL_GROUP == BFIN_PARALLEL_GROUP2)
+    illegal_instruction_or_combination (cpu);
+
   if (W == 0)
     {
       TRACE_INSN (cpu, "%s = [FP + %s];", reg_name, imm_str);
       reg_write (cpu, grp, reg, GET_LONG (ea));
     }
   else
     {
       TRACE_INSN (cpu, "[FP + %s] = %s;", imm_str, reg_name);
       PUT_LONG (ea, reg_read (cpu, grp, reg));
     }
@@ skipping 20 matching lines @@
                  __func__, W, op, offset, ptr, reg);
 
   if (op == 0 || op == 3)
     imm = uimm4s4 (offset), imm_str = uimm4s4_str (offset);
   else
     imm = uimm4s2 (offset), imm_str = uimm4s2_str (offset);
   ea = PREG (ptr) + imm;
 
   TRACE_DECODE (cpu, "%s: uimm4s4/uimm4s2:%#x", __func__, imm);
 
+  if (PARALLEL_GROUP == BFIN_PARALLEL_GROUP2)
+    illegal_instruction_combination (cpu);
+
   if (W == 1 && op == 2)
     illegal_instruction (cpu);
 
   if (W == 0)
     {
       if (op == 0)
         {
           TRACE_INSN (cpu, "R%i = [%s + %s];", reg, ptr_name, imm_str);
           SET_DREG (reg, GET_LONG (ea));
         }
@@ skipping 53 matching lines @@
 
   PROFILE_COUNT_INSN (cpu, pc, BFIN_INSN_LoopSetup);
   TRACE_EXTRACT (cpu, "%s: rop:%i c:%i soffset:%i reg:%i eoffset:%i",
                  __func__, rop, c, soffset, reg, eoffset);
   TRACE_DECODE (cpu, "%s: s_pcrel4:%#x e_lppcrel10:%#x",
                 __func__, spcrel, epcrel);
 
   if (reg > 7)
     illegal_instruction (cpu);
 
-  if (INSN_LEN == 8)
+  if (PARALLEL_GROUP != BFIN_PARALLEL_NONE)
     illegal_instruction_combination (cpu);
 
   if (rop == 0)
     {
       TRACE_INSN (cpu, "LSETUP (%#x, %#x) LC%i;", spcrel, epcrel, c);
     }
   else if (rop == 1 && reg <= 7)
     {
       TRACE_INSN (cpu, "LSETUP (%#x, %#x) LC%i = %s;",
                   spcrel, epcrel, c, get_preg_name (reg));
@@ skipping 27 matching lines @@
   int grp = ((iw0 >> (LDIMMhalf_grp_bits - 16)) & LDIMMhalf_grp_mask);
   int hword = ((iw1 >> LDIMMhalf_hword_bits) & LDIMMhalf_hword_mask);
   bu32 val;
   const char *val_str;
   const char *reg_name = get_allreg_name (grp, reg);
 
   PROFILE_COUNT_INSN (cpu, pc, BFIN_INSN_LDIMMhalf);
   TRACE_EXTRACT (cpu, "%s: Z:%i H:%i S:%i grp:%i reg:%i hword:%#x",
                  __func__, Z, H, S, grp, reg, hword);
 
-  if (INSN_LEN == 8)
+  if (PARALLEL_GROUP != BFIN_PARALLEL_NONE)
     illegal_instruction_combination (cpu);
 
   if (S == 1)
     val = imm16 (hword), val_str = imm16_str (hword);
   else
     val = luimm16 (hword), val_str = luimm16_str (hword);
 
   if (H == 0 && S == 1 && Z == 0)
     {
       TRACE_INSN (cpu, "%s = %s (X);", reg_name, val_str);
@@ skipping 31 matching lines @@
   int msw = ((iw0 >> 0) & 0xff);
   int pcrel = pcrel24 ((msw << 16) | lsw);
   bu32 newpc = pc + pcrel;
 
   PROFILE_COUNT_INSN (cpu, pc, BFIN_INSN_CALLa);
   TRACE_EXTRACT (cpu, "%s: S:%i msw:%#x lsw:%#x", __func__, S, msw, lsw);
   TRACE_DECODE (cpu, "%s: pcrel24:%#x", __func__, pcrel);
 
   TRACE_INSN (cpu, "%s %#x;", S ? "CALL" : "JUMP.L", pcrel);
 
-  if (INSN_LEN == 8)
+  if (PARALLEL_GROUP != BFIN_PARALLEL_NONE)
     illegal_instruction_combination (cpu);
 
   if (S == 1)
     {
       TRACE_BRANCH (cpu, pc, newpc, -1, "CALL");
       SET_RETSREG (hwloop_get_next_pc (cpu, pc, 4));
     }
   else
     TRACE_BRANCH (cpu, pc, newpc, -1, "JUMP.L");
 
@@ skipping 113 matching lines @@
   bu32 sp;
 
   PROFILE_COUNT_INSN (cpu, pc, BFIN_INSN_linkage);
   TRACE_EXTRACT (cpu, "%s: R:%i framesize:%#x", __func__, R, framesize);
 
   if (R == 0)
     {
       int size = uimm16s4 (framesize);
       sp = SPREG;
       TRACE_INSN (cpu, "LINK %s;", uimm16s4_str (framesize));
-      if (INSN_LEN == 8)
+      if (PARALLEL_GROUP != BFIN_PARALLEL_NONE)
         illegal_instruction_combination (cpu);
       sp -= 4;
       PUT_LONG (sp, RETSREG);
       sp -= 4;
       PUT_LONG (sp, FPREG);
       SET_FPREG (sp);
       sp -= size;
       CYCLE_DELAY = 3;
     }
   else
     {
       /* Restore SP from FP.  */
       sp = FPREG;
       TRACE_INSN (cpu, "UNLINK;");
-      if (INSN_LEN == 8)
+      if (PARALLEL_GROUP != BFIN_PARALLEL_NONE)
         illegal_instruction_combination (cpu);
       SET_FPREG (GET_LONG (sp));
       sp += 4;
       SET_RETSREG (GET_LONG (sp));
       sp += 4;
       CYCLE_DELAY = 2;
     }
 
   SET_SPREG (sp);
 }
@@ skipping 1230 matching lines @@
 
       SET_ASTATREG (v, v);
       if (v)
         SET_ASTATREG (vs, 1);
       setflags_nz (cpu, val);
     }
   else if (aop == 3 && aopcde == 7)
     {
       bu32 val = DREG (src0);
 
-      TRACE_INSN (cpu, "R%i = - R%i %s;", dst0, src0, amod1 (s, 0));
+      TRACE_INSN (cpu, "R%i = - R%i%s;", dst0, src0, amod1 (s, 0));
 
       if (s && val == 0x80000000)
         {
           val = 0x7fffffff;
           SET_ASTATREG (v, 1);
           SET_ASTATREG (vs, 1);
         }
       else if (val == 0x80000000)
         val = 0x80000000;
       else
@@ skipping 171 matching lines @@
       if ((HLs & 1) == 0)
         val = (bu16)(DREG (src1) & 0xFFFF);
       else
         val = (bu16)((DREG (src1) & 0xFFFF0000) >> 16);
 
       /* Positive shift magnitudes produce Logical Left shifts.
          Negative shift magnitudes produce Arithmetic Right shifts.  */
       if (shft <= 0)
         val = ashiftrt (cpu, val, -shft, 16);
       else
-        val = lshift (cpu, val, shft, 16, sop == 1);
+        {
+          int sgn = (val >> 15) & 0x1;
+
+          val = lshift (cpu, val, shft, 16, sop == 1, 1);
+          if (((val >> 15) & 0x1) != sgn)
+            {
+              SET_ASTATREG (v, 1);
+              SET_ASTATREG (vs, 1);
+            }
+        }
 
       if ((HLs & 2) == 0)
         STORE (DREG (dst0), REG_H_L (DREG (dst0), val));
       else
         STORE (DREG (dst0), REG_H_L (val << 16, DREG (dst0)));
     }
   else if (sop == 2 && sopcde == 0)
     {
       bs32 shft = (bs8)(DREG (src0) << 2) >> 2;
       bu16 val;
@@ skipping 31 matching lines @@
       TRACE_DECODE (cpu, "A%i:%#"PRIx64" shift:%i CC:%i", HLs, acc, shift, cc);
 
       acc = rot40 (acc, shift, &cc);
       SET_AREG (HLs, acc);
       if (shift)
         SET_CCREG (cc);
     }
   else if (sop == 0 && sopcde == 3 && (HLs == 0 || HLs == 1))
     {
       bs32 shft = (bs8)(DREG (src0) << 2) >> 2;
-      bu64 val = get_extended_acc (cpu, HLs);
+      bu64 acc = get_extended_acc (cpu, HLs);
+      bu64 val;
 
       HLs = !!HLs;
       TRACE_INSN (cpu, "A%i = ASHIFT A%i BY R%i.L;", HLs, HLs, src0);
-      TRACE_DECODE (cpu, "A%i:%#"PRIx64" shift:%i", HLs, val, shft);
+      TRACE_DECODE (cpu, "A%i:%#"PRIx64" shift:%i", HLs, acc, shft);
 
       if (shft <= 0)
-        val = ashiftrt (cpu, val, -shft, 40);
+        val = ashiftrt (cpu, acc, -shft, 40);
       else
-        val = lshift (cpu, val, shft, 40, 0);
+        val = lshift (cpu, acc, shft, 40, 0, 0);
 
       STORE (AXREG (HLs), (val >> 32) & 0xff);
       STORE (AWREG (HLs), (val & 0xffffffff));
-      STORE (ASTATREG (av[HLs]), val == 0);
-      if (val == 0)
-        STORE (ASTATREG (avs[HLs]), 1);
+      STORE (ASTATREG (av[HLs]), 0);
     }
   else if (sop == 1 && sopcde == 3 && (HLs == 0 || HLs == 1))
     {
       bs32 shft = (bs8)(DREG (src0) << 2) >> 2;
+      bu64 acc = get_unextended_acc (cpu, HLs);
       bu64 val;
 
       HLs = !!HLs;
       TRACE_INSN (cpu, "A%i = LSHIFT A%i BY R%i.L;", HLs, HLs, src0);
-      val = get_unextended_acc (cpu, HLs);
+      TRACE_DECODE (cpu, "A%i:%#"PRIx64" shift:%i", HLs, acc, shft);
 
       if (shft <= 0)
-        val = lshiftrt (cpu, val, -shft, 40);
+        val = lshiftrt (cpu, acc, -shft, 40);
       else
-        val = lshift (cpu, val, shft, 40, 0);
+        val = lshift (cpu, acc, shft, 40, 0, 0);
 
       STORE (AXREG (HLs), (val >> 32) & 0xff);
       STORE (AWREG (HLs), (val & 0xffffffff));
-      STORE (ASTATREG (av[HLs]), val == 0);
-      if (val == 0)
-        STORE (ASTATREG (avs[HLs]), 1);
+      STORE (ASTATREG (av[HLs]), 0);
     }
   else if ((sop == 0 || sop == 1) && sopcde == 1)
     {
       bs32 shft = (bs8)(DREG (src0) << 2) >> 2;
       bu16 val0, val1;
       bu32 astat;
 
       TRACE_INSN (cpu, "R%i = ASHIFT R%i BY R%i.L (V%s);",
                   dst0, src1, src0, sop == 1 ? ",S" : "");
 
       val0 = (bu16)DREG (src1) & 0xFFFF;
       val1 = (bu16)((DREG (src1) & 0xFFFF0000) >> 16);
 
       if (shft <= 0)
         {
           val0 = ashiftrt (cpu, val0, -shft, 16);
           astat = ASTAT;
           val1 = ashiftrt (cpu, val1, -shft, 16);
         }
       else
         {
-          val0 = lshift (cpu, val0, shft, 16, sop == 1);
+          int sgn0 = (val0 >> 15) & 0x1;
+          int sgn1 = (val1 >> 15) & 0x1;
+
+          val0 = lshift (cpu, val0, shft, 16, sop == 1, 1);
           astat = ASTAT;
-          val1 = lshift (cpu, val1, shft, 16, sop == 1);
+          val1 = lshift (cpu, val1, shft, 16, sop == 1, 1);
+
+          if ((sgn0 != ((val0 >> 15) & 0x1)) || (sgn1 != ((val1 >> 15) & 0x1)))
+            {
+              SET_ASTATREG (v, 1);
+              SET_ASTATREG (vs, 1);
+            }
         }
       SET_ASTAT (ASTAT | astat);
       STORE (DREG (dst0), (val1 << 16) | val0);
     }
   else if ((sop == 0 || sop == 1 || sop == 2) && sopcde == 2)
     {
       /* dregs = [LA]SHIFT dregs BY dregs_lo (opt_S)  */
       /* sop == 1 : opt_S  */
       bu32 v = DREG (src1);
       /* LSHIFT uses sign extended low 6 bits of dregs_lo.  */
       bs32 shft = (bs8)(DREG (src0) << 2) >> 2;
 
       TRACE_INSN (cpu, "R%i = %cSHIFT R%i BY R%i.L%s;", dst0,
                   shft && sop != 2 ? 'A' : 'L', src1, src0,
                   sop == 1 ? " (S)" : "");
 
       if (shft < 0)
         {
           if (sop == 2)
             STORE (DREG (dst0), lshiftrt (cpu, v, -shft, 32));
           else
             STORE (DREG (dst0), ashiftrt (cpu, v, -shft, 32));
         }
       else
-        STORE (DREG (dst0), lshift (cpu, v, shft, 32, sop == 1));
+        {
+          bu32 val = lshift (cpu, v, shft, 32, sop == 1, 1);
+
+          STORE (DREG (dst0), val);
+          if (((v >> 31) & 0x1) != ((val >> 31) & 0x1))
+            {
+              SET_ASTATREG (v, 1);
+              SET_ASTATREG (vs, 1);
+            }
+        }
     }
   else if (sop == 3 && sopcde == 2)
     {
       int shift = imm6 (DREG (src0) & 0xFFFF);
       bu32 src = DREG (src1);
       bu32 ret, cc = CCREG;
 
       TRACE_INSN (cpu, "R%i = ROT R%i BY R%i.L;", dst0, src1, src0);
       TRACE_DECODE (cpu, "R%i:%#x R%i:%#x shift:%i CC:%i",
                     dst0, DREG (dst0), src1, src, shift, cc);
@@ skipping 15 matching lines @@
       val1 = (bu16)((DREG (src1) & 0xFFFF0000) >> 16);
 
       if (shft <= 0)
         {
           val0 = lshiftrt (cpu, val0, -shft, 16);
           astat = ASTAT;
           val1 = lshiftrt (cpu, val1, -shft, 16);
         }
       else
         {
-          val0 = lshift (cpu, val0, shft, 16, 0);
+          val0 = lshift (cpu, val0, shft, 16, 0, 0);
           astat = ASTAT;
-          val1 = lshift (cpu, val1, shft, 16, 0);
+          val1 = lshift (cpu, val1, shft, 16, 0, 0);
         }
       SET_ASTAT (ASTAT | astat);
       STORE (DREG (dst0), (val1 << 16) | val0);
     }
   else if (sopcde == 4)
     {
       bu32 sv0 = DREG (src0);
       bu32 sv1 = DREG (src1);
       TRACE_INSN (cpu, "R%i = PACK (R%i.%c, R%i.%c);", dst0,
                   src1, sop & 2 ? 'H' : 'L',
@@ skipping 315 matching lines @@
   else if ((sop == 0 || sop == 1 || sop == 2) && sopcde == 13)
     {
       int shift = (sop + 1) * 8;
       TRACE_INSN (cpu, "R%i = ALIGN%i (R%i, R%i);", dst0, shift, src1, src0);
       STORE (DREG (dst0), (DREG (src1) << (32 - shift)) | (DREG (src0) >> shift));
     }
   else
     illegal_instruction (cpu);
 }
 
+static bu64
+sgn_extend (bu40 org, bu40 val, int size)
+{
+  bu64 ret = val;
+
+  if (org & (1ULL << (size - 1)))
+    {
+      /* We need to shift in to the MSB which is set.  */
+      int n;
+
+      for (n = 40; n >= 0; n--)
+        if (ret & (1ULL << n))
+          break;
+      ret |= (-1ULL << n);
+    }
+  else
+    ret &= ~(-1ULL << 39);
+
+  return ret;
+}
 static void
 decode_dsp32shiftimm_0 (SIM_CPU *cpu, bu16 iw0, bu16 iw1)
 {
   /* dsp32shiftimm
      +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
      | 1 | 1 | 0 | 0 |.M.| 1 | 1 | 0 | 1 | - | - |.sopcde............|
      |.sop...|.HLs...|.dst0......|.immag.................|.src1......|
      +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
   int src1     = ((iw1 >> DSP32ShiftImm_src1_bits) & DSP32ShiftImm_src1_mask);
   int sop      = ((iw1 >> DSP32ShiftImm_sop_bits) & DSP32ShiftImm_sop_mask);
@@ skipping 14 matching lines @@
       bu16 in = DREG (src1) >> ((HLs & 1) ? 16 : 0);
       bu16 result;
       bu32 v;
 
       if (sop == 0)
         {
           TRACE_INSN (cpu, "R%i.%c = R%i.%c >>> %i;",
                       dst0, (HLs & 2) ? 'H' : 'L',
                       src1, (HLs & 1) ? 'H' : 'L', newimmag);
           if (newimmag > 16)
-            result = lshift (cpu, in, 16 - (newimmag & 0xF), 16, 0);
+            {
+              result = lshift (cpu, in, 16 - (newimmag & 0xF), 16, 0, 1);
+              if (((result >> 15) & 0x1) != ((in >> 15) & 0x1))
+                {
+                  SET_ASTATREG (v, 1);
+                  SET_ASTATREG (vs, 1);
+                }
+            }
           else
             result = ashiftrt (cpu, in, newimmag, 16);
         }
       else if (sop == 1 && bit8 == 0)
         {
           TRACE_INSN (cpu, "R%i.%c = R%i.%c << %i (S);",
                       dst0, (HLs & 2) ? 'H' : 'L',
                       src1, (HLs & 1) ? 'H' : 'L', immag);
-          result = lshift (cpu, in, immag, 16, 1);
+          result = lshift (cpu, in, immag, 16, 1, 1);
         }
       else if (sop == 1 && bit8)
         {
           TRACE_INSN (cpu, "R%i.%c = R%i.%c >>> %i (S);",
                       dst0, (HLs & 2) ? 'H' : 'L',
-                      src1, (HLs & 1) ? 'H' : 'L', immag);
-          result = lshift (cpu, in, immag, 16, 1);
+                      src1, (HLs & 1) ? 'H' : 'L', newimmag);
+          if (newimmag > 16)
+            {
+              int shift = 32 - newimmag;
+              bu16 inshift = in << shift;
+
+              if (((inshift & ~0xFFFF)
+                   && ((inshift & ~0xFFFF) >> 16) != ~(~0 << shift))
+                  || (inshift & 0x8000) != (in & 0x8000))
+                {
+                  if (in & 0x8000)
+                    result = 0x8000;
+                  else
+                    result = 0x7fff;
+                  SET_ASTATREG (v, 1);
+                  SET_ASTATREG (vs, 1);
+                }
+              else
+                {
+                  result = inshift;
+                  SET_ASTATREG (v, 0);
+                }
+
+              SET_ASTATREG (az, !result);
+              SET_ASTATREG (an, !!(result & 0x8000));
+            }
+          else
+            {
+              result = ashiftrt (cpu, in, newimmag, 16);
+              result = sgn_extend (in, result, 16);
+            }
         }
       else if (sop == 2 && bit8)
         {
           TRACE_INSN (cpu, "R%i.%c = R%i.%c >> %i;",
                       dst0, (HLs & 2) ? 'H' : 'L',
                       src1, (HLs & 1) ? 'H' : 'L', newimmag);
           result = lshiftrt (cpu, in, newimmag, 16);
         }
       else if (sop == 2 && bit8 == 0)
         {
           TRACE_INSN (cpu, "R%i.%c = R%i.%c << %i;",
                       dst0, (HLs & 2) ? 'H' : 'L',
                       src1, (HLs & 1) ? 'H' : 'L', immag);
-          result = lshift (cpu, in, immag, 16, 0);
+          result = lshift (cpu, in, immag, 16, 0, 1);
         }
       else
         illegal_instruction (cpu);
 
       v = DREG (dst0);
       if (HLs & 2)
         STORE (DREG (dst0), (v & 0xFFFF) | (result << 16));
       else
         STORE (DREG (dst0), (v & 0xFFFF0000) | result);
     }
   else if (sop == 2 && sopcde == 3 && (HLs == 1 || HLs == 0))
     {
       int shift = imm6 (immag);
       bu32 cc = CCREG;
       bu40 acc = get_unextended_acc (cpu, HLs);
 
       TRACE_INSN (cpu, "A%i = ROT A%i BY %i;", HLs, HLs, shift);
       TRACE_DECODE (cpu, "A%i:%#"PRIx64" shift:%i CC:%i", HLs, acc, shift, cc);
 
       acc = rot40 (acc, shift, &cc);
       SET_AREG (HLs, acc);
       if (shift)
         SET_CCREG (cc);
     }
   else if (sop == 0 && sopcde == 3 && bit8 == 1)
     {
       /* Arithmetic shift, so shift in sign bit copies.  */
-      bu64 acc;
+      bu64 acc, val;
       int shift = uimm5 (newimmag);
       HLs = !!HLs;
 
       TRACE_INSN (cpu, "A%i = A%i >>> %i;", HLs, HLs, shift);
 
       acc = get_extended_acc (cpu, HLs);
-      acc >>= shift;
+      val = acc >> shift;
+
       /* Sign extend again.  */
-      if (acc & (1ULL << 39))
-        acc |= -(1ULL << 39);
-      else
-        acc &= ~(-(1ULL << 39));
+      val = sgn_extend (acc, val, 40);
 
-      STORE (AXREG (HLs), (acc >> 32) & 0xFF);
-      STORE (AWREG (HLs), acc & 0xFFFFFFFF);
+      STORE (AXREG (HLs), (val >> 32) & 0xFF);
+      STORE (AWREG (HLs), val & 0xFFFFFFFF);
+      STORE (ASTATREG (an), !!(val & (1ULL << 39)));
+      STORE (ASTATREG (az), !val);
+      STORE (ASTATREG (av[HLs]), 0);
     }
   else if ((sop == 0 && sopcde == 3 && bit8 == 0)
            || (sop == 1 && sopcde == 3))
     {
       bu64 acc;
       int shiftup = uimm5 (immag);
       int shiftdn = uimm5 (newimmag);
       HLs = !!HLs;
 
       TRACE_INSN (cpu, "A%i = A%i %s %i;", HLs, HLs,
@@ skipping 24 matching lines @@
   else if (sop == 1 && sopcde == 1 && bit8 == 0)
     {
       int count = imm5 (immag);
       bu16 val0 = DREG (src1) >> 16;
       bu16 val1 = DREG (src1) & 0xFFFF;
       bu32 astat;
 
       TRACE_INSN (cpu, "R%i = R%i << %i (V,S);", dst0, src1, count);
       if (count >= 0)
         {
-          val0 = lshift (cpu, val0, count, 16, 1);
+          val0 = lshift (cpu, val0, count, 16, 1, 1);
           astat = ASTAT;
-          val1 = lshift (cpu, val1, count, 16, 1);
+          val1 = lshift (cpu, val1, count, 16, 1, 1);
         }
       else
         {
           val0 = ashiftrt (cpu, val0, -count, 16);
           astat = ASTAT;
           val1 = ashiftrt (cpu, val1, -count, 16);
         }
       SET_ASTAT (ASTAT | astat);
 
       STORE (DREG (dst0), (val0 << 16) | val1);
@@ skipping 14 matching lines @@
       STORE (DREG (dst0), val0 | (val1 << 16));
     }
   else if (sop == 2 && sopcde == 1 && bit8 == 0)
     {
       int count = imm5 (immag);
       bu16 val0 = DREG (src1) & 0xFFFF;
       bu16 val1 = DREG (src1) >> 16;
       bu32 astat;
 
       TRACE_INSN (cpu, "R%i = R%i << %i (V);", dst0, src1, count);
-      val0 = lshift (cpu, val0, count, 16, 0);
+      val0 = lshift (cpu, val0, count, 16, 0, 1);
       astat = ASTAT;
-      val1 = lshift (cpu, val1, count, 16, 0);
+      val1 = lshift (cpu, val1, count, 16, 0, 1);
       SET_ASTAT (ASTAT | astat);
 
       STORE (DREG (dst0), val0 | (val1 << 16));
     }
   else if (sopcde == 1 && (sop == 0 || (sop == 1 && bit8 == 1)))
     {
       int count = uimm5 (newimmag);
       bu16 val0 = DREG (src1) & 0xFFFF;
       bu16 val1 = DREG (src1) >> 16;
       bu32 astat;
 
       TRACE_INSN (cpu, "R%i = R%i >>> %i %s;", dst0, src1, count,
                   sop == 0 ? "(V)" : "(V,S)");
 
-      if (count & 0x10)
+      if (count > 16)
         {
-          val0 = lshift (cpu, val0, 16 - (count & 0xF), 16, 0);
+          int sgn0 = (val0 >> 15) & 0x1;
+          int sgn1 = (val1 >> 15) & 0x1;
+
+          val0 = lshift (cpu, val0, 16 - (count & 0xF), 16, 0, 1);
           astat = ASTAT;
-          val1 = lshift (cpu, val1, 16 - (count & 0xF), 16, 0);
+          val1 = lshift (cpu, val1, 16 - (count & 0xF), 16, 0, 1);
+
+          if ((sgn0 != ((val0 >> 15) & 0x1)) || (sgn1 != ((val1 >> 15) & 0x1)))
+            {
+              SET_ASTATREG (v, 1);
+              SET_ASTATREG (vs, 1);
+            }
         }
       else
         {
           val0 = ashiftrt (cpu, val0, count, 16);
           astat = ASTAT;
           val1 = ashiftrt (cpu, val1, count, 16);
         }
 
       SET_ASTAT (ASTAT | astat);
 
       STORE (DREG (dst0), REG_H_L (val1 << 16, val0));
     }
   else if (sop == 1 && sopcde == 2)
     {
       int count = imm6 (immag);
 
       TRACE_INSN (cpu, "R%i = R%i << %i (S);", dst0, src1, count);
-      STORE (DREG (dst0), lshift (cpu, DREG (src1), count, 32, 1));
+      STORE (DREG (dst0), lshift (cpu, DREG (src1), count, 32, 1, 1));
     }
   else if (sop == 2 && sopcde == 2)
     {
       int count = imm6 (newimmag);
 
       TRACE_INSN (cpu, "R%i = R%i >> %i;", dst0, src1, count);
 
       if (count < 0)
-        STORE (DREG (dst0), lshift (cpu, DREG (src1), -count, 32, 0));
+        STORE (DREG (dst0), lshift (cpu, DREG (src1), -count, 32, 0, 1));
       else
         STORE (DREG (dst0), lshiftrt (cpu, DREG (src1), count, 32));
     }
   else if (sop == 3 && sopcde == 2)
     {
       int shift = imm6 (immag);
       bu32 src = DREG (src1);
       bu32 ret, cc = CCREG;
 
       TRACE_INSN (cpu, "R%i = ROT R%i BY %i;", dst0, src1, shift);
       TRACE_DECODE (cpu, "R%i:%#x R%i:%#x shift:%i CC:%i",
                     dst0, DREG (dst0), src1, src, shift, cc);
 
       ret = rot32 (src, shift, &cc);
       STORE (DREG (dst0), ret);
       if (shift)
         SET_CCREG (cc);
     }
   else if (sop == 0 && sopcde == 2)
     {
       int count = imm6 (newimmag);
 
       TRACE_INSN (cpu, "R%i = R%i >>> %i;", dst0, src1, count);
 
       if (count < 0)
-        STORE (DREG (dst0), lshift (cpu, DREG (src1), -count, 32, 0));
+        STORE (DREG (dst0), lshift (cpu, DREG (src1), -count, 32, 0, 1));
       else
         STORE (DREG (dst0), ashiftrt (cpu, DREG (src1), count, 32));
     }
   else
     illegal_instruction (cpu);
 }
 
 static void
 outc (SIM_CPU *cpu, char ch)
 {
@@ skipping 213 matching lines @@
         decode_dspLDST_0 (cpu, iw0);
       else if ((iw0 & 0xF000) == 0x9000)
         decode_LDST_0 (cpu, iw0);
       else if ((iw0 & 0xFC00) == 0xB800)
         decode_LDSTiiFP_0 (cpu, iw0);
       else if ((iw0 & 0xE000) == 0xA000)
         decode_LDSTii_0 (cpu, iw0);
       else
         {
           TRACE_EXTRACT (cpu, "%s: no matching 16-bit pattern", __func__);
-          illegal_instruction (cpu);
+          illegal_instruction_or_combination (cpu);
         }
       return insn_len;
     }
 
   /* Grab the next 16 bits to determine if it's a 32-bit or 64-bit opcode.  */
   iw1 = IFETCH (pc + 2);
   if ((iw0 & BIT_MULTI_INS) && (iw0 & 0xe800) != 0xe800 /* not linkage  */)
     {
       SIM_DESC sd = CPU_STATE (cpu);
       trace_prefix (sd, cpu, NULL_CIA, pc, TRACE_LINENUM_P (cpu),
                         NULL, 0, "|| %#"PRIx64, sim_events_time (sd));
       insn_len = 8;
+      PARALLEL_GROUP = BFIN_PARALLEL_GROUP0;
     }
   else
     insn_len = 4;
 
   TRACE_EXTRACT (cpu, "%s: iw0:%#x iw1:%#x insn_len:%i", __func__,
                      iw0, iw1, insn_len);
 
   /* Only cache on first run through (in case of parallel insns).  */
   if (INSN_LEN == 0)
     INSN_LEN = insn_len;
+  else
+    /* Once you're past the first slot, only 16bit insns are valid.  */
+    illegal_instruction_combination (cpu);
 
   if ((iw0 & 0xf7ff) == 0xc003 && (iw1 & 0xfe00) == 0x1800)
     {
       PROFILE_COUNT_INSN (cpu, pc, BFIN_INSN_dsp32mac);
       TRACE_INSN (cpu, "MNOP;");
     }
   else if (((iw0 & 0xFF80) == 0xE080) && ((iw1 & 0x0C00) == 0x0000))
     decode_LoopSetup_0 (cpu, iw0, iw1, pc);
   else if (((iw0 & 0xFF00) == 0xE100) && ((iw1 & 0x0000) == 0x0000))
     decode_LDIMMhalf_0 (cpu, iw0, iw1);
@@ skipping 28 matching lines @@
   return insn_len;
 }
 
 bu32
 interp_insn_bfin (SIM_CPU *cpu, bu32 pc)
 {
   int i;
   bu32 insn_len;
 
   BFIN_CPU_STATE.n_stores = 0;
+  PARALLEL_GROUP = BFIN_PARALLEL_NONE;
   DIS_ALGN_EXPT &= ~1;
   CYCLE_DELAY = 1;
   INSN_LEN = 0;
 
   insn_len = _interp_insn_bfin (cpu, pc);
 
   /* Proper display of multiple issue instructions.  */
   if (insn_len == 8)
     {
+      PARALLEL_GROUP = BFIN_PARALLEL_GROUP1;
       _interp_insn_bfin (cpu, pc + 4);
+      PARALLEL_GROUP = BFIN_PARALLEL_GROUP2;
       _interp_insn_bfin (cpu, pc + 6);
     }
   for (i = 0; i < BFIN_CPU_STATE.n_stores; i++)
     {
       bu32 *addr = BFIN_CPU_STATE.stores[i].addr;
       *addr = BFIN_CPU_STATE.stores[i].val;
       TRACE_REGISTER (cpu, "dequeuing write %s = %#x",
                       get_store_name (cpu, addr), *addr);
     }
 
   cycles_inc (cpu, CYCLE_DELAY);
 
   /* Set back to zero in case a pending CEC event occurs
      after this this insn.  */
   INSN_LEN = 0;
 
   return insn_len;
 }