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Side by Side Diff: sim/avr/interp.c

Issue 11969036: Merge GDB 7.5.1 (Closed) Base URL: http://git.chromium.org/native_client/nacl-gdb.git@master
Patch Set: Created 7 years, 11 months ago
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1 /* Simulator for Atmel's AVR core. 1 /* Simulator for Atmel's AVR core.
2 Copyright (C) 2009-2012 Free Software Foundation, Inc. 2 Copyright (C) 2009-2012 Free Software Foundation, Inc.
3 Written by Tristan Gingold, AdaCore. 3 Written by Tristan Gingold, AdaCore.
4 4
5 This file is part of GDB, the GNU debugger. 5 This file is part of GDB, the GNU debugger.
6 6
7 This program is free software; you can redistribute it and/or modify 7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by 8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or 9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version. 10 (at your option) any later version.
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863 } 863 }
864 864
865 void 865 void
866 sim_resume (SIM_DESC sd, int step, int signal) 866 sim_resume (SIM_DESC sd, int step, int signal)
867 { 867 {
868 unsigned int ipc; 868 unsigned int ipc;
869 869
870 if (step) 870 if (step)
871 { 871 {
872 cpu_exception = sim_stopped; 872 cpu_exception = sim_stopped;
873 cpu_signal = TARGET_SIGNAL_TRAP; 873 cpu_signal = GDB_SIGNAL_TRAP;
874 } 874 }
875 else 875 else
876 cpu_exception = sim_running; 876 cpu_exception = sim_running;
877 877
878 do 878 do
879 { 879 {
880 int code; 880 int code;
881 word op; 881 word op;
882 byte res; 882 byte res;
883 byte r, d, vd; 883 byte r, d, vd;
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993 pc |= sram[++sp] << 8; 993 pc |= sram[++sp] << 8;
994 pc |= sram[++sp]; 994 pc |= sram[++sp];
995 write_word (REG_SP, sp); 995 write_word (REG_SP, sp);
996 } 996 }
997 cycles += 3; 997 cycles += 3;
998 break; 998 break;
999 999
1000 case OP_break: 1000 case OP_break:
1001 /* Stop on this address. */ 1001 /* Stop on this address. */
1002 cpu_exception = sim_stopped; 1002 cpu_exception = sim_stopped;
1003 » cpu_signal = TARGET_SIGNAL_TRAP; 1003 » cpu_signal = GDB_SIGNAL_TRAP;
1004 pc = ipc; 1004 pc = ipc;
1005 break; 1005 break;
1006 1006
1007 case OP_bld: 1007 case OP_bld:
1008 d = get_d (op); 1008 d = get_d (op);
1009 r = flash[ipc].r; 1009 r = flash[ipc].r;
1010 if (sram[SREG] & SREG_T) 1010 if (sram[SREG] & SREG_T)
1011 sram[d] |= r; 1011 sram[d] |= r;
1012 else 1012 else
1013 sram[d] &= ~r; 1013 sram[d] &= ~r;
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1756 sim_stop_reason (SIM_DESC sd, enum sim_stop * reason, int *sigrc) 1756 sim_stop_reason (SIM_DESC sd, enum sim_stop * reason, int *sigrc)
1757 { 1757 {
1758 *reason = cpu_exception; 1758 *reason = cpu_exception;
1759 *sigrc = cpu_signal; 1759 *sigrc = cpu_signal;
1760 } 1760 }
1761 1761
1762 int 1762 int
1763 sim_stop (SIM_DESC sd) 1763 sim_stop (SIM_DESC sd)
1764 { 1764 {
1765 cpu_exception = sim_stopped; 1765 cpu_exception = sim_stopped;
1766 cpu_signal = TARGET_SIGNAL_INT; 1766 cpu_signal = GDB_SIGNAL_INT;
1767 return 1; 1767 return 1;
1768 } 1768 }
1769 1769
1770 void 1770 void
1771 sim_info (SIM_DESC sd, int verbose) 1771 sim_info (SIM_DESC sd, int verbose)
1772 { 1772 {
1773 callback->printf_filtered 1773 callback->printf_filtered
1774 (callback, "\n\n# cycles %10u\n", cycles); 1774 (callback, "\n\n# cycles %10u\n", cycles);
1775 } 1775 }
1776 1776
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1852 sim_set_callbacks (host_callback *ptr) 1852 sim_set_callbacks (host_callback *ptr)
1853 { 1853 {
1854 callback = ptr; 1854 callback = ptr;
1855 } 1855 }
1856 1856
1857 char ** 1857 char **
1858 sim_complete_command (SIM_DESC sd, char *text, char *word) 1858 sim_complete_command (SIM_DESC sd, char *text, char *word)
1859 { 1859 {
1860 return NULL; 1860 return NULL;
1861 } 1861 }
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