Merge GDB 7.5.1

opcodes/sparc-dis.c

 /* Print SPARC instructions.
    Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
-   2000, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2010
+   2000, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2010, 2012
    Free Software Foundation, Inc.
 
    This file is part of the GNU opcodes library.
 
    This library is free software; you can redistribute it and/or modify
    it under the terms of the GNU General Public License as published by
    the Free Software Foundation; either version 3, or (at your option)
    any later version.
 
    It is distributed in the hope that it will be useful, but WITHOUT
    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
    License for more details.
 
    You should have received a copy of the GNU General Public License
    along with this program; if not, write to the Free Software
    Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
    MA 02110-1301, USA.  */
 
+#include "sysdep.h"
 #include <stdio.h>
-
-#include "sysdep.h"
 #include "opcode/sparc.h"
 #include "dis-asm.h"
 #include "libiberty.h"
 #include "opintl.h"
 
 /* Bitmask of v9 architectures.  */
 #define MASK_V9 ((1 << SPARC_OPCODE_ARCH_V9) \
                  | (1 << SPARC_OPCODE_ARCH_V9A) \
                  | (1 << SPARC_OPCODE_ARCH_V9B))
 /* 1 if INSN is for v9 only.  */
@@ skipping 65 matching lines @@
   "resv14", "resv15", "resv16", "resv17", "resv18", "resv19", "resv20",
   "resv21", "resv22", "resv23", "resv24", "resv25", "resv26", "resv27",
   "resv28", "resv29", "resv30", "hstick_cmpr"
 };
 
 /* These are ordered according to there register number in
    rd and wr insns (-16).  */
 static char *v9a_asr_reg_names[] =
 {
   "pcr", "pic", "dcr", "gsr", "set_softint", "clear_softint",
-  "softint", "tick_cmpr", "stick", "stick_cmpr", "resv26",
-  "resv27", "cps"
+  "softint", "tick_cmpr", "stick", "stick_cmpr", "cfr",
+  "pause", "cps"
 };
 
 /* Macros used to extract instruction fields.  Not all fields have
    macros defined here, only those which are actually used.  */
 
 #define X_RD(i)      (((i) >> 25) & 0x1f)
 #define X_RS1(i)     (((i) >> 14) & 0x1f)
 #define X_LDST_I(i)  (((i) >> 13) & 1)
 #define X_ASI(i)     (((i) >> 5) & 0xff)
 #define X_RS2(i)     (((i) >> 0) & 0x1f)
 #define X_RS3(i)     (((i) >> 9) & 0x1f)
 #define X_IMM(i,n)   (((i) >> 0) & ((1 << (n)) - 1))
 #define X_SIMM(i,n)  SEX (X_IMM ((i), (n)), (n))
 #define X_DISP22(i)  (((i) >> 0) & 0x3fffff)
 #define X_IMM22(i)   X_DISP22 (i)
 #define X_DISP30(i)  (((i) >> 0) & 0x3fffffff)
 
 /* These are for v9.  */
 #define X_DISP16(i)  (((((i) >> 20) & 3) << 14) | (((i) >> 0) & 0x3fff))
+#define X_DISP10(i)  (((((i) >> 19) & 3) << 8) | (((i) >> 5) & 0xff))
 #define X_DISP19(i)  (((i) >> 0) & 0x7ffff)
 #define X_MEMBAR(i)  ((i) & 0x7f)
 
 /* Here is the union which was used to extract instruction fields
    before the shift and mask macros were written.
 
    union sparc_insn
      {
        unsigned long int code;
        struct
@@ skipping 554 matching lines @@
                       if (found_plus)
                         imm_added_to_rs1 = 1;
 
                       if (imm <= 9)
                         (*info->fprintf_func) (stream, "%d", imm);
                       else
                         (*info->fprintf_func) (stream, "%#x", imm);
                     }
                     break;
 
+                  case ')':     /* 5 bit unsigned immediate from RS3.  */
+                    (info->fprintf_func) (stream, "%#x", X_RS3 (insn));
+                    break;
+
                   case 'X':     /* 5 bit unsigned immediate.  */
                   case 'Y':     /* 6 bit unsigned immediate.  */
                     {
                       int imm = X_IMM (insn, *s == 'X' ? 5 : 6);
 
                       if (imm <= 9)
                         (info->fprintf_func) (stream, "%d", imm);
                       else
                         (info->fprintf_func) (stream, "%#x", (unsigned) imm);
                     }
@@ skipping 20 matching lines @@
                                   (info->fprintf_func) (stream, "|");
                                 name = sparc_decode_membar (bit);
                                 (info->fprintf_func) (stream, "%s", name);
                                 printed_one = 1;
                               }
                             bit >>= 1;
                           }
                       break;
                     }
 
+                  case '=':
+                    info->target = memaddr + SEX (X_DISP10 (insn), 10) * 4;
+                    (*info->print_address_func) (info->target, info);
+                    break;
+
                   case 'k':
                     info->target = memaddr + SEX (X_DISP16 (insn), 16) * 4;
                     (*info->print_address_func) (info->target, info);
                     break;
 
                   case 'G':
                     info->target = memaddr + SEX (X_DISP19 (insn), 19) * 4;
                     (*info->print_address_func) (info->target, info);
                     break;
 
@@ skipping 265 matching lines @@
             }
 
           return sizeof (buffer);
         }
     }
 
   info->insn_type = dis_noninsn;        /* Mark as non-valid instruction.  */
   (*info->fprintf_func) (stream, _("unknown"));
   return sizeof (buffer);
 }