opcodes/m68hc11-opc.c - Issue 11969036: Merge GDB 7.5.1

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Issue 11969036: Merge GDB 7.5.1 (Closed) Base URL: http://git.chromium.org/native_client/nacl-gdb.git@master

Patch Set: Created 7 years, 11 months ago

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1 /* m68hc11-opc.c -- Motorola 68HC11 & 68HC12 opcode list	1 /* m68hc11-opc.c -- Motorola 68HC11, 68HC12, 9S12X and XGATE opcode list

2 Copyright 1999, 2000, 2002, 2005, 2007 Free Software Foundation, Inc.	2 Copyright 1999, 2000, 2002, 2005, 2007, 2012

	3 Free Software Foundation, Inc.

3 Written by Stephane Carrez (stcarrez@nerim.fr)	4 Written by Stephane Carrez (stcarrez@nerim.fr)

	5 XGATE and S12X added by James Murray (jsm@jsm-net.demon.co.uk)

	6 Note: min/max cycles not updated for S12X opcodes.

4	7

5 This file is part of the GNU opcodes library.	8 This file is part of the GNU opcodes library.

6	9

7 This library is free software; you can redistribute it and/or modify	10 This library is free software; you can redistribute it and/or modify

8 it under the terms of the GNU General Public License as published by	11 it under the terms of the GNU General Public License as published by

9 the Free Software Foundation; either version 3, or (at your option)	12 the Free Software Foundation; either version 3, or (at your option)

10 any later version.	13 any later version.

11	14

12 It is distributed in the hope that it will be useful, but WITHOUT	15 It is distributed in the hope that it will be useful, but WITHOUT

13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY	16 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY

(...skipping 82 matching lines...) Expand 10 before \| Expand all \| Expand 10 after Loading...
96 #define OP_EXG_MARKER M6812_OP_EXG_MARKER	99 #define OP_EXG_MARKER M6812_OP_EXG_MARKER

97 #define OP_TFR_MARKER M6812_OP_TFR_MARKER	100 #define OP_TFR_MARKER M6812_OP_TFR_MARKER

98 #define OP_DBEQ_MARKER (M6812_OP_DBCC_MARKER\|M6812_OP_EQ_MARKER)	101 #define OP_DBEQ_MARKER (M6812_OP_DBCC_MARKER\|M6812_OP_EQ_MARKER)

99 #define OP_DBNE_MARKER (M6812_OP_DBCC_MARKER)	102 #define OP_DBNE_MARKER (M6812_OP_DBCC_MARKER)

100 #define OP_TBEQ_MARKER (M6812_OP_TBCC_MARKER\|M6812_OP_EQ_MARKER)	103 #define OP_TBEQ_MARKER (M6812_OP_TBCC_MARKER\|M6812_OP_EQ_MARKER)

101 #define OP_TBNE_MARKER (M6812_OP_TBCC_MARKER)	104 #define OP_TBNE_MARKER (M6812_OP_TBCC_MARKER)

102 #define OP_IBEQ_MARKER (M6812_OP_IBCC_MARKER\|M6812_OP_EQ_MARKER)	105 #define OP_IBEQ_MARKER (M6812_OP_IBCC_MARKER\|M6812_OP_EQ_MARKER)

103 #define OP_IBNE_MARKER (M6812_OP_IBCC_MARKER)	106 #define OP_IBNE_MARKER (M6812_OP_IBCC_MARKER)

104	107

105 /*	108 /*

106 { "test", OP_NONE, 1, 0x00, 5, _M, CHG_NONE, cpu6811 },	109 { "test", OP_NONE, 1, 0x00, 5, _M, CHG_NONE, cpu6811, 0 },

107 +-- cpu	110 +-- cpu +-- XGATE o pcode mask

108 Name -+ +------- Insn CCR changes	111 Name -+ +------- Insn CCR changes

109 Format ------+ +----------- Max # cycles	112 Format ------+ +----------- Max # cycles

110 Size --------------------+ +--------------- Min # cycles	113 Size --------------------+ +--------------- Min # cycles

111 +--------------------- Opcode	114 +--------------------- Opcode

112 */	115 */

113 const struct m68hc11_opcode m68hc11_opcodes[] = {	116 const struct m68hc11_opcode m68hc11_opcodes[] = {

114 { "aba", OP_NONE, 1, 0x1b, 2, 2, CHG_HNZVC, cpu6811 },	117 { "aba", OP_NONE, 1, 0x1b, 2, 2, CHG_HNZVC, cpu6811, 0 },

115 { "aba", OP_NONE \| OP_PAGE2,2, 0x06, 2, 2, CHG_HNZVC, cpu6812 },	118 { "aba", OP_NONE \| OP_PAGE2,2, 0x06, 2, 2, CHG_HNZVC, cpu6812\|cpu9s12x, 0 },

116 { "abx", OP_NONE, 1, 0x3a, 3, 3, CHG_NONE, cpu6811 },	119 { "abx", OP_NONE, 1, 0x3a, 3, 3, CHG_NONE, cpu6811, 0 },

117 { "aby", OP_NONE \| OP_PAGE2,2, 0x3a, 4, 4, CHG_NONE, cpu6811 },	120 { "aby", OP_NONE \| OP_PAGE2,2, 0x3a, 4, 4, CHG_NONE, cpu6811, 0 },

118	121

119 { "adca", OP_IMM8, 2, 0x89, 1, 1, CHG_HNZVC, cpu6811\|cpu6812 },	122 { "adca", OP_IMM8, 2, 0x89, 1, 1, CHG_HNZVC, cpu6811\|cpu6812\|cpu9 s12x, 0 },

120 { "adca", OP_DIRECT, 2, 0x99, 3, 3, CHG_HNZVC, cpu6811\|cpu6812 },	123 { "adca", OP_DIRECT, 2, 0x99, 3, 3, CHG_HNZVC, cpu6811\|cpu6812\|cpu9 s12x, 0 },

121 { "adca", OP_IND16, 3, 0xb9, 3, 3, CHG_HNZVC, cpu6811\|cpu6812 },	124 { "adca", OP_IND16, 3, 0xb9, 3, 3, CHG_HNZVC, cpu6811\|cpu6812\|cpu9 s12x, 0 },

122 { "adca", OP_IX, 2, 0xa9, 4, 4, CHG_HNZVC, cpu6811 },	125 { "adca", OP_IX, 2, 0xa9, 4, 4, CHG_HNZVC, cpu6811, 0 },

123 { "adca", OP_IY \| OP_PAGE2, 3, 0xa9, 5, 5, CHG_HNZVC, cpu6811 },	126 { "adca", OP_IY \| OP_PAGE2, 3, 0xa9, 5, 5, CHG_HNZVC, cpu6811, 0 },

124 { "adca", OP_IDX, 2, 0xa9, 3, 3, CHG_HNZVC, cpu6812 },	127 { "adca", OP_IDX, 2, 0xa9, 3, 3, CHG_HNZVC, cpu6812\|cpu9s12x, 0 },

125 { "adca", OP_IDX_1, 3, 0xa9, 3, 3, CHG_HNZVC, cpu6812 },	128 { "adca", OP_IDX_1, 3, 0xa9, 3, 3, CHG_HNZVC, cpu6812\|cpu9s12x, 0 },

126 { "adca", OP_IDX_2, 4, 0xa9, 4, 4, CHG_HNZVC, cpu6812 },	129 { "adca", OP_IDX_2, 4, 0xa9, 4, 4, CHG_HNZVC, cpu6812\|cpu9s12x, 0 },

127 { "adca", OP_D_IDX, 2, 0xa9, 6, 6, CHG_HNZVC, cpu6812 },	130 { "adca", OP_D_IDX, 2, 0xa9, 6, 6, CHG_HNZVC, cpu6812\|cpu9s12x, 0 },

128 { "adca", OP_D_IDX_2, 4, 0xa9, 6, 6, CHG_HNZVC, cpu6812 },	131 { "adca", OP_D_IDX_2, 4, 0xa9, 6, 6, CHG_HNZVC, cpu6812\|cpu9s12x, 0 },

129	132

130 { "adcb", OP_IMM8, 2, 0xc9, 1, 1, CHG_HNZVC, cpu6811\|cpu6812 },	133 { "adcb", OP_IMM8, 2, 0xc9, 1, 1, CHG_HNZVC, cpu6811\|cpu6812\|cpu9 s12x, 0 },

131 { "adcb", OP_DIRECT, 2, 0xd9, 3, 3, CHG_HNZVC, cpu6811\|cpu6812 },	134 { "adcb", OP_DIRECT, 2, 0xd9, 3, 3, CHG_HNZVC, cpu6811\|cpu6812\|cpu9 s12x, 0 },

132 { "adcb", OP_IND16, 3, 0xf9, 3, 3, CHG_HNZVC, cpu6811\|cpu6812 },	135 { "adcb", OP_IND16, 3, 0xf9, 3, 3, CHG_HNZVC, cpu6811\|cpu6812\|cpu9 s12x, 0 },

133 { "adcb", OP_IX, 2, 0xe9, 4, 4, CHG_HNZVC, cpu6811 },	136 { "adcb", OP_IX, 2, 0xe9, 4, 4, CHG_HNZVC, cpu6811, 0 },

134 { "adcb", OP_IY \| OP_PAGE2, 3, 0xe9, 5, 5, CHG_HNZVC, cpu6811 },	137 { "adcb", OP_IY \| OP_PAGE2, 3, 0xe9, 5, 5, CHG_HNZVC, cpu6811, 0 },

135 { "adcb", OP_IDX, 2, 0xe9, 3, 3, CHG_HNZVC, cpu6812 },	138 { "adcb", OP_IDX, 2, 0xe9, 3, 3, CHG_HNZVC, cpu6812\|cpu9s12x, 0 },

136 { "adcb", OP_IDX_1, 3, 0xe9, 3, 3, CHG_HNZVC, cpu6812 },	139 { "adcb", OP_IDX_1, 3, 0xe9, 3, 3, CHG_HNZVC, cpu6812\|cpu9s12x, 0 },

137 { "adcb", OP_IDX_2, 4, 0xe9, 4, 4, CHG_HNZVC, cpu6812 },	140 { "adcb", OP_IDX_2, 4, 0xe9, 4, 4, CHG_HNZVC, cpu6812\|cpu9s12x, 0 },

138 { "adcb", OP_D_IDX, 2, 0xe9, 6, 6, CHG_HNZVC, cpu6812 },	141 { "adcb", OP_D_IDX, 2, 0xe9, 6, 6, CHG_HNZVC, cpu6812\|cpu9s12x, 0 },

139 { "adcb", OP_D_IDX_2, 4, 0xe9, 6, 6, CHG_HNZVC, cpu6812 },	142 { "adcb", OP_D_IDX_2, 4, 0xe9, 6, 6, CHG_HNZVC, cpu6812\|cpu9s12x, 0 },

140	143

141 { "adda", OP_IMM8, 2, 0x8b, 1, 1, CHG_HNZVC, cpu6811\|cpu6812 },	144 { "adda", OP_IMM8, 2, 0x8b, 1, 1, CHG_HNZVC, cpu6811\|cpu6812\|cpu9 s12x, 0 },

142 { "adda", OP_DIRECT, 2, 0x9b, 3, 3, CHG_HNZVC, cpu6811\|cpu6812 },	145 { "adda", OP_DIRECT, 2, 0x9b, 3, 3, CHG_HNZVC, cpu6811\|cpu6812\|cpu9 s12x, 0 },

143 { "adda", OP_IND16, 3, 0xbb, 3, 3, CHG_HNZVC, cpu6811\|cpu6812 },	146 { "adda", OP_IND16, 3, 0xbb, 3, 3, CHG_HNZVC, cpu6811\|cpu6812\|cpu9 s12x, 0 },

144 { "adda", OP_IX, 2, 0xab, 4, 4, CHG_HNZVC, cpu6811 },	147 { "adda", OP_IX, 2, 0xab, 4, 4, CHG_HNZVC, cpu6811, 0 },

145 { "adda", OP_IY \| OP_PAGE2, 3, 0xab, 5, 5, CHG_HNZVC, cpu6811 },	148 { "adda", OP_IY \| OP_PAGE2, 3, 0xab, 5, 5, CHG_HNZVC, cpu6811, 0 },

146 { "adda", OP_IDX, 2, 0xab, 3, 3, CHG_HNZVC, cpu6812 },	149 { "adda", OP_IDX, 2, 0xab, 3, 3, CHG_HNZVC, cpu6812\|cpu9s12x, 0 },

147 { "adda", OP_IDX_1, 3, 0xab, 3, 3, CHG_HNZVC, cpu6812 },	150 { "adda", OP_IDX_1, 3, 0xab, 3, 3, CHG_HNZVC, cpu6812\|cpu9s12x, 0 },

148 { "adda", OP_IDX_2, 4, 0xab, 4, 4, CHG_HNZVC, cpu6812 },	151 { "adda", OP_IDX_2, 4, 0xab, 4, 4, CHG_HNZVC, cpu6812\|cpu9s12x, 0 },

149 { "adda", OP_D_IDX, 2, 0xab, 6, 6, CHG_HNZVC, cpu6812 },	152 { "adda", OP_D_IDX, 2, 0xab, 6, 6, CHG_HNZVC, cpu6812\|cpu9s12x, 0 },

150 { "adda", OP_D_IDX_2, 4, 0xab, 6, 6, CHG_HNZVC, cpu6812 },	153 { "adda", OP_D_IDX_2, 4, 0xab, 6, 6, CHG_HNZVC, cpu6812\|cpu9s12x, 0 },

151	154

152 { "addb", OP_IMM8, 2, 0xcb, 1, 1, CHG_HNZVC, cpu6811\|cpu6812 },	155 { "addb", OP_IMM8, 2, 0xcb, 1, 1, CHG_HNZVC, cpu6811\|cpu6812\|cpu9 s12x, 0 },

153 { "addb", OP_DIRECT, 2, 0xdb, 3, 3, CHG_HNZVC, cpu6811\|cpu6812 },	156 { "addb", OP_DIRECT, 2, 0xdb, 3, 3, CHG_HNZVC, cpu6811\|cpu6812\|cpu9 s12x, 0 },

154 { "addb", OP_IND16, 3, 0xfb, 3, 3, CHG_HNZVC, cpu6811\|cpu6812 },	157 { "addb", OP_IND16, 3, 0xfb, 3, 3, CHG_HNZVC, cpu6811\|cpu6812\|cpu9 s12x, 0 },

155 { "addb", OP_IX, 2, 0xeb, 4, 4, CHG_HNZVC, cpu6811 },	158 { "addb", OP_IX, 2, 0xeb, 4, 4, CHG_HNZVC, cpu6811, 0 },

156 { "addb", OP_IY \| OP_PAGE2, 3, 0xeb, 5, 5, CHG_HNZVC, cpu6811 },	159 { "addb", OP_IY \| OP_PAGE2, 3, 0xeb, 5, 5, CHG_HNZVC, cpu6811, 0 },

157 { "addb", OP_IDX, 2, 0xeb, 3, 3, CHG_HNZVC, cpu6812 },	160 { "addb", OP_IDX, 2, 0xeb, 3, 3, CHG_HNZVC, cpu6812\|cpu9s12x, 0 },

158 { "addb", OP_IDX_1, 3, 0xeb, 3, 3, CHG_HNZVC, cpu6812 },	161 { "addb", OP_IDX_1, 3, 0xeb, 3, 3, CHG_HNZVC, cpu6812\|cpu9s12x, 0 },

159 { "addb", OP_IDX_2, 4, 0xeb, 4, 4, CHG_HNZVC, cpu6812 },	162 { "addb", OP_IDX_2, 4, 0xeb, 4, 4, CHG_HNZVC, cpu6812\|cpu9s12x, 0 },

160 { "addb", OP_D_IDX, 2, 0xeb, 6, 6, CHG_HNZVC, cpu6812 },	163 { "addb", OP_D_IDX, 2, 0xeb, 6, 6, CHG_HNZVC, cpu6812\|cpu9s12x, 0 },

161 { "addb", OP_D_IDX_2, 4, 0xeb, 6, 6, CHG_HNZVC, cpu6812 },	164 { "addb", OP_D_IDX_2, 4, 0xeb, 6, 6, CHG_HNZVC, cpu6812\|cpu9s12x, 0 },

162	165

163 { "addd", OP_IMM16, 3, 0xc3, 2, 2, CHG_NZVC, cpu6811\|cpu6812 },	166 { "addd", OP_IMM16, 3, 0xc3, 2, 2, CHG_NZVC, cpu6811\|cpu6812\|cpu9s 12x, 0 },

164 { "addd", OP_DIRECT, 2, 0xd3, 3, 3, CHG_NZVC, cpu6811\|cpu6812 },	167 { "addd", OP_DIRECT, 2, 0xd3, 3, 3, CHG_NZVC, cpu6811\|cpu6812\|cpu9s 12x, 0 },

165 { "addd", OP_IND16, 3, 0xf3, 3, 3, CHG_NZVC, cpu6811\|cpu6812 },	168 { "addd", OP_IND16, 3, 0xf3, 3, 3, CHG_NZVC, cpu6811\|cpu6812\|cpu9s 12x, 0 },

166 { "addd", OP_IX, 2, 0xe3, 6, 6, CHG_NZVC, cpu6811 },	169 { "addd", OP_IX, 2, 0xe3, 6, 6, CHG_NZVC, cpu6811, 0 },

167 { "addd", OP_IY \| OP_PAGE2, 3, 0xe3, 7, 7, CHG_NZVC, cpu6811 },	170 { "addd", OP_IY \| OP_PAGE2, 3, 0xe3, 7, 7, CHG_NZVC, cpu6811, 0 },

168 { "addd", OP_IDX, 2, 0xe3, 3, 3, CHG_NZVC, cpu6812 },	171 { "addd", OP_IDX, 2, 0xe3, 3, 3, CHG_NZVC, cpu6812\|cpu9s12x, 0 } ,

169 { "addd", OP_IDX_1, 3, 0xe3, 3, 3, CHG_NZVC, cpu6812 },	172 { "addd", OP_IDX_1, 3, 0xe3, 3, 3, CHG_NZVC, cpu6812\|cpu9s12x, 0 } ,

170 { "addd", OP_IDX_2, 4, 0xe3, 4, 4, CHG_NZVC, cpu6812 },	173 { "addd", OP_IDX_2, 4, 0xe3, 4, 4, CHG_NZVC, cpu6812\|cpu9s12x, 0 } ,

171 { "addd", OP_D_IDX, 2, 0xe3, 6, 6, CHG_NZVC, cpu6812 },	174 { "addd", OP_D_IDX, 2, 0xe3, 6, 6, CHG_NZVC, cpu6812\|cpu9s12x, 0 } ,

172 { "addd", OP_D_IDX_2, 4, 0xe3, 6, 6, CHG_NZVC, cpu6812 },	175 { "addd", OP_D_IDX_2, 4, 0xe3, 6, 6, CHG_NZVC, cpu6812\|cpu9s12x, 0 } ,

173	176

174 { "anda", OP_IMM8, 2, 0x84, 1, 1, CLR_V_CHG_NZ, cpu6811\|cpu6812 },	177 { "addx", OP_IMM16 \| OP_PAGE2, 3, 0x8b, 2, 2, CHG_NZVC, cpu9s12x, 0 },

175 { "anda", OP_DIRECT, 2, 0x94, 3, 3, CLR_V_CHG_NZ, cpu6811\|cpu6812 },	178 { "addx", OP_DIRECT \| OP_PAGE2, 2, 0x9b, 3, 3, CHG_NZVC, cpu9s12x, 0 },

176 { "anda", OP_IND16, 3, 0xb4, 3, 3, CLR_V_CHG_NZ, cpu6811\|cpu6812 },	179 { "addx", OP_IND16 \| OP_PAGE2, 3, 0xbb, 3, 3, CHG_NZVC, cpu9s12x, 0 },

177 { "anda", OP_IX, 2, 0xa4, 4, 4, CLR_V_CHG_NZ, cpu6811 },	180 { "addx", OP_IDX \| OP_PAGE2, 2, 0xab, 3, 3, CHG_NZVC, cpu9s12x, 0 },

178 { "anda", OP_IY \| OP_PAGE2, 3, 0xa4, 5, 5, CLR_V_CHG_NZ, cpu6811 },	181 { "addx", OP_IDX_1 \| OP_PAGE2, 3, 0xab, 3, 3, CHG_NZVC, cpu9s12x, 0 },

179 { "anda", OP_IDX, 2, 0xa4, 3, 3, CLR_V_CHG_NZ, cpu6812 },	182 { "addx", OP_IDX_2 \| OP_PAGE2, 4, 0xab, 4, 4, CHG_NZVC, cpu9s12x, 0 },

180 { "anda", OP_IDX_1, 3, 0xa4, 3, 3, CLR_V_CHG_NZ, cpu6812 },	183 { "addx", OP_D_IDX \| OP_PAGE2, 2, 0xab, 6, 6, CHG_NZVC, cpu9s12x, 0 },

181 { "anda", OP_IDX_2, 4, 0xa4, 4, 4, CLR_V_CHG_NZ, cpu6812 },	184 { "addx", OP_D_IDX_2 \| OP_PAGE2, 4, 0xab, 6, 6, CHG_NZVC, cpu9s12x, 0 },

182 { "anda", OP_D_IDX, 2, 0xa4, 6, 6, CLR_V_CHG_NZ, cpu6812 },	185

183 { "anda", OP_D_IDX_2, 4, 0xa4, 6, 6, CLR_V_CHG_NZ, cpu6812 },	186 { "addy", OP_IMM16 \| OP_PAGE2, 3, 0xcb, 2, 2, CHG_NZVC, cpu9s12x, 0 },

184	187 { "addy", OP_DIRECT \| OP_PAGE2, 2, 0xdb, 3, 3, CHG_NZVC, cpu9s12x, 0 },

185 { "andb", OP_IMM8, 2, 0xc4, 1, 1, CLR_V_CHG_NZ, cpu6811\|cpu6812 },	188 { "addy", OP_IND16 \| OP_PAGE2, 3, 0xfb, 3, 3, CHG_NZVC, cpu9s12x, 0 },

186 { "andb", OP_DIRECT, 2, 0xd4, 3, 3, CLR_V_CHG_NZ, cpu6811\|cpu6812 },	189 { "addy", OP_IDX \| OP_PAGE2, 2, 0xeb, 3, 3, CHG_NZVC, cpu9s12x, 0 },

187 { "andb", OP_IND16, 3, 0xf4, 3, 3, CLR_V_CHG_NZ, cpu6811\|cpu6812 },	190 { "addy", OP_IDX_1 \| OP_PAGE2, 3, 0xeb, 3, 3, CHG_NZVC, cpu9s12x, 0 },

188 { "andb", OP_IX, 2, 0xe4, 4, 4, CLR_V_CHG_NZ, cpu6811 },	191 { "addy", OP_IDX_2 \| OP_PAGE2, 4, 0xeb, 4, 4, CHG_NZVC, cpu9s12x, 0 },

189 { "andb", OP_IY \| OP_PAGE2, 3, 0xe4, 5, 5, CLR_V_CHG_NZ, cpu6811 },	192 { "addy", OP_D_IDX \| OP_PAGE2, 2, 0xeb, 6, 6, CHG_NZVC, cpu9s12x, 0 },

190 { "andb", OP_IDX, 2, 0xe4, 3, 3, CLR_V_CHG_NZ, cpu6812 },	193 { "addy", OP_D_IDX_2 \| OP_PAGE2, 4, 0xeb, 6, 6, CHG_NZVC, cpu9s12x, 0 },

191 { "andb", OP_IDX_1, 3, 0xe4, 3, 3, CLR_V_CHG_NZ, cpu6812 },	194

192 { "andb", OP_IDX_2, 4, 0xe4, 4, 4, CLR_V_CHG_NZ, cpu6812 },	195 { "aded", OP_IMM16 \| OP_PAGE2, 3, 0xc3, 2, 2, CHG_NZVC, cpu9s12x, 0 },

193 { "andb", OP_D_IDX, 2, 0xe4, 6, 6, CLR_V_CHG_NZ, cpu6812 },	196 { "aded", OP_DIRECT \| OP_PAGE2, 2, 0xd3, 3, 3, CHG_NZVC, cpu9s12x, 0 },

194 { "andb", OP_D_IDX_2, 4, 0xe4, 6, 6, CLR_V_CHG_NZ, cpu6812 },	197 { "aded", OP_IND16 \| OP_PAGE2, 3, 0xf3, 3, 3, CHG_NZVC, cpu9s12x, 0 },

195	198 { "aded", OP_IDX \| OP_PAGE2, 2, 0xe3, 3, 3, CHG_NZVC, cpu9s12x, 0 },

196 { "andcc", OP_IMM8, 2, 0x10, 1, 1, CHG_ALL, cpu6812 },	199 { "aded", OP_IDX_1 \| OP_PAGE2, 3, 0xe3, 3, 3, CHG_NZVC, cpu9s12x, 0 },

197	200 { "aded", OP_IDX_2 \| OP_PAGE2, 4, 0xe3, 4, 4, CHG_NZVC, cpu9s12x, 0 },

198 { "asl", OP_IND16, 3, 0x78, 4, 4, CHG_NZVC, cpu6811\|cpu6812 },	201 { "aded", OP_D_IDX \| OP_PAGE2, 2, 0xe3, 6, 6, CHG_NZVC, cpu9s12x, 0 },

199 { "asl", OP_IX, 2, 0x68, 6, 6, CHG_NZVC, cpu6811 },	202 { "aded", OP_D_IDX_2 \| OP_PAGE2, 4, 0xe3, 6, 6, CHG_NZVC, cpu9s12x, 0 },

200 { "asl", OP_IY \| OP_PAGE2, 3, 0x68, 7, 7, CHG_NZVC, cpu6811 },	203

201 { "asl", OP_IDX, 2, 0x68, 3, 3, CHG_NZVC, cpu6812 },	204 { "adex", OP_IMM16 \| OP_PAGE2, 3, 0x89, 2, 2, CHG_NZVC, cpu9s12x, 0 },

202 { "asl", OP_IDX_1, 3, 0x68, 4, 4, CHG_NZVC, cpu6812 },	205 { "adex", OP_DIRECT \| OP_PAGE2, 2, 0x99, 3, 3, CHG_NZVC, cpu9s12x, 0 },

203 { "asl", OP_IDX_2, 4, 0x68, 5, 5, CHG_NZVC, cpu6812 },	206 { "adex", OP_IND16 \| OP_PAGE2, 3, 0xb9, 3, 3, CHG_NZVC, cpu9s12x, 0 },

204 { "asl", OP_D_IDX, 2, 0x68, 6, 6, CHG_NZVC, cpu6812 },	207 { "adex", OP_IDX \| OP_PAGE2, 2, 0xa9, 3, 3, CHG_NZVC, cpu9s12x, 0 },

205 { "asl", OP_D_IDX_2, 4, 0x68, 6, 6, CHG_NZVC, cpu6812 },	208 { "adex", OP_IDX_1 \| OP_PAGE2, 3, 0xa9, 3, 3, CHG_NZVC, cpu9s12x, 0 },

206	209 { "adex", OP_IDX_2 \| OP_PAGE2, 4, 0xa9, 4, 4, CHG_NZVC, cpu9s12x, 0 },

207 { "asla", OP_NONE, 1, 0x48, 1, 1, CHG_NZVC, cpu6811\|cpu6812 },	210 { "adex", OP_D_IDX \| OP_PAGE2, 2, 0xa9, 6, 6, CHG_NZVC, cpu9s12x, 0 },

208 { "aslb", OP_NONE, 1, 0x58, 1, 1, CHG_NZVC, cpu6811\|cpu6812 },	211 { "adex", OP_D_IDX_2 \| OP_PAGE2, 4, 0xa9, 6, 6, CHG_NZVC, cpu9s12x, 0 },

209 { "asld", OP_NONE, 1, 0x05, 3, 3, CHG_NZVC, cpu6811 },	212

210 { "asld", OP_NONE, 1, 0x59, 1, 1, CHG_NZVC, cpu6812 },	213 { "adey", OP_IMM16 \| OP_PAGE2, 3, 0xc9, 2, 2, CHG_NZVC, cpu9s12x, 0 },

211	214 { "adey", OP_DIRECT \| OP_PAGE2, 2, 0xd9, 3, 3, CHG_NZVC, cpu9s12x, 0 },

212 { "asr", OP_IND16, 3, 0x77, 4, 4, CHG_NZVC, cpu6811\|cpu6812 },	215 { "adey", OP_IND16 \| OP_PAGE2, 3, 0xf9, 3, 3, CHG_NZVC, cpu9s12x, 0 },

213 { "asr", OP_IX, 2, 0x67, 6, 6, CHG_NZVC, cpu6811 },	216 { "adey", OP_IDX \| OP_PAGE2, 2, 0xe9, 3, 3, CHG_NZVC, cpu9s12x, 0 },

214 { "asr", OP_IY \| OP_PAGE2, 3, 0x67, 7, 7, CHG_NZVC, cpu6811 },	217 { "adey", OP_IDX_1 \| OP_PAGE2, 3, 0xe9, 3, 3, CHG_NZVC, cpu9s12x, 0 },

215 { "asr", OP_IDX, 2, 0x67, 3, 3, CHG_NZVC, cpu6812 },	218 { "adey", OP_IDX_2 \| OP_PAGE2, 4, 0xe9, 4, 4, CHG_NZVC, cpu9s12x, 0 },

216 { "asr", OP_IDX_1, 3, 0x67, 4, 4, CHG_NZVC, cpu6812 },	219 { "adey", OP_D_IDX \| OP_PAGE2, 2, 0xe9, 6, 6, CHG_NZVC, cpu9s12x, 0 },

217 { "asr", OP_IDX_2, 4, 0x67, 5, 5, CHG_NZVC, cpu6812 },	220 { "adey", OP_D_IDX_2 \| OP_PAGE2, 4, 0xe9, 6, 6, CHG_NZVC, cpu9s12x, 0 },

218 { "asr", OP_D_IDX, 2, 0x67, 6, 6, CHG_NZVC, cpu6812 },	221

219 { "asr", OP_D_IDX_2, 4, 0x67, 6, 6, CHG_NZVC, cpu6812 },	222 { "anda", OP_IMM8, 2, 0x84, 1, 1, CLR_V_CHG_NZ, cpu6811\|cpu6812\|cpu 9s12x, 0 },

220	223 { "anda", OP_DIRECT, 2, 0x94, 3, 3, CLR_V_CHG_NZ, cpu6811\|cpu6812\|cpu 9s12x, 0 },

221 { "asra", OP_NONE, 1, 0x47, 1, 1, CHG_NZVC, cpu6811\|cpu6812 },	224 { "anda", OP_IND16, 3, 0xb4, 3, 3, CLR_V_CHG_NZ, cpu6811\|cpu6812\|cpu 9s12x, 0 },

222 { "asrb", OP_NONE, 1, 0x57, 1, 1, CHG_NZVC, cpu6811\|cpu6812 },	225 { "anda", OP_IX, 2, 0xa4, 4, 4, CLR_V_CHG_NZ, cpu6811, 0 },

223	226 { "anda", OP_IY \| OP_PAGE2, 3, 0xa4, 5, 5, CLR_V_CHG_NZ, cpu6811, 0 },

224 { "bcc", OP_JUMP_REL, 2, 0x24, 1, 3, CHG_NONE, cpu6811\|cpu6812 },	227 { "anda", OP_IDX, 2, 0xa4, 3, 3, CLR_V_CHG_NZ, cpu6812\|cpu9s12x, 0 },

225	228 { "anda", OP_IDX_1, 3, 0xa4, 3, 3, CLR_V_CHG_NZ, cpu6812\|cpu9s12x, 0 },

226 { "bclr", OP_BITMASK\|OP_DIRECT, 3, 0x15, 6, 6, CLR_V_CHG_NZ, cpu6811 },	229 { "anda", OP_IDX_2, 4, 0xa4, 4, 4, CLR_V_CHG_NZ, cpu6812\|cpu9s12x, 0 },

227 { "bclr", OP_BITMASK\|OP_IX, 3, 0x1d, 7, 7, CLR_V_CHG_NZ, cpu6811 },	230 { "anda", OP_D_IDX, 2, 0xa4, 6, 6, CLR_V_CHG_NZ, cpu6812\|cpu9s12x, 0 },

228 { "bclr", OP_BITMASK\|OP_IY\|OP_PAGE2, 4, 0x1d, 8, 8, CLR_V_CHG_NZ, cpu6811},	231 { "anda", OP_D_IDX_2, 4, 0xa4, 6, 6, CLR_V_CHG_NZ, cpu6812\|cpu9s12x, 0 },

229 { "bclr", OP_BITMASK\|OP_DIRECT, 3, 0x4d, 4, 4, CLR_V_CHG_NZ, cpu6812 },	232

230 { "bclr", OP_BITMASK\|OP_IND16, 4, 0x1d, 4, 4, CLR_V_CHG_NZ, cpu6812 },	233 { "andb", OP_IMM8, 2, 0xc4, 1, 1, CLR_V_CHG_NZ, cpu6811\|cpu6812\|cpu 9s12x, 0 },

231 { "bclr", OP_BITMASK\|OP_IDX, 3, 0x0d, 4, 4, CLR_V_CHG_NZ, cpu6812 },	234 { "andb", OP_DIRECT, 2, 0xd4, 3, 3, CLR_V_CHG_NZ, cpu6811\|cpu6812\|cpu 9s12x, 0 },

232 { "bclr", OP_BITMASK\|OP_IDX_1, 4, 0x0d, 4, 4, CLR_V_CHG_NZ, cpu6812 },	235 { "andb", OP_IND16, 3, 0xf4, 3, 3, CLR_V_CHG_NZ, cpu6811\|cpu6812\|cpu 9s12x, 0 },

233 { "bclr", OP_BITMASK\|OP_IDX_2, 5, 0x0d, 6, 6, CLR_V_CHG_NZ, cpu6812 },	236 { "andb", OP_IX, 2, 0xe4, 4, 4, CLR_V_CHG_NZ, cpu6811, 0 },

234	237 { "andb", OP_IY \| OP_PAGE2, 3, 0xe4, 5, 5, CLR_V_CHG_NZ, cpu6811, 0 },

235 { "bcs", OP_JUMP_REL, 2, 0x25, 1, 3, CHG_NONE, cpu6811 \| cpu6812 },	238 { "andb", OP_IDX, 2, 0xe4, 3, 3, CLR_V_CHG_NZ, cpu6812\|cpu9s12x, 0 },

236 { "beq", OP_JUMP_REL, 2, 0x27, 1, 3, CHG_NONE, cpu6811 \| cpu6812 },	239 { "andb", OP_IDX_1, 3, 0xe4, 3, 3, CLR_V_CHG_NZ, cpu6812\|cpu9s12x, 0 },

237 { "bge", OP_JUMP_REL, 2, 0x2c, 1, 3, CHG_NONE, cpu6811 \| cpu6812 },	240 { "andb", OP_IDX_2, 4, 0xe4, 4, 4, CLR_V_CHG_NZ, cpu6812\|cpu9s12x, 0 },

238	241 { "andb", OP_D_IDX, 2, 0xe4, 6, 6, CLR_V_CHG_NZ, cpu6812\|cpu9s12x, 0 },

239 { "bgnd", OP_NONE, 1, 0x00, 5, 5, CHG_NONE, cpu6811 \| cpu6812 },	242 { "andb", OP_D_IDX_2, 4, 0xe4, 6, 6, CLR_V_CHG_NZ, cpu6812\|cpu9s12x, 0 },

240	243

241 { "bgt", OP_JUMP_REL, 2, 0x2e, 1, 3, CHG_NONE, cpu6811 \| cpu6812 },	244 { "andcc", OP_IMM8, 2, 0x10, 1, 1, CHG_ALL, cpu6812\|cpu9s12x, 0 } ,

242 { "bhi", OP_JUMP_REL, 2, 0x22, 1, 3, CHG_NONE, cpu6811 \| cpu6812 },	245

243 { "bhs", OP_JUMP_REL, 2, 0x24, 1, 3, CHG_NONE, cpu6811 \| cpu6812 },	246 { "andx", OP_IMM16 \| OP_PAGE2, 2, 0x84, 1, 1, CLR_V_CHG_NZ, cpu9s12 x, 0 },

	247 { "andx", OP_DIRECT \| OP_PAGE2, 2, 0x94, 3, 3, CLR_V_CHG_NZ, cpu9s12x , 0 },

	248 { "andx", OP_IND16 \| OP_PAGE2, 3, 0xb4, 3, 3, CLR_V_CHG_NZ, cpu9s12x , 0 },

	249 { "andx", OP_IDX \| OP_PAGE2, 2, 0xa4, 3, 3, CLR_V_CHG_NZ, cpu9s1 2x, 0 },

	250 { "andx", OP_IDX_1 \| OP_PAGE2, 3, 0xa4, 3, 3, CLR_V_CHG_NZ, cpu9s1 2x, 0 },

	251 { "andx", OP_IDX_2 \| OP_PAGE2, 4, 0xa4, 4, 4, CLR_V_CHG_NZ, cpu9s1 2x, 0 },

	252 { "andx", OP_D_IDX \| OP_PAGE2, 2, 0xa4, 6, 6, CLR_V_CHG_NZ, cpu9s1 2x, 0 },

	253 { "andx", OP_D_IDX_2 \| OP_PAGE2, 4, 0xa4, 6, 6, CLR_V_CHG_NZ, cpu9s1 2x, 0 },

	254

	255 { "andy", OP_IMM16 \| OP_PAGE2, 2, 0xc4, 1, 1, CLR_V_CHG_NZ, cpu9s12 x, 0 },

	256 { "andy", OP_DIRECT \| OP_PAGE2, 2, 0xd4, 3, 3, CLR_V_CHG_NZ, cpu9s12x , 0 },

	257 { "andy", OP_IND16 \| OP_PAGE2, 3, 0xf4, 3, 3, CLR_V_CHG_NZ, cpu9s12x , 0 },

	258 { "andy", OP_IDX \| OP_PAGE2, 2, 0xe4, 3, 3, CLR_V_CHG_NZ, cpu9s1 2x, 0 },

	259 { "andy", OP_IDX_1 \| OP_PAGE2, 3, 0xe4, 3, 3, CLR_V_CHG_NZ, cpu9s1 2x, 0 },

	260 { "andy", OP_IDX_2 \| OP_PAGE2, 4, 0xe4, 4, 4, CLR_V_CHG_NZ, cpu9s1 2x, 0 },

	261 { "andy", OP_D_IDX \| OP_PAGE2, 2, 0xe4, 6, 6, CLR_V_CHG_NZ, cpu9s1 2x, 0 },

	262 { "andy", OP_D_IDX_2 \| OP_PAGE2, 4, 0xe4, 6, 6, CLR_V_CHG_NZ, cpu9s1 2x, 0 },

	263

	264 { "asl", OP_IND16, 3, 0x78, 4, 4, CHG_NZVC, cpu6811\|cpu6812\|cpu9s 12x, 0 },

	265 { "asl", OP_IX, 2, 0x68, 6, 6, CHG_NZVC, cpu6811, 0 },

	266 { "asl", OP_IY \| OP_PAGE2, 3, 0x68, 7, 7, CHG_NZVC, cpu6811, 0 },

	267 { "asl", OP_IDX, 2, 0x68, 3, 3, CHG_NZVC, cpu6812\|cpu9s12x, 0 } ,

	268 { "asl", OP_IDX_1, 3, 0x68, 4, 4, CHG_NZVC, cpu6812\|cpu9s12x, 0 } ,

	269 { "asl", OP_IDX_2, 4, 0x68, 5, 5, CHG_NZVC, cpu6812\|cpu9s12x, 0 } ,

	270 { "asl", OP_D_IDX, 2, 0x68, 6, 6, CHG_NZVC, cpu6812\|cpu9s12x, 0 } ,

	271 { "asl", OP_D_IDX_2, 4, 0x68, 6, 6, CHG_NZVC, cpu6812\|cpu9s12x, 0 } ,

	272

	273 { "asla", OP_NONE, 1, 0x48, 1, 1, CHG_NZVC, cpu6811\|cpu6812\|cpu9s 12x, 0 },

	274 { "aslb", OP_NONE, 1, 0x58, 1, 1, CHG_NZVC, cpu6811\|cpu6812\|cpu9s 12x, 0 },

	275 { "asld", OP_NONE, 1, 0x05, 3, 3, CHG_NZVC, cpu6811, 0 },

	276 { "asld", OP_NONE, 1, 0x59, 1, 1, CHG_NZVC, cpu6812\|cpu9s12x, 0 } ,

	277

	278 { "aslw", OP_IND16 \| OP_PAGE2, 3, 0x78, 4, 4, CHG_NZVC, cpu9s12x, 0 },

	279 { "aslw", OP_IDX \| OP_PAGE2, 2, 0x68, 3, 3, CHG_NZVC, cpu9s12x, 0 },

	280 { "aslw", OP_IDX_1 \| OP_PAGE2, 3, 0x68, 4, 4, CHG_NZVC, cpu9s12x, 0 },

	281 { "aslw", OP_IDX_2 \| OP_PAGE2, 4, 0x68, 5, 5, CHG_NZVC, cpu9s12x, 0 },

	282 { "aslw", OP_D_IDX \| OP_PAGE2, 2, 0x68, 6, 6, CHG_NZVC, cpu9s12x, 0 },

	283 { "aslw", OP_D_IDX_2 \| OP_PAGE2, 4, 0x68, 6, 6, CHG_NZVC, cpu9s12x, 0 },

	284

	285 { "aslx", OP_NONE \| OP_PAGE2, 1, 0x48, 1, 1, CHG_NZVC, cpu9s12x, 0 },

	286

	287 { "asly", OP_NONE \| OP_PAGE2, 1, 0x58, 1, 1, CHG_NZVC, cpu9s12x, 0 },

	288

	289 { "asr", OP_IND16, 3, 0x77, 4, 4, CHG_NZVC, cpu6811\|cpu6812\|cpu9s 12x, 0 },

	290 { "asr", OP_IX, 2, 0x67, 6, 6, CHG_NZVC, cpu6811, 0 },

	291 { "asr", OP_IY \| OP_PAGE2, 3, 0x67, 7, 7, CHG_NZVC, cpu6811, 0 },

	292 { "asr", OP_IDX, 2, 0x67, 3, 3, CHG_NZVC, cpu6812\|cpu9s12x, 0 } ,

	293 { "asr", OP_IDX_1, 3, 0x67, 4, 4, CHG_NZVC, cpu6812\|cpu9s12x, 0 } ,

	294 { "asr", OP_IDX_2, 4, 0x67, 5, 5, CHG_NZVC, cpu6812\|cpu9s12x, 0 } ,

	295 { "asr", OP_D_IDX, 2, 0x67, 6, 6, CHG_NZVC, cpu6812\|cpu9s12x, 0 } ,

	296 { "asr", OP_D_IDX_2, 4, 0x67, 6, 6, CHG_NZVC, cpu6812\|cpu9s12x, 0 } ,

	297

	298 { "asra", OP_NONE, 1, 0x47, 1, 1, CHG_NZVC, cpu6811\|cpu6812\|cpu9s 12x, 0 },

	299 { "asrb", OP_NONE, 1, 0x57, 1, 1, CHG_NZVC, cpu6811\|cpu6812\|cpu9s 12x, 0 },

	300

	301 { "asrw", OP_IND16 \| OP_PAGE2, 3, 0x77, 4, 4, CHG_NZVC, cpu9s12x, 0 },

	302 { "asrw", OP_IDX \| OP_PAGE2, 2, 0x67, 3, 3, CHG_NZVC, cpu9s12x, 0 },

	303 { "asrw", OP_IDX_1 \| OP_PAGE2, 3, 0x67, 4, 4, CHG_NZVC, cpu9s12x, 0 },

	304 { "asrw", OP_IDX_2 \| OP_PAGE2, 4, 0x67, 5, 5, CHG_NZVC, cpu9s12x, 0 },

	305 { "asrw", OP_D_IDX \| OP_PAGE2, 2, 0x67, 6, 6, CHG_NZVC, cpu9s12x, 0 },

	306 { "asrw", OP_D_IDX_2 \| OP_PAGE2, 4, 0x67, 6, 6, CHG_NZVC, cpu9s12x, 0 },

	307

	308 { "asrx", OP_NONE \| OP_PAGE2, 1, 0x47, 1, 1, CHG_NZVC, cpu9s12x, 0 },

	309

	310 { "asry", OP_NONE \| OP_PAGE2, 1, 0x57, 1, 1, CHG_NZVC, cpu9s12x, 0 },

	311

	312 { "bcc", OP_JUMP_REL, 2, 0x24, 1, 3, CHG_NONE, cpu6811\|cpu6812\|cpu9s 12x, 0 },

	313

	314 { "bclr", OP_BITMASK\|OP_DIRECT, 3, 0x15, 6, 6, CLR_V_CHG_NZ, cpu6811, 0 },

	315 { "bclr", OP_BITMASK\|OP_IX, 3, 0x1d, 7, 7, CLR_V_CHG_NZ, cpu6811, 0 } ,

	316 { "bclr", OP_BITMASK\|OP_IY\|OP_PAGE2, 4, 0x1d, 8, 8, CLR_V_CHG_NZ, cpu6811, 0 } ,

	317 { "bclr", OP_BITMASK\|OP_DIRECT, 3, 0x4d, 4, 4, CLR_V_CHG_NZ, cpu6812\|cpu9 s12x, 0 },

	318 { "bclr", OP_BITMASK\|OP_IND16, 4, 0x1d, 4, 4, CLR_V_CHG_NZ, cpu6812\|cpu9 s12x, 0 },

	319 { "bclr", OP_BITMASK\|OP_IDX, 3, 0x0d, 4, 4, CLR_V_CHG_NZ, cpu6812\|cpu9 s12x, 0 },

	320 { "bclr", OP_BITMASK\|OP_IDX_1, 4, 0x0d, 4, 4, CLR_V_CHG_NZ, cpu6812\|cpu9 s12x, 0 },

	321 { "bclr", OP_BITMASK\|OP_IDX_2, 5, 0x0d, 6, 6, CLR_V_CHG_NZ, cpu6812\|cpu9 s12x, 0 },

	322

	323 { "bcs", OP_JUMP_REL, 2, 0x25, 1, 3, CHG_NONE, cpu6811 \| cpu6812\|cpu9 s12x, 0 },

	324 { "beq", OP_JUMP_REL, 2, 0x27, 1, 3, CHG_NONE, cpu6811 \| cpu6812\|cpu9 s12x, 0 },

	325 { "bge", OP_JUMP_REL, 2, 0x2c, 1, 3, CHG_NONE, cpu6811 \| cpu6812\|cpu9 s12x, 0 },

	326

	327 { "bgnd", OP_NONE, 1, 0x00, 5, 5, CHG_NONE, cpu6811 \| cpu6812\|cpu9 s12x, 0 },

	328

	329 { "bgt", OP_JUMP_REL, 2, 0x2e, 1, 3, CHG_NONE, cpu6811 \| cpu6812\|cpu9 s12x, 0 },

	330 { "bhi", OP_JUMP_REL, 2, 0x22, 1, 3, CHG_NONE, cpu6811 \| cpu6812\|cpu9 s12x, 0 },

	331 { "bhs", OP_JUMP_REL, 2, 0x24, 1, 3, CHG_NONE, cpu6811 \| cpu6812\|cpu9 s12x, 0 },

244	332

245 { "bita", OP_IMM8, 2, 0x85, 1, 1, CLR_V_CHG_NZ, cpu6811\|cpu6812 },	333 { "bita", OP_IMM8, 2, 0x85, 1, 1, CLR_V_CHG_NZ, cpu6811\|cpu6812\|cpu 9s12x, 0 },

246 { "bita", OP_DIRECT, 2, 0x95, 3, 3, CLR_V_CHG_NZ, cpu6811\|cpu6812 },	334 { "bita", OP_DIRECT, 2, 0x95, 3, 3, CLR_V_CHG_NZ, cpu6811\|cpu6812\|cpu 9s12x, 0 },

247 { "bita", OP_IND16, 3, 0xb5, 3, 3, CLR_V_CHG_NZ, cpu6811\|cpu6812 },	335 { "bita", OP_IND16, 3, 0xb5, 3, 3, CLR_V_CHG_NZ, cpu6811\|cpu6812\|cpu 9s12x, 0 },

248 { "bita", OP_IX, 2, 0xa5, 4, 4, CLR_V_CHG_NZ, cpu6811 },	336 { "bita", OP_IX, 2, 0xa5, 4, 4, CLR_V_CHG_NZ, cpu6811, 0 },

249 { "bita", OP_IY \| OP_PAGE2, 3, 0xa5, 5, 5, CLR_V_CHG_NZ, cpu6811 },	337 { "bita", OP_IY \| OP_PAGE2, 3, 0xa5, 5, 5, CLR_V_CHG_NZ, cpu6811, 0 },

250 { "bita", OP_IDX, 2, 0xa5, 3, 3, CLR_V_CHG_NZ, cpu6812 },	338 { "bita", OP_IDX, 2, 0xa5, 3, 3, CLR_V_CHG_NZ, cpu6812\|cpu9s12x, 0 },

251 { "bita", OP_IDX_1, 3, 0xa5, 3, 3, CLR_V_CHG_NZ, cpu6812 },	339 { "bita", OP_IDX_1, 3, 0xa5, 3, 3, CLR_V_CHG_NZ, cpu6812\|cpu9s12x, 0 },

252 { "bita", OP_IDX_2, 4, 0xa5, 4, 4, CLR_V_CHG_NZ, cpu6812 },	340 { "bita", OP_IDX_2, 4, 0xa5, 4, 4, CLR_V_CHG_NZ, cpu6812\|cpu9s12x, 0 },

253 { "bita", OP_D_IDX, 2, 0xa5, 6, 6, CLR_V_CHG_NZ, cpu6812 },	341 { "bita", OP_D_IDX, 2, 0xa5, 6, 6, CLR_V_CHG_NZ, cpu6812\|cpu9s12x, 0 },

254 { "bita", OP_D_IDX_2, 4, 0xa5, 6, 6, CLR_V_CHG_NZ, cpu6812 },	342 { "bita", OP_D_IDX_2, 4, 0xa5, 6, 6, CLR_V_CHG_NZ, cpu6812\|cpu9s12x, 0 },

255	343

256 { "bitb", OP_IMM8, 2, 0xc5, 1, 1, CLR_V_CHG_NZ, cpu6811\|cpu6812 },	344 { "bitb", OP_IMM8, 2, 0xc5, 1, 1, CLR_V_CHG_NZ, cpu6811\|cpu6812\|cpu 9s12x, 0 },

257 { "bitb", OP_DIRECT, 2, 0xd5, 3, 3, CLR_V_CHG_NZ, cpu6811\|cpu6812 },	345 { "bitb", OP_DIRECT, 2, 0xd5, 3, 3, CLR_V_CHG_NZ, cpu6811\|cpu6812\|cpu 9s12x, 0 },

258 { "bitb", OP_IND16, 3, 0xf5, 3, 3, CLR_V_CHG_NZ, cpu6811\|cpu6812 },	346 { "bitb", OP_IND16, 3, 0xf5, 3, 3, CLR_V_CHG_NZ, cpu6811\|cpu6812\|cpu 9s12x, 0 },

259 { "bitb", OP_IX, 2, 0xe5, 4, 4, CLR_V_CHG_NZ, cpu6811 },	347 { "bitb", OP_IX, 2, 0xe5, 4, 4, CLR_V_CHG_NZ, cpu6811, 0 },

260 { "bitb", OP_IY \| OP_PAGE2, 3, 0xe5, 5, 5, CLR_V_CHG_NZ, cpu6811 },	348 { "bitb", OP_IY \| OP_PAGE2, 3, 0xe5, 5, 5, CLR_V_CHG_NZ, cpu6811, 0 },

261 { "bitb", OP_IDX, 2, 0xe5, 3, 3, CLR_V_CHG_NZ, cpu6812 },	349 { "bitb", OP_IDX, 2, 0xe5, 3, 3, CLR_V_CHG_NZ, cpu6812\|cpu9s12x, 0 },

262 { "bitb", OP_IDX_1, 3, 0xe5, 3, 3, CLR_V_CHG_NZ, cpu6812 },	350 { "bitb", OP_IDX_1, 3, 0xe5, 3, 3, CLR_V_CHG_NZ, cpu6812\|cpu9s12x, 0 },

263 { "bitb", OP_IDX_2, 4, 0xe5, 4, 4, CLR_V_CHG_NZ, cpu6812 },	351 { "bitb", OP_IDX_2, 4, 0xe5, 4, 4, CLR_V_CHG_NZ, cpu6812\|cpu9s12x, 0 },

264 { "bitb", OP_D_IDX, 2, 0xe5, 6, 6, CLR_V_CHG_NZ, cpu6812 },	352 { "bitb", OP_D_IDX, 2, 0xe5, 6, 6, CLR_V_CHG_NZ, cpu6812\|cpu9s12x, 0 },

265 { "bitb", OP_D_IDX_2, 4, 0xe5, 6, 6, CLR_V_CHG_NZ, cpu6812 },	353 { "bitb", OP_D_IDX_2, 4, 0xe5, 6, 6, CLR_V_CHG_NZ, cpu6812\|cpu9s12x, 0 },

266	354

267 { "ble", OP_JUMP_REL, 2, 0x2f, 1, 3, CHG_NONE, cpu6811 \| cpu6812 },	355 { "bitx", OP_IMM16 \| OP_PAGE2, 2, 0x85, 1, 1, CLR_V_CHG_NZ, cpu9s12 x, 0 },

268 { "blo", OP_JUMP_REL, 2, 0x25, 1, 3, CHG_NONE, cpu6811 \| cpu6812 },	356 { "bitx", OP_DIRECT \| OP_PAGE2, 2, 0x95, 3, 3, CLR_V_CHG_NZ, cpu9s12x , 0 },

269 { "bls", OP_JUMP_REL, 2, 0x23, 1, 3, CHG_NONE, cpu6811 \| cpu6812 },	357 { "bitx", OP_IND16 \| OP_PAGE2, 3, 0xb5, 3, 3, CLR_V_CHG_NZ, cpu9s12x , 0 },

270 { "blt", OP_JUMP_REL, 2, 0x2d, 1, 3, CHG_NONE, cpu6811 \| cpu6812 },	358 { "bitx", OP_IDX \| OP_PAGE2, 2, 0xa5, 3, 3, CLR_V_CHG_NZ, cpu9s1 2x, 0 },

271 { "bmi", OP_JUMP_REL, 2, 0x2b, 1, 3, CHG_NONE, cpu6811 \| cpu6812 },	359 { "bitx", OP_IDX_1 \| OP_PAGE2, 3, 0xa5, 3, 3, CLR_V_CHG_NZ, cpu9s1 2x, 0 },

272 { "bne", OP_JUMP_REL, 2, 0x26, 1, 3, CHG_NONE, cpu6811 \| cpu6812 },	360 { "bitx", OP_IDX_2 \| OP_PAGE2, 4, 0xa5, 4, 4, CLR_V_CHG_NZ, cpu9s1 2x, 0 },

273 { "bpl", OP_JUMP_REL, 2, 0x2a, 1, 3, CHG_NONE, cpu6811 \| cpu6812 },	361 { "bitx", OP_D_IDX \| OP_PAGE2, 2, 0xa5, 6, 6, CLR_V_CHG_NZ, cpu9s1 2x, 0 },

274 { "bra", OP_JUMP_REL, 2, 0x20, 1, 3, CHG_NONE, cpu6811 \| cpu6812 },	362 { "bitx", OP_D_IDX_2 \| OP_PAGE2, 4, 0xa5, 6, 6, CLR_V_CHG_NZ, cpu9s1 2x, 0 },

	363

	364 { "bity", OP_IMM16 \| OP_PAGE2, 2, 0xc5, 1, 1, CLR_V_CHG_NZ, cpu9s12 x, 0 },

	365 { "bity", OP_DIRECT \| OP_PAGE2, 2, 0xd5, 3, 3, CLR_V_CHG_NZ, cpu9s12x , 0 },

	366 { "bity", OP_IND16 \| OP_PAGE2, 3, 0xf5, 3, 3, CLR_V_CHG_NZ, cpu9s12x , 0 },

	367 { "bity", OP_IDX \| OP_PAGE2, 2, 0xe5, 3, 3, CLR_V_CHG_NZ, cpu9s1 2x, 0 },

	368 { "bity", OP_IDX_1 \| OP_PAGE2, 3, 0xe5, 3, 3, CLR_V_CHG_NZ, cpu9s1 2x, 0 },

	369 { "bity", OP_IDX_2 \| OP_PAGE2, 4, 0xe5, 4, 4, CLR_V_CHG_NZ, cpu9s1 2x, 0 },

	370 { "bity", OP_D_IDX \| OP_PAGE2, 2, 0xe5, 6, 6, CLR_V_CHG_NZ, cpu9s1 2x, 0 },

	371 { "bity", OP_D_IDX_2 \| OP_PAGE2, 4, 0xe5, 6, 6, CLR_V_CHG_NZ, cpu9s1 2x, 0 },

	372

	373 { "ble", OP_JUMP_REL, 2, 0x2f, 1, 3, CHG_NONE, cpu6811 \| cpu6812\|cpu9 s12x, 0 },

	374 { "blo", OP_JUMP_REL, 2, 0x25, 1, 3, CHG_NONE, cpu6811 \| cpu6812\|cpu9 s12x, 0 },

	375 { "bls", OP_JUMP_REL, 2, 0x23, 1, 3, CHG_NONE, cpu6811 \| cpu6812\|cpu9 s12x, 0 },

	376 { "blt", OP_JUMP_REL, 2, 0x2d, 1, 3, CHG_NONE, cpu6811 \| cpu6812\|cpu9 s12x, 0 },

	377 { "bmi", OP_JUMP_REL, 2, 0x2b, 1, 3, CHG_NONE, cpu6811 \| cpu6812\|cpu9 s12x, 0 },

	378 { "bne", OP_JUMP_REL, 2, 0x26, 1, 3, CHG_NONE, cpu6811 \| cpu6812\|cpu9 s12x, 0 },

	379 { "bpl", OP_JUMP_REL, 2, 0x2a, 1, 3, CHG_NONE, cpu6811 \| cpu6812\|cpu9 s12x, 0 },

	380 { "bra", OP_JUMP_REL, 2, 0x20, 1, 3, CHG_NONE, cpu6811 \| cpu6812\|cpu9 s12x, 0 },

275	381

276 { "brclr", OP_BITMASK \| OP_JUMP_REL	382 { "brclr", OP_BITMASK \| OP_JUMP_REL

277 \| OP_DIRECT, 4, 0x13, 6, 6, CHG_NONE, cpu6811 },	383 \| OP_DIRECT, 4, 0x13, 6, 6, CHG_NONE, cpu6811, 0 },

278 { "brclr", OP_BITMASK \| OP_JUMP_REL	384 { "brclr", OP_BITMASK \| OP_JUMP_REL

279 \| OP_IX, 4, 0x1f, 7, 7, CHG_NONE, cpu6811 },	385 \| OP_IX, 4, 0x1f, 7, 7, CHG_NONE, cpu6811, 0 },

280 { "brclr", OP_BITMASK \| OP_JUMP_REL	386 { "brclr", OP_BITMASK \| OP_JUMP_REL

281 \| OP_IY \| OP_PAGE2, 5, 0x1f, 8, 8, CHG_NONE, cpu6811 },	387 \| OP_IY \| OP_PAGE2, 5, 0x1f, 8, 8, CHG_NONE, cpu6811, 0 },

282 { "brclr", OP_BITMASK \| OP_JUMP_REL	388 { "brclr", OP_BITMASK \| OP_JUMP_REL

283 \| OP_DIRECT, 4, 0x4f, 4, 4, CHG_NONE, cpu6812 },	389 \| OP_DIRECT, 4, 0x4f, 4, 4, CHG_NONE, cpu6812\|cpu9s12x, 0 },

284 { "brclr", OP_BITMASK \| OP_JUMP_REL	390 { "brclr", OP_BITMASK \| OP_JUMP_REL

285 \| OP_IND16, 5, 0x1f, 5, 5, CHG_NONE, cpu6812 },	391 \| OP_IND16, 5, 0x1f, 5, 5, CHG_NONE, cpu6812\|cpu9s12x, 0 },

286 { "brclr", OP_BITMASK \| OP_JUMP_REL	392 { "brclr", OP_BITMASK \| OP_JUMP_REL

287 \| OP_IDX, 4, 0x0f, 4, 4, CHG_NONE, cpu6812 },	393 \| OP_IDX, 4, 0x0f, 4, 4, CHG_NONE, cpu6812\|cpu9s12x, 0 },

288 { "brclr", OP_BITMASK \| OP_JUMP_REL	394 { "brclr", OP_BITMASK \| OP_JUMP_REL

289 \| OP_IDX_1, 5, 0x0f, 6, 6, CHG_NONE, cpu6812 },	395 \| OP_IDX_1, 5, 0x0f, 6, 6, CHG_NONE, cpu6812\|cpu9s12x, 0 },

290 { "brclr", OP_BITMASK	396 { "brclr", OP_BITMASK

291 \| OP_JUMP_REL	397 \| OP_JUMP_REL

292 \| OP_IDX_2, 6, 0x0f, 8, 8, CHG_NONE, cpu6812 },	398 \| OP_IDX_2, 6, 0x0f, 8, 8, CHG_NONE, cpu6812\|cpu9s12x, 0 },

293	399

294 { "brn", OP_JUMP_REL, 2, 0x21, 1, 3, CHG_NONE, cpu6811\|cpu6812 },	400 { "brn", OP_JUMP_REL, 2, 0x21, 1, 3, CHG_NONE, cpu6811\|cpu6812\|cpu9 s12x, 0 },

295	401

296 { "brset", OP_BITMASK \| OP_JUMP_REL	402 { "brset", OP_BITMASK \| OP_JUMP_REL

297 \| OP_DIRECT, 4, 0x12, 6, 6, CHG_NONE, cpu6811 },	403 \| OP_DIRECT, 4, 0x12, 6, 6, CHG_NONE, cpu6811, 0 },

298 { "brset", OP_BITMASK	404 { "brset", OP_BITMASK

299 \| OP_JUMP_REL	405 \| OP_JUMP_REL

300 \| OP_IX, 4, 0x1e, 7, 7, CHG_NONE, cpu6811 },	406 \| OP_IX, 4, 0x1e, 7, 7, CHG_NONE, cpu6811, 0 },

301 { "brset", OP_BITMASK \| OP_JUMP_REL	407 { "brset", OP_BITMASK \| OP_JUMP_REL

302 \| OP_IY \| OP_PAGE2, 5, 0x1e, 8, 8, CHG_NONE, cpu6811 },	408 \| OP_IY \| OP_PAGE2, 5, 0x1e, 8, 8, CHG_NONE, cpu6811, 0 },

303 { "brset", OP_BITMASK \| OP_JUMP_REL	409 { "brset", OP_BITMASK \| OP_JUMP_REL

304 \| OP_DIRECT, 4, 0x4e, 4, 4, CHG_NONE, cpu6812 },	410 \| OP_DIRECT, 4, 0x4e, 4, 4, CHG_NONE, cpu6812\|cpu9s12x, 0 },

305 { "brset", OP_BITMASK \| OP_JUMP_REL	411 { "brset", OP_BITMASK \| OP_JUMP_REL

306 \| OP_IND16, 5, 0x1e, 5, 5, CHG_NONE, cpu6812 },	412 \| OP_IND16, 5, 0x1e, 5, 5, CHG_NONE, cpu6812\|cpu9s12x, 0 },

307 { "brset", OP_BITMASK \| OP_JUMP_REL	413 { "brset", OP_BITMASK \| OP_JUMP_REL

308 \| OP_IDX, 4, 0x0e, 4, 4, CHG_NONE, cpu6812 },	414 \| OP_IDX, 4, 0x0e, 4, 4, CHG_NONE, cpu6812\|cpu9s12x, 0 },

309 { "brset", OP_BITMASK \| OP_JUMP_REL	415 { "brset", OP_BITMASK \| OP_JUMP_REL

310 \| OP_IDX_1, 5, 0x0e, 6, 6, CHG_NONE, cpu6812 },	416 \| OP_IDX_1, 5, 0x0e, 6, 6, CHG_NONE, cpu6812\|cpu9s12x, 0 },

311 { "brset", OP_BITMASK \| OP_JUMP_REL	417 { "brset", OP_BITMASK \| OP_JUMP_REL

312 \| OP_IDX_2, 6, 0x0e, 8, 8, CHG_NONE, cpu6812 },	418 \| OP_IDX_2, 6, 0x0e, 8, 8, CHG_NONE, cpu6812\|cpu9s12x, 0 },

313	419

314	420

315 { "bset", OP_BITMASK \| OP_DIRECT, 3, 0x14, 6, 6, CLR_V_CHG_NZ, cpu6811 },	421 { "bset", OP_BITMASK \| OP_DIRECT, 3, 0x14, 6, 6, CLR_V_CHG_NZ, cpu6811, 0 },

316 { "bset", OP_BITMASK \| OP_IX, 3, 0x1c, 7, 7, CLR_V_CHG_NZ, cpu6811 },	422 { "bset", OP_BITMASK \| OP_IX, 3, 0x1c, 7, 7, CLR_V_CHG_NZ, cpu6811, 0 },

317 { "bset", OP_BITMASK\|OP_IY\|OP_PAGE2, 4, 0x1c, 8, 8, CLR_V_CHG_NZ, cpu6811 },	423 { "bset", OP_BITMASK\|OP_IY\|OP_PAGE2, 4, 0x1c, 8, 8, CLR_V_CHG_NZ, cpu6811, 0 } ,

318 { "bset", OP_BITMASK\|OP_DIRECT, 3, 0x4c, 4, 4, CLR_V_CHG_NZ, cpu6812 },	424 { "bset", OP_BITMASK\|OP_DIRECT, 3, 0x4c, 4, 4, CLR_V_CHG_NZ, cpu6812\|cpu9 s12x, 0 },

319 { "bset", OP_BITMASK\|OP_IND16, 4, 0x1c, 4, 4, CLR_V_CHG_NZ, cpu6812 },	425 { "bset", OP_BITMASK\|OP_IND16, 4, 0x1c, 4, 4, CLR_V_CHG_NZ, cpu6812\|cpu9 s12x, 0 },

320 { "bset", OP_BITMASK\|OP_IDX, 3, 0x0c, 4, 4, CLR_V_CHG_NZ, cpu6812 },	426 { "bset", OP_BITMASK\|OP_IDX, 3, 0x0c, 4, 4, CLR_V_CHG_NZ, cpu6812\|cpu9 s12x, 0 },

321 { "bset", OP_BITMASK\|OP_IDX_1, 4, 0x0c, 4, 4, CLR_V_CHG_NZ, cpu6812 },	427 { "bset", OP_BITMASK\|OP_IDX_1, 4, 0x0c, 4, 4, CLR_V_CHG_NZ, cpu6812\|cpu9 s12x, 0 },

322 { "bset", OP_BITMASK\|OP_IDX_2, 5, 0x0c, 6, 6, CLR_V_CHG_NZ, cpu6812 },	428 { "bset", OP_BITMASK\|OP_IDX_2, 5, 0x0c, 6, 6, CLR_V_CHG_NZ, cpu6812\|cpu9 s12x, 0 },

323	429

324 { "bsr", OP_JUMP_REL, 2, 0x8d, 6, 6, CHG_NONE, cpu6811 },	430 { "bsr", OP_JUMP_REL, 2, 0x8d, 6, 6, CHG_NONE, cpu6811, 0 },

325 { "bsr", OP_JUMP_REL, 2, 0x07, 4, 4, CHG_NONE, cpu6812 },	431 { "bsr", OP_JUMP_REL, 2, 0x07, 4, 4, CHG_NONE, cpu6812\|cpu9s12x, 0 },

326	432

327 { "bvc", OP_JUMP_REL, 2, 0x28, 1, 3, CHG_NONE, cpu6811 \| cpu6812 },	433 { "btas", OP_BITMASK\|OP_DIRECT \| OP_PAGE2, 3, 0x35, 4, 4, CLR_V_CHG_NZ, c pu9s12x, 0 },

328 { "bvs", OP_JUMP_REL, 2, 0x29, 1, 3, CHG_NONE, cpu6811 \| cpu6812 },	434 { "btas", OP_BITMASK\|OP_IND16 \| OP_PAGE2, 4, 0x36, 4, 4, CLR_V_CHG_NZ, c pu9s12x, 0 },

	435 { "btas", OP_BITMASK\|OP_IDX \| OP_PAGE2, 3, 0x37, 4, 4, CLR_V_CHG_NZ, c pu9s12x, 0 },

	436 { "btas", OP_BITMASK\|OP_IDX_1 \| OP_PAGE2, 4, 0x37, 4, 4, CLR_V_CHG_NZ, c pu9s12x, 0 },

	437 { "btas", OP_BITMASK\|OP_IDX_2 \| OP_PAGE2, 5, 0x37, 6, 6, CLR_V_CHG_NZ, c pu9s12x, 0 },

	438

	439 { "bvc", OP_JUMP_REL, 2, 0x28, 1, 3, CHG_NONE, cpu6811 \| cpu6812\|cpu9 s12x, 0 },

	440 { "bvs", OP_JUMP_REL, 2, 0x29, 1, 3, CHG_NONE, cpu6811 \| cpu6812\|cpu9 s12x, 0 },

329	441

330 { "call", OP_IND16 \| OP_PAGE	442 { "call", OP_IND16 \| OP_PAGE

331 \| OP_BRANCH, 4, 0x4a, 8, 8, CHG_NONE, cpu6812 },	443 \| OP_BRANCH, 4, 0x4a, 8, 8, CHG_NONE, cpu6812\|cpu9s12x, 0 } ,

332 { "call", OP_IDX \| OP_PAGE	444 { "call", OP_IDX \| OP_PAGE

333 \| OP_BRANCH, 3, 0x4b, 8, 8, CHG_NONE, cpu6812 },	445 \| OP_BRANCH, 3, 0x4b, 8, 8, CHG_NONE, cpu6812\|cpu9s12x, 0 } ,

334 { "call", OP_IDX_1 \| OP_PAGE	446 { "call", OP_IDX_1 \| OP_PAGE

335 \| OP_BRANCH, 4, 0x4b, 8, 8, CHG_NONE, cpu6812 },	447 \| OP_BRANCH, 4, 0x4b, 8, 8, CHG_NONE, cpu6812\|cpu9s12x, 0 } ,

336 { "call", OP_IDX_2 \| OP_PAGE	448 { "call", OP_IDX_2 \| OP_PAGE

337 \| OP_BRANCH, 5, 0x4b, 9, 9, CHG_NONE, cpu6812 },	449 \| OP_BRANCH, 5, 0x4b, 9, 9, CHG_NONE, cpu6812\|cpu9s12x, 0 } ,

338 { "call", OP_D_IDX	450 { "call", OP_D_IDX

339 \| OP_BRANCH, 2, 0x4b, 10, 10, CHG_NONE, cpu6812 },	451 \| OP_BRANCH, 2, 0x4b, 10, 10, CHG_NONE, cpu6812\|cpu9s12x, 0 } ,

340 { "call", OP_D_IDX_2	452 { "call", OP_D_IDX_2

341 \| OP_BRANCH, 4, 0x4b, 10, 10, CHG_NONE, cpu6812 },	453 \| OP_BRANCH, 4, 0x4b, 10, 10, CHG_NONE, cpu6812\|cpu9s12x, 0 } ,

342	454

343 { "cba", OP_NONE, 1, 0x11, 2, 2, CHG_NZVC, cpu6811 },	455 { "cba", OP_NONE, 1, 0x11, 2, 2, CHG_NZVC, cpu6811, 0 },

344 { "cba", OP_NONE \| OP_PAGE2,2, 0x17, 2, 2, CHG_NZVC, cpu6812 },	456 { "cba", OP_NONE \| OP_PAGE2,2, 0x17, 2, 2, CHG_NZVC, cpu6812\|cpu9s12x, 0 } ,

345	457

346 { "clc", OP_NONE, 1, 0x0c, 2, 2, CLR_C, cpu6811 },	458 { "clc", OP_NONE, 1, 0x0c, 2, 2, CLR_C, cpu6811, 0 },

347 { "cli", OP_NONE, 1, 0x0e, 2, 2, CLR_I, cpu6811 },	459 { "cli", OP_NONE, 1, 0x0e, 2, 2, CLR_I, cpu6811, 0 },

348	460

349 { "clr", OP_IND16, 3, 0x7f, 6, 6, SET_Z_CLR_NVC, cpu6811 },	461 { "clr", OP_IND16, 3, 0x7f, 6, 6, SET_Z_CLR_NVC, cpu6811, 0 },

350 { "clr", OP_IX, 2, 0x6f, 6, 6, SET_Z_CLR_NVC, cpu6811 },	462 { "clr", OP_IX, 2, 0x6f, 6, 6, SET_Z_CLR_NVC, cpu6811, 0 },

351 { "clr", OP_IY \| OP_PAGE2, 3, 0x6f, 7, 7, SET_Z_CLR_NVC, cpu6811 },	463 { "clr", OP_IY \| OP_PAGE2, 3, 0x6f, 7, 7, SET_Z_CLR_NVC, cpu6811, 0 },

352 { "clr", OP_IND16, 3, 0x79, 3, 3, SET_Z_CLR_NVC, cpu6812 },	464 { "clr", OP_IND16, 3, 0x79, 3, 3, SET_Z_CLR_NVC, cpu6812\|cpu9s12x , 0 },

353 { "clr", OP_IDX, 2, 0x69, 2, 2, SET_Z_CLR_NVC, cpu6812 },	465 { "clr", OP_IDX, 2, 0x69, 2, 2, SET_Z_CLR_NVC, cpu6812\|cpu9s12x , 0 },

354 { "clr", OP_IDX_1, 3, 0x69, 3, 3, SET_Z_CLR_NVC, cpu6812 },	466 { "clr", OP_IDX_1, 3, 0x69, 3, 3, SET_Z_CLR_NVC, cpu6812\|cpu9s12x , 0 },

355 { "clr", OP_IDX_2, 4, 0x69, 4, 4, SET_Z_CLR_NVC, cpu6812 },	467 { "clr", OP_IDX_2, 4, 0x69, 4, 4, SET_Z_CLR_NVC, cpu6812\|cpu9s12x , 0 },

356 { "clr", OP_D_IDX, 2, 0x69, 5, 5, SET_Z_CLR_NVC, cpu6812 },	468 { "clr", OP_D_IDX, 2, 0x69, 5, 5, SET_Z_CLR_NVC, cpu6812\|cpu9s12x , 0 },

357 { "clr", OP_D_IDX_2, 4, 0x69, 5, 5, SET_Z_CLR_NVC, cpu6812 },	469 { "clr", OP_D_IDX_2, 4, 0x69, 5, 5, SET_Z_CLR_NVC, cpu6812\|cpu9s12x , 0 },

358	470

359 { "clra", OP_NONE, 1, 0x4f, 2, 2, SET_Z_CLR_NVC, cpu6811 },	471 { "clra", OP_NONE, 1, 0x4f, 2, 2, SET_Z_CLR_NVC, cpu6811, 0 },

360 { "clrb", OP_NONE, 1, 0x5f, 2, 2, SET_Z_CLR_NVC, cpu6811 },	472 { "clrb", OP_NONE, 1, 0x5f, 2, 2, SET_Z_CLR_NVC, cpu6811, 0 },

361 { "clra", OP_NONE, 1, 0x87, 1, 1, SET_Z_CLR_NVC, cpu6812 },	473 { "clra", OP_NONE, 1, 0x87, 1, 1, SET_Z_CLR_NVC, cpu6812\|cpu9s12x , 0 },

362 { "clrb", OP_NONE, 1, 0xc7, 1, 1, SET_Z_CLR_NVC, cpu6812 },	474 { "clrb", OP_NONE, 1, 0xc7, 1, 1, SET_Z_CLR_NVC, cpu6812\|cpu9s12x , 0 },

363	475

364 { "clv", OP_NONE, 1, 0x0a, 2, 2, CLR_V, cpu6811 },	476 { "clrw", OP_IND16 \| OP_PAGE2, 3, 0x79, 4, 4, SET_Z_CLR_NVC, cpu9 s12x, 0 },

365	477 { "clrw", OP_IDX \| OP_PAGE2, 2, 0x69, 3, 3, SET_Z_CLR_NVC, cpu9 s12x, 0 },

366 { "cmpa", OP_IMM8, 2, 0x81, 1, 1, CHG_NZVC, cpu6811\|cpu6812 },	478 { "clrw", OP_IDX_1 \| OP_PAGE2, 3, 0x69, 4, 4, SET_Z_CLR_NVC, cpu9 s12x, 0 },

367 { "cmpa", OP_DIRECT, 2, 0x91, 3, 3, CHG_NZVC, cpu6811\|cpu6812 },	479 { "clrw", OP_IDX_2 \| OP_PAGE2, 4, 0x69, 5, 5, SET_Z_CLR_NVC, cpu9 s12x, 0 },

368 { "cmpa", OP_IND16, 3, 0xb1, 3, 3, CHG_NZVC, cpu6811\|cpu6812 },	480 { "clrw", OP_D_IDX \| OP_PAGE2, 2, 0x69, 6, 6, SET_Z_CLR_NVC, cpu9 s12x, 0 },

369 { "cmpa", OP_IX, 2, 0xa1, 4, 4, CHG_NZVC, cpu6811 },	481 { "clrw", OP_D_IDX_2 \| OP_PAGE2, 4, 0x69, 6, 6, SET_Z_CLR_NVC, cpu9 s12x, 0 },

370 { "cmpa", OP_IY \| OP_PAGE2, 3, 0xa1, 5, 5, CHG_NZVC, cpu6811 },	482

371 { "cmpa", OP_IDX, 2, 0xa1, 3, 3, CHG_NZVC, cpu6812 },	483 { "clrx", OP_NONE \| OP_PAGE2, 3, 0x87, 4, 4, SET_Z_CLR_NVC, cpu9s 12x, 0 },

372 { "cmpa", OP_IDX_1, 3, 0xa1, 3, 3, CHG_NZVC, cpu6812 },	484

373 { "cmpa", OP_IDX_2, 4, 0xa1, 4, 4, CHG_NZVC, cpu6812 },	485 { "clry", OP_NONE \| OP_PAGE2, 3, 0xc7, 4, 4, SET_Z_CLR_NVC, cpu9s 12x, 0 },

374 { "cmpa", OP_D_IDX, 2, 0xa1, 6, 6, CHG_NZVC, cpu6812 },	486

375 { "cmpa", OP_D_IDX_2, 4, 0xa1, 6, 6, CHG_NZVC, cpu6812 },	487 { "clv", OP_NONE, 1, 0x0a, 2, 2, CLR_V, cpu6811, 0 },

376	488

377 { "cmpb", OP_IMM8, 2, 0xc1, 1, 1, CHG_NZVC, cpu6811\|cpu6812 },	489 { "cmpa", OP_IMM8, 2, 0x81, 1, 1, CHG_NZVC, cpu6811\|cpu6812\|cpu9s 12x, 0 },

378 { "cmpb", OP_DIRECT, 2, 0xd1, 3, 3, CHG_NZVC, cpu6811\|cpu6812 },	490 { "cmpa", OP_DIRECT, 2, 0x91, 3, 3, CHG_NZVC, cpu6811\|cpu6812\|cpu9s 12x, 0 },

379 { "cmpb", OP_IND16, 3, 0xf1, 3, 3, CHG_NZVC, cpu6811\|cpu6812 },	491 { "cmpa", OP_IND16, 3, 0xb1, 3, 3, CHG_NZVC, cpu6811\|cpu6812\|cpu9s 12x, 0 },

380 { "cmpb", OP_IX, 2, 0xe1, 4, 4, CHG_NZVC, cpu6811 },	492 { "cmpa", OP_IX, 2, 0xa1, 4, 4, CHG_NZVC, cpu6811, 0 },

381 { "cmpb", OP_IY \| OP_PAGE2, 3, 0xe1, 5, 5, CHG_NZVC, cpu6811 },	493 { "cmpa", OP_IY \| OP_PAGE2, 3, 0xa1, 5, 5, CHG_NZVC, cpu6811, 0 },

382 { "cmpb", OP_IDX, 2, 0xe1, 3, 3, CHG_NZVC, cpu6812 },	494 { "cmpa", OP_IDX, 2, 0xa1, 3, 3, CHG_NZVC, cpu6812\|cpu9s12x, 0 } ,

383 { "cmpb", OP_IDX_1, 3, 0xe1, 3, 3, CHG_NZVC, cpu6812 },	495 { "cmpa", OP_IDX_1, 3, 0xa1, 3, 3, CHG_NZVC, cpu6812\|cpu9s12x, 0 } ,

384 { "cmpb", OP_IDX_2, 4, 0xe1, 4, 4, CHG_NZVC, cpu6812 },	496 { "cmpa", OP_IDX_2, 4, 0xa1, 4, 4, CHG_NZVC, cpu6812\|cpu9s12x, 0 } ,

385 { "cmpb", OP_D_IDX, 2, 0xe1, 6, 6, CHG_NZVC, cpu6812 },	497 { "cmpa", OP_D_IDX, 2, 0xa1, 6, 6, CHG_NZVC, cpu6812\|cpu9s12x, 0 } ,

386 { "cmpb", OP_D_IDX_2, 4, 0xe1, 6, 6, CHG_NZVC, cpu6812 },	498 { "cmpa", OP_D_IDX_2, 4, 0xa1, 6, 6, CHG_NZVC, cpu6812\|cpu9s12x, 0 } ,

387	499

388 { "com", OP_IND16, 3, 0x73, 6, 6, SET_C_CLR_V_CHG_NZ, cpu6811 },	500 { "cmpb", OP_IMM8, 2, 0xc1, 1, 1, CHG_NZVC, cpu6811\|cpu6812\|cpu9s 12x, 0 },

389 { "com", OP_IX, 2, 0x63, 6, 6, SET_C_CLR_V_CHG_NZ, cpu6811 },	501 { "cmpb", OP_DIRECT, 2, 0xd1, 3, 3, CHG_NZVC, cpu6811\|cpu6812\|cpu9s 12x, 0 },

390 { "com", OP_IY \| OP_PAGE2, 3, 0x63, 7, 7, SET_C_CLR_V_CHG_NZ, cpu6811 },	502 { "cmpb", OP_IND16, 3, 0xf1, 3, 3, CHG_NZVC, cpu6811\|cpu6812\|cpu9s 12x, 0 },

391 { "com", OP_IND16, 3, 0x71, 4, 4, SET_C_CLR_V_CHG_NZ, cpu6812 },	503 { "cmpb", OP_IX, 2, 0xe1, 4, 4, CHG_NZVC, cpu6811, 0 },

392 { "com", OP_IDX, 2, 0x61, 3, 3, SET_C_CLR_V_CHG_NZ, cpu6812 },	504 { "cmpb", OP_IY \| OP_PAGE2, 3, 0xe1, 5, 5, CHG_NZVC, cpu6811, 0 },

393 { "com", OP_IDX_1, 3, 0x61, 4, 4, SET_C_CLR_V_CHG_NZ, cpu6812 },	505 { "cmpb", OP_IDX, 2, 0xe1, 3, 3, CHG_NZVC, cpu6812\|cpu9s12x, 0 } ,

394 { "com", OP_IDX_2, 4, 0x61, 5, 5, SET_C_CLR_V_CHG_NZ, cpu6812 },	506 { "cmpb", OP_IDX_1, 3, 0xe1, 3, 3, CHG_NZVC, cpu6812\|cpu9s12x, 0 } ,

395 { "com", OP_D_IDX, 2, 0x61, 6, 6, SET_C_CLR_V_CHG_NZ, cpu6812 },	507 { "cmpb", OP_IDX_2, 4, 0xe1, 4, 4, CHG_NZVC, cpu6812\|cpu9s12x, 0 } ,

396 { "com", OP_D_IDX_2, 4, 0x61, 6, 6, SET_C_CLR_V_CHG_NZ, cpu6812 },	508 { "cmpb", OP_D_IDX, 2, 0xe1, 6, 6, CHG_NZVC, cpu6812\|cpu9s12x, 0 } ,

397	509 { "cmpb", OP_D_IDX_2, 4, 0xe1, 6, 6, CHG_NZVC, cpu6812\|cpu9s12x, 0 } ,

398 { "coma", OP_NONE, 1, 0x43, 2, 2, SET_C_CLR_V_CHG_NZ, cpu6811 },	510

399 { "coma", OP_NONE, 1, 0x41, 1, 1, SET_C_CLR_V_CHG_NZ, cpu6812 },	511 { "com", OP_IND16, 3, 0x73, 6, 6, SET_C_CLR_V_CHG_NZ, cpu6811, 0 },

400 { "comb", OP_NONE, 1, 0x53, 2, 2, SET_C_CLR_V_CHG_NZ, cpu6811 },	512 { "com", OP_IX, 2, 0x63, 6, 6, SET_C_CLR_V_CHG_NZ, cpu6811, 0 },

401 { "comb", OP_NONE, 1, 0x51, 1, 1, SET_C_CLR_V_CHG_NZ, cpu6812 },	513 { "com", OP_IY \| OP_PAGE2, 3, 0x63, 7, 7, SET_C_CLR_V_CHG_NZ, cpu6811, 0 },

402	514 { "com", OP_IND16, 3, 0x71, 4, 4, SET_C_CLR_V_CHG_NZ, cpu6812\|cpu 9s12x, 0 },

403 { "cpd", OP_IMM16 \| OP_PAGE3, 4, 0x83, 5, 5, CHG_NZVC, cpu6811 },	515 { "com", OP_IDX, 2, 0x61, 3, 3, SET_C_CLR_V_CHG_NZ, cpu6812\|cpu 9s12x, 0 },

404 { "cpd", OP_DIRECT \| OP_PAGE3, 3, 0x93, 6, 6, CHG_NZVC, cpu6811 },	516 { "com", OP_IDX_1, 3, 0x61, 4, 4, SET_C_CLR_V_CHG_NZ, cpu6812\|cpu 9s12x, 0 },

405 { "cpd", OP_IND16 \| OP_PAGE3, 4, 0xb3, 7, 7, CHG_NZVC, cpu6811 },	517 { "com", OP_IDX_2, 4, 0x61, 5, 5, SET_C_CLR_V_CHG_NZ, cpu6812\|cpu 9s12x, 0 },

406 { "cpd", OP_IX \| OP_PAGE3, 3, 0xa3, 7, 7, CHG_NZVC, cpu6811 },	518 { "com", OP_D_IDX, 2, 0x61, 6, 6, SET_C_CLR_V_CHG_NZ, cpu6812\|cpu 9s12x, 0 },

407 { "cpd", OP_IY \| OP_PAGE4, 3, 0xa3, 7, 7, CHG_NZVC, cpu6811 },	519 { "com", OP_D_IDX_2, 4, 0x61, 6, 6, SET_C_CLR_V_CHG_NZ, cpu6812\|cpu 9s12x, 0 },

408 { "cpd", OP_IMM16, 3, 0x8c, 2, 2, CHG_NZVC, cpu6812 },	520

409 { "cpd", OP_DIRECT, 2, 0x9c, 3, 3, CHG_NZVC, cpu6812 },	521 { "coma", OP_NONE, 1, 0x43, 2, 2, SET_C_CLR_V_CHG_NZ, cpu6811, 0 },

410 { "cpd", OP_IND16, 3, 0xbc, 3, 3, CHG_NZVC, cpu6812 },	522 { "coma", OP_NONE, 1, 0x41, 1, 1, SET_C_CLR_V_CHG_NZ, cpu6812\|cpu 9s12x, 0 },

411 { "cpd", OP_IDX, 2, 0xac, 3, 3, CHG_NZVC, cpu6812 },	523 { "comb", OP_NONE, 1, 0x53, 2, 2, SET_C_CLR_V_CHG_NZ, cpu6811, 0 },

412 { "cpd", OP_IDX_1, 3, 0xac, 3, 3, CHG_NZVC, cpu6812 },	524 { "comb", OP_NONE, 1, 0x51, 1, 1, SET_C_CLR_V_CHG_NZ, cpu6812\|cpu 9s12x, 0 },

413 { "cpd", OP_IDX_2, 4, 0xac, 4, 4, CHG_NZVC, cpu6812 },	525

414 { "cpd", OP_D_IDX, 2, 0xac, 6, 6, CHG_NZVC, cpu6812 },	526 { "comw", OP_IND16 \| OP_PAGE2, 3, 0x71, 4, 4, SET_C_CLR_V_CHG_NZ, cpu9s12x, 0 },

415 { "cpd", OP_D_IDX_2, 4, 0xac, 6, 6, CHG_NZVC, cpu6812 },	527 { "comw", OP_IDX \| OP_PAGE2, 2, 0x61, 3, 3, SET_C_CLR_V_CHG_NZ, cpu9s12x, 0 },

416	528 { "comw", OP_IDX_1 \| OP_PAGE2, 3, 0x61, 4, 4, SET_C_CLR_V_CHG_NZ, cpu9s12x, 0 },

417 { "cps", OP_IMM16, 3, 0x8f, 2, 2, CHG_NZVC, cpu6812 },	529 { "comw", OP_IDX_2 \| OP_PAGE2, 4, 0x61, 5, 5, SET_C_CLR_V_CHG_NZ, cpu9s12x, 0 },

418 { "cps", OP_DIRECT, 2, 0x9f, 3, 3, CHG_NZVC, cpu6812 },	530 { "comw", OP_D_IDX \| OP_PAGE2, 2, 0x61, 6, 6, SET_C_CLR_V_CHG_NZ, cpu9s12x, 0 },

419 { "cps", OP_IND16, 3, 0xbf, 3, 3, CHG_NZVC, cpu6812 },	531 { "comw", OP_D_IDX_2 \| OP_PAGE2, 4, 0x61, 6, 6, SET_C_CLR_V_CHG_NZ, cpu9s12x, 0 },

420 { "cps", OP_IDX, 2, 0xaf, 3, 3, CHG_NZVC, cpu6812 },	532

421 { "cps", OP_IDX_1, 3, 0xaf, 3, 3, CHG_NZVC, cpu6812 },	533 { "comx", OP_NONE \| OP_PAGE2, 1, 0x41, 2, 2, SET_C_CLR_V_CHG_NZ, cpu9s12x, 0 },

422 { "cps", OP_IDX_2, 4, 0xaf, 4, 4, CHG_NZVC, cpu6812 },	534

423 { "cps", OP_D_IDX, 2, 0xaf, 6, 6, CHG_NZVC, cpu6812 },	535 { "comy", OP_NONE \| OP_PAGE2, 1, 0x51, 2, 2, SET_C_CLR_V_CHG_NZ, cpu9s12x, 0 },

424 { "cps", OP_D_IDX_2, 4, 0xaf, 6, 6, CHG_NZVC, cpu6812 },	536

425	537 { "cpd", OP_IMM16 \| OP_PAGE3, 4, 0x83, 5, 5, CHG_NZVC, cpu6811, 0 },

426 { "cpx", OP_IMM16, 3, 0x8c, 4, 4, CHG_NZVC, cpu6811 },	538 { "cpd", OP_DIRECT \| OP_PAGE3, 3, 0x93, 6, 6, CHG_NZVC, cpu6811, 0 },

427 { "cpx", OP_DIRECT, 2, 0x9c, 5, 5, CHG_NZVC, cpu6811 },	539 { "cpd", OP_IND16 \| OP_PAGE3, 4, 0xb3, 7, 7, CHG_NZVC, cpu6811, 0 },

428 { "cpx", OP_IND16, 3, 0xbc, 5, 5, CHG_NZVC, cpu6811 },	540 { "cpd", OP_IX \| OP_PAGE3, 3, 0xa3, 7, 7, CHG_NZVC, cpu6811, 0 },

429 { "cpx", OP_IX, 2, 0xac, 6, 6, CHG_NZVC, cpu6811 },	541 { "cpd", OP_IY \| OP_PAGE4, 3, 0xa3, 7, 7, CHG_NZVC, cpu6811, 0 },

430 { "cpx", OP_IY \| OP_PAGE4, 3, 0xac, 7, 7, CHG_NZVC, cpu6811 },	542 { "cpd", OP_IMM16, 3, 0x8c, 2, 2, CHG_NZVC, cpu6812\|cpu9s12x, 0 },

431 { "cpx", OP_IMM16, 3, 0x8e, 2, 2, CHG_NZVC, cpu6812 },	543 { "cpd", OP_DIRECT, 2, 0x9c, 3, 3, CHG_NZVC, cpu6812\|cpu9s12x, 0 },

432 { "cpx", OP_DIRECT, 2, 0x9e, 3, 3, CHG_NZVC, cpu6812 },	544 { "cpd", OP_IND16, 3, 0xbc, 3, 3, CHG_NZVC, cpu6812\|cpu9s12x, 0 },

433 { "cpx", OP_IND16, 3, 0xbe, 3, 3, CHG_NZVC, cpu6812 },	545 { "cpd", OP_IDX, 2, 0xac, 3, 3, CHG_NZVC, cpu6812\|cpu9s12x, 0 },

434 { "cpx", OP_IDX, 2, 0xae, 3, 3, CHG_NZVC, cpu6812 },	546 { "cpd", OP_IDX_1, 3, 0xac, 3, 3, CHG_NZVC, cpu6812\|cpu9s12x, 0 },

435 { "cpx", OP_IDX_1, 3, 0xae, 3, 3, CHG_NZVC, cpu6812 },	547 { "cpd", OP_IDX_2, 4, 0xac, 4, 4, CHG_NZVC, cpu6812\|cpu9s12x, 0 },

436 { "cpx", OP_IDX_2, 4, 0xae, 4, 4, CHG_NZVC, cpu6812 },	548 { "cpd", OP_D_IDX, 2, 0xac, 6, 6, CHG_NZVC, cpu6812\|cpu9s12x, 0 },

437 { "cpx", OP_D_IDX, 2, 0xae, 6, 6, CHG_NZVC, cpu6812 },	549 { "cpd", OP_D_IDX_2, 4, 0xac, 6, 6, CHG_NZVC, cpu6812\|cpu9s12x, 0 },

438 { "cpx", OP_D_IDX_2, 4, 0xae, 6, 6, CHG_NZVC, cpu6812 },	550

439	551 { "cped", OP_IMM16 \| OP_PAGE2, 3, 0x8c, 2, 2, CHG_NZVC, cpu9s12 x, 0 },

440 { "cpy", OP_PAGE2 \| OP_IMM16, 4, 0x8c, 5, 5, CHG_NZVC, cpu6811 },	552 { "cped", OP_DIRECT \| OP_PAGE2, 2, 0x9c, 3, 3, CHG_NZVC, cpu9s12 x, 0 },

441 { "cpy", OP_PAGE2 \| OP_DIRECT, 3, 0x9c, 6, 6, CHG_NZVC, cpu6811 },	553 { "cped", OP_IND16 \| OP_PAGE2, 3, 0xbc, 3, 3, CHG_NZVC, cpu9s12 x, 0 },

442 { "cpy", OP_PAGE2 \| OP_IY, 3, 0xac, 7, 7, CHG_NZVC, cpu6811 },	554 { "cped", OP_IDX \| OP_PAGE2, 2, 0xac, 3, 3, CHG_NZVC, cpu9s12 x, 0 },

443 { "cpy", OP_PAGE2 \| OP_IND16, 4, 0xbc, 7, 7, CHG_NZVC, cpu6811 },	555 { "cped", OP_IDX_1 \| OP_PAGE2, 3, 0xac, 3, 3, CHG_NZVC, cpu9s12 x, 0 },

444 { "cpy", OP_PAGE3 \| OP_IX, 3, 0xac, 7, 7, CHG_NZVC, cpu6811 },	556 { "cped", OP_IDX_2 \| OP_PAGE2, 4, 0xac, 4, 4, CHG_NZVC, cpu9s12 x, 0 },

445 { "cpy", OP_IMM16, 3, 0x8d, 2, 2, CHG_NZVC, cpu6812 },	557 { "cped", OP_D_IDX \| OP_PAGE2, 2, 0xac, 6, 6, CHG_NZVC, cpu9s12 x, 0 },

446 { "cpy", OP_DIRECT, 2, 0x9d, 3, 3, CHG_NZVC, cpu6812 },	558 { "cped", OP_D_IDX_2 \| OP_PAGE2, 4, 0xac, 6, 6, CHG_NZVC, cpu9s12 x, 0 },

447 { "cpy", OP_IND16, 3, 0xbd, 3, 3, CHG_NZVC, cpu6812 },	559

448 { "cpy", OP_IDX, 2, 0xad, 3, 3, CHG_NZVC, cpu6812 },	560 { "cpes", OP_IMM16 \| OP_PAGE2, 3, 0x8f, 2, 2, CHG_NZVC, cpu9s12 x, 0 },

449 { "cpy", OP_IDX_1, 3, 0xad, 3, 3, CHG_NZVC, cpu6812 },	561 { "cpes", OP_DIRECT \| OP_PAGE2, 2, 0x9f, 3, 3, CHG_NZVC, cpu9s12 x, 0 },

450 { "cpy", OP_IDX_2, 4, 0xad, 4, 4, CHG_NZVC, cpu6812 },	562 { "cpes", OP_IND16 \| OP_PAGE2, 3, 0xbf, 3, 3, CHG_NZVC, cpu9s12 x, 0 },

451 { "cpy", OP_D_IDX, 2, 0xad, 6, 6, CHG_NZVC, cpu6812 },	563 { "cpes", OP_IDX \| OP_PAGE2, 2, 0xaf, 3, 3, CHG_NZVC, cpu9s12 x, 0 },

452 { "cpy", OP_D_IDX_2, 4, 0xad, 6, 6, CHG_NZVC, cpu6812 },	564 { "cpes", OP_IDX_1 \| OP_PAGE2, 3, 0xaf, 3, 3, CHG_NZVC, cpu9s12 x, 0 },

	565 { "cpes", OP_IDX_2 \| OP_PAGE2, 4, 0xaf, 4, 4, CHG_NZVC, cpu9s12 x, 0 },

	566 { "cpes", OP_D_IDX \| OP_PAGE2, 2, 0xaf, 6, 6, CHG_NZVC, cpu9s12 x, 0 },

	567 { "cpes", OP_D_IDX_2 \| OP_PAGE2, 4, 0xaf, 6, 6, CHG_NZVC, cpu9s12 x, 0 },

	568

	569 { "cpex", OP_IMM16 \| OP_PAGE2, 3, 0x8e, 2, 2, CHG_NZVC, cpu9s12 x, 0 },

	570 { "cpex", OP_DIRECT \| OP_PAGE2, 2, 0x9e, 3, 3, CHG_NZVC, cpu9s12 x, 0 },

	571 { "cpex", OP_IND16 \| OP_PAGE2, 3, 0xbe, 3, 3, CHG_NZVC, cpu9s12 x, 0 },

	572 { "cpex", OP_IDX \| OP_PAGE2, 2, 0xae, 3, 3, CHG_NZVC, cpu9s12 x, 0 },

	573 { "cpex", OP_IDX_1 \| OP_PAGE2, 3, 0xae, 3, 3, CHG_NZVC, cpu9s12 x, 0 },

	574 { "cpex", OP_IDX_2 \| OP_PAGE2, 4, 0xae, 4, 4, CHG_NZVC, cpu9s12 x, 0 },

	575 { "cpex", OP_D_IDX \| OP_PAGE2, 2, 0xae, 6, 6, CHG_NZVC, cpu9s12 x, 0 },

	576 { "cpex", OP_D_IDX_2 \| OP_PAGE2, 4, 0xae, 6, 6, CHG_NZVC, cpu9s12 x, 0 },

	577

	578 { "cpey", OP_IMM16 \| OP_PAGE2, 3, 0x8d, 2, 2, CHG_NZVC, cpu9s12 x, 0 },

	579 { "cpey", OP_DIRECT \| OP_PAGE2, 2, 0x9d, 3, 3, CHG_NZVC, cpu9s12 x, 0 },

	580 { "cpey", OP_IND16 \| OP_PAGE2, 3, 0xbd, 3, 3, CHG_NZVC, cpu9s12 x, 0 },

	581 { "cpey", OP_IDX \| OP_PAGE2, 2, 0xad, 3, 3, CHG_NZVC, cpu9s12 x, 0 },

	582 { "cpey", OP_IDX_1 \| OP_PAGE2, 3, 0xad, 3, 3, CHG_NZVC, cpu9s12 x, 0 },

	583 { "cpey", OP_IDX_2 \| OP_PAGE2, 4, 0xad, 4, 4, CHG_NZVC, cpu9s12 x, 0 },

	584 { "cpey", OP_D_IDX \| OP_PAGE2, 2, 0xad, 6, 6, CHG_NZVC, cpu9s12 x, 0 },

	585 { "cpey", OP_D_IDX_2 \| OP_PAGE2, 4, 0xad, 6, 6, CHG_NZVC, cpu9s12 x, 0 },

	586

	587 { "cps", OP_IMM16, 3, 0x8f, 2, 2, CHG_NZVC, cpu6812\|cpu9s12x, 0 },

	588 { "cps", OP_DIRECT, 2, 0x9f, 3, 3, CHG_NZVC, cpu6812\|cpu9s12x, 0 },

	589 { "cps", OP_IND16, 3, 0xbf, 3, 3, CHG_NZVC, cpu6812\|cpu9s12x, 0 },

	590 { "cps", OP_IDX, 2, 0xaf, 3, 3, CHG_NZVC, cpu6812\|cpu9s12x, 0 },

	591 { "cps", OP_IDX_1, 3, 0xaf, 3, 3, CHG_NZVC, cpu6812\|cpu9s12x, 0 },

	592 { "cps", OP_IDX_2, 4, 0xaf, 4, 4, CHG_NZVC, cpu6812\|cpu9s12x, 0 },

	593 { "cps", OP_D_IDX, 2, 0xaf, 6, 6, CHG_NZVC, cpu6812\|cpu9s12x, 0 },

	594 { "cps", OP_D_IDX_2, 4, 0xaf, 6, 6, CHG_NZVC, cpu6812\|cpu9s12x, 0 },

	595

	596 { "cpx", OP_IMM16, 3, 0x8c, 4, 4, CHG_NZVC, cpu6811, 0 },

	597 { "cpx", OP_DIRECT, 2, 0x9c, 5, 5, CHG_NZVC, cpu6811, 0 },

	598 { "cpx", OP_IND16, 3, 0xbc, 5, 5, CHG_NZVC, cpu6811, 0 },

	599 { "cpx", OP_IX, 2, 0xac, 6, 6, CHG_NZVC, cpu6811, 0 },

	600 { "cpx", OP_IY \| OP_PAGE4, 3, 0xac, 7, 7, CHG_NZVC, cpu6811, 0 },

	601 { "cpx", OP_IMM16, 3, 0x8e, 2, 2, CHG_NZVC, cpu6812\|cpu9s12x, 0 },

	602 { "cpx", OP_DIRECT, 2, 0x9e, 3, 3, CHG_NZVC, cpu6812\|cpu9s12x, 0 },

	603 { "cpx", OP_IND16, 3, 0xbe, 3, 3, CHG_NZVC, cpu6812\|cpu9s12x, 0 },

	604 { "cpx", OP_IDX, 2, 0xae, 3, 3, CHG_NZVC, cpu6812\|cpu9s12x, 0 },

	605 { "cpx", OP_IDX_1, 3, 0xae, 3, 3, CHG_NZVC, cpu6812\|cpu9s12x, 0 },

	606 { "cpx", OP_IDX_2, 4, 0xae, 4, 4, CHG_NZVC, cpu6812\|cpu9s12x, 0 },

	607 { "cpx", OP_D_IDX, 2, 0xae, 6, 6, CHG_NZVC, cpu6812\|cpu9s12x, 0 },

	608 { "cpx", OP_D_IDX_2, 4, 0xae, 6, 6, CHG_NZVC, cpu6812\|cpu9s12x, 0 },

	609

	610 { "cpy", OP_PAGE2 \| OP_IMM16, 4, 0x8c, 5, 5, CHG_NZVC, cpu6811, 0 },

	611 { "cpy", OP_PAGE2 \| OP_DIRECT, 3, 0x9c, 6, 6, CHG_NZVC, cpu6811, 0 },

	612 { "cpy", OP_PAGE2 \| OP_IY, 3, 0xac, 7, 7, CHG_NZVC, cpu6811, 0 },

	613 { "cpy", OP_PAGE2 \| OP_IND16, 4, 0xbc, 7, 7, CHG_NZVC, cpu6811, 0 },

	614 { "cpy", OP_PAGE3 \| OP_IX, 3, 0xac, 7, 7, CHG_NZVC, cpu6811, 0 },

	615 { "cpy", OP_IMM16, 3, 0x8d, 2, 2, CHG_NZVC, cpu6812\|cpu9s12x, 0 },

	616 { "cpy", OP_DIRECT, 2, 0x9d, 3, 3, CHG_NZVC, cpu6812\|cpu9s12x, 0 },

	617 { "cpy", OP_IND16, 3, 0xbd, 3, 3, CHG_NZVC, cpu6812\|cpu9s12x, 0 },

	618 { "cpy", OP_IDX, 2, 0xad, 3, 3, CHG_NZVC, cpu6812\|cpu9s12x, 0 },

	619 { "cpy", OP_IDX_1, 3, 0xad, 3, 3, CHG_NZVC, cpu6812\|cpu9s12x, 0 },

	620 { "cpy", OP_IDX_2, 4, 0xad, 4, 4, CHG_NZVC, cpu6812\|cpu9s12x, 0 },

	621 { "cpy", OP_D_IDX, 2, 0xad, 6, 6, CHG_NZVC, cpu6812\|cpu9s12x, 0 },

	622 { "cpy", OP_D_IDX_2, 4, 0xad, 6, 6, CHG_NZVC, cpu6812\|cpu9s12x, 0 },

453	623

454 /* After 'daa', the Z flag is undefined. Mark it as changed. */	624 /* After 'daa', the Z flag is undefined. Mark it as changed. */

455 { "daa", OP_NONE, 1, 0x19, 2, 2, CHG_NZVC, cpu6811 },	625 { "daa", OP_NONE, 1, 0x19, 2, 2, CHG_NZVC, cpu6811, 0 },

456 { "daa", OP_NONE \| OP_PAGE2, 2, 0x07, 3, 3, CHG_NZVC, cpu6812 },	626 { "daa", OP_NONE \| OP_PAGE2, 2, 0x07, 3, 3, CHG_NZVC, cpu6812\|cpu9s12x, 0 },

457	627

458 { "dbeq", OP_DBEQ_MARKER	628 { "dbeq", OP_DBEQ_MARKER

459 \| OP_REG \| OP_JUMP_REL,3, 0x04, 3, 3, CHG_NONE, cpu6812 },	629 \| OP_REG \| OP_JUMP_REL,3, 0x04, 3, 3, CHG_NONE, cpu6812\|cpu9s12x, 0 },

460 { "dbne", OP_DBNE_MARKER	630 { "dbne", OP_DBNE_MARKER

461 \| OP_REG \| OP_JUMP_REL,3, 0x04, 3, 3, CHG_NONE, cpu6812 },	631 \| OP_REG \| OP_JUMP_REL,3, 0x04, 3, 3, CHG_NONE, cpu6812\|cpu9s12x, 0 },

462	632

463 { "dec", OP_IX, 2, 0x6a, 6, 6, CHG_NZV, cpu6811 },	633 { "dec", OP_IX, 2, 0x6a, 6, 6, CHG_NZV, cpu6811, 0 },

464 { "dec", OP_IND16, 3, 0x7a, 6, 6, CHG_NZV, cpu6811 },	634 { "dec", OP_IND16, 3, 0x7a, 6, 6, CHG_NZV, cpu6811, 0 },

465 { "dec", OP_IY \| OP_PAGE2, 3, 0x6a, 7, 7, CHG_NZV, cpu6811 },	635 { "dec", OP_IY \| OP_PAGE2, 3, 0x6a, 7, 7, CHG_NZV, cpu6811, 0 },

466 { "dec", OP_IND16, 3, 0x73, 4, 4, CHG_NZV, cpu6812 },	636 { "dec", OP_IND16, 3, 0x73, 4, 4, CHG_NZV, cpu6812\|cpu9s12x, 0 },

467 { "dec", OP_IDX, 2, 0x63, 3, 3, CHG_NZV, cpu6812 },	637 { "dec", OP_IDX, 2, 0x63, 3, 3, CHG_NZV, cpu6812\|cpu9s12x, 0 },

468 { "dec", OP_IDX_1, 3, 0x63, 4, 4, CHG_NZV, cpu6812 },	638 { "dec", OP_IDX_1, 3, 0x63, 4, 4, CHG_NZV, cpu6812\|cpu9s12x, 0 },

469 { "dec", OP_IDX_2, 4, 0x63, 5, 5, CHG_NZV, cpu6812 },	639 { "dec", OP_IDX_2, 4, 0x63, 5, 5, CHG_NZV, cpu6812\|cpu9s12x, 0 },

470 { "dec", OP_D_IDX, 2, 0x63, 6, 6, CHG_NZV, cpu6812 },	640 { "dec", OP_D_IDX, 2, 0x63, 6, 6, CHG_NZV, cpu6812\|cpu9s12x, 0 },

471 { "dec", OP_D_IDX_2, 4, 0x63, 6, 6, CHG_NZV, cpu6812 },	641 { "dec", OP_D_IDX_2, 4, 0x63, 6, 6, CHG_NZV, cpu6812\|cpu9s12x, 0 },

472	642

473 { "des", OP_NONE, 1, 0x34, 3, 3, CHG_NONE, cpu6811 },	643 { "des", OP_NONE, 1, 0x34, 3, 3, CHG_NONE, cpu6811, 0 },

474	644

475 { "deca", OP_NONE, 1, 0x4a, 2, 2, CHG_NZV, cpu6811 },	645 { "deca", OP_NONE, 1, 0x4a, 2, 2, CHG_NZV, cpu6811, 0 },

476 { "deca", OP_NONE, 1, 0x43, 1, 1, CHG_NZV, cpu6812 },	646 { "deca", OP_NONE, 1, 0x43, 1, 1, CHG_NZV, cpu6812\|cpu9s12x, 0 },

477 { "decb", OP_NONE, 1, 0x5a, 2, 2, CHG_NZV, cpu6811 },	647 { "decb", OP_NONE, 1, 0x5a, 2, 2, CHG_NZV, cpu6811, 0 },

478 { "decb", OP_NONE, 1, 0x53, 1, 1, CHG_NZV, cpu6812 },	648 { "decb", OP_NONE, 1, 0x53, 1, 1, CHG_NZV, cpu6812\|cpu9s12x, 0 },

479	649

480 { "dex", OP_NONE, 1, 0x09, 1, 1, CHG_Z, cpu6812\|cpu6811 },	650 { "decw", OP_IND16 \| OP_PAGE2, 3, 0x73, 4, 4, CHG_NZV, cpu9s12x, 0 },

481 { "dey", OP_NONE \| OP_PAGE2, 2, 0x09, 4, 4, CHG_Z, cpu6811 },	651 { "decw", OP_IDX \| OP_PAGE2, 2, 0x63, 3, 3, CHG_NZV, cpu9s12x, 0 },

482 { "dey", OP_NONE, 1, 0x03, 1, 1, CHG_Z, cpu6812 },	652 { "decw", OP_IDX_1 \| OP_PAGE2, 3, 0x63, 4, 4, CHG_NZV, cpu9s12x, 0 },

483	653 { "decw", OP_IDX_2 \| OP_PAGE2, 4, 0x63, 5, 5, CHG_NZV, cpu9s12x, 0 },

484 { "ediv", OP_NONE, 1, 0x11, 11, 11, CHG_NZVC, cpu6812 },	654 { "decw", OP_D_IDX \| OP_PAGE2, 2, 0x63, 6, 6, CHG_NZV, cpu9s12x, 0 },

485 { "edivs", OP_NONE \| OP_PAGE2, 2, 0x14, 12, 12, CHG_NZVC, cpu6812 },	655 { "decw", OP_D_IDX_2 \| OP_PAGE2, 4, 0x63, 6, 6, CHG_NZV, cpu9s12x, 0 },

486 { "emacs", OP_IND16 \| OP_PAGE2, 4, 0x12, 13, 13, CHG_NZVC, cpu6812 },	656

487	657 { "decx", OP_NONE \| OP_PAGE2, 3, 0x43, 4, 4, CHG_NZV, cpu9s12x, 0 },

488 { "emaxd", OP_IDX \| OP_PAGE2, 3, 0x1a, 4, 4, CHG_NZVC, cpu6812 },	658

489 { "emaxd", OP_IDX_1 \| OP_PAGE2, 4, 0x1a, 4, 4, CHG_NZVC, cpu6812 },	659 { "decy", OP_NONE \| OP_PAGE2, 3, 0x53, 4, 4, CHG_NZV, cpu9s12x, 0 },

490 { "emaxd", OP_IDX_2 \| OP_PAGE2, 5, 0x1a, 5, 5, CHG_NZVC, cpu6812 },	660

491 { "emaxd", OP_D_IDX \| OP_PAGE2, 3, 0x1a, 7, 7, CHG_NZVC, cpu6812 },	661 { "dex", OP_NONE, 1, 0x09, 1, 1, CHG_Z, cpu6812\|cpu9s12x\|cpu68 11, 0 },

492 { "emaxd", OP_D_IDX_2 \| OP_PAGE2, 5, 0x1a, 7, 7, CHG_NZVC, cpu6812 },	662 { "dey", OP_NONE \| OP_PAGE2, 2, 0x09, 4, 4, CHG_Z, cpu6811, 0 },

493	663 { "dey", OP_NONE, 1, 0x03, 1, 1, CHG_Z, cpu6812\|cpu9s12x, 0 },

494 { "emaxm", OP_IDX \| OP_PAGE2, 3, 0x1e, 4, 4, CHG_NZVC, cpu6812 },	664

495 { "emaxm", OP_IDX_1 \| OP_PAGE2, 4, 0x1e, 5, 5, CHG_NZVC, cpu6812 },	665 { "ediv", OP_NONE, 1, 0x11, 11, 11, CHG_NZVC, cpu6812\|cpu9s12x, 0 },

496 { "emaxm", OP_IDX_2 \| OP_PAGE2, 5, 0x1e, 6, 6, CHG_NZVC, cpu6812 },	666 { "edivs", OP_NONE \| OP_PAGE2, 2, 0x14, 12, 12, CHG_NZVC, cpu6812\|cpu9s12x, 0 },

497 { "emaxm", OP_D_IDX \| OP_PAGE2, 3, 0x1e, 7, 7, CHG_NZVC, cpu6812 },	667 { "emacs", OP_IND16 \| OP_PAGE2, 4, 0x12, 13, 13, CHG_NZVC, cpu6812\|cpu9s12x , 0 },

498 { "emaxm", OP_D_IDX_2 \| OP_PAGE2, 5, 0x1e, 7, 7, CHG_NZVC, cpu6812 },	668

499	669 { "emaxd", OP_IDX \| OP_PAGE2, 3, 0x1a, 4, 4, CHG_NZVC, cpu6812\|cpu9s12x , 0 },

500 { "emind", OP_IDX \| OP_PAGE2, 3, 0x1b, 4, 4, CHG_NZVC, cpu6812 },	670 { "emaxd", OP_IDX_1 \| OP_PAGE2, 4, 0x1a, 4, 4, CHG_NZVC, cpu6812\|cpu9s12x , 0 },

501 { "emind", OP_IDX_1 \| OP_PAGE2, 4, 0x1b, 4, 4, CHG_NZVC, cpu6812 },	671 { "emaxd", OP_IDX_2 \| OP_PAGE2, 5, 0x1a, 5, 5, CHG_NZVC, cpu6812\|cpu9s12x , 0 },

502 { "emind", OP_IDX_2 \| OP_PAGE2, 5, 0x1b, 5, 5, CHG_NZVC, cpu6812 },	672 { "emaxd", OP_D_IDX \| OP_PAGE2, 3, 0x1a, 7, 7, CHG_NZVC, cpu6812\|cpu9s12x , 0 },

503 { "emind", OP_D_IDX \| OP_PAGE2, 3, 0x1b, 7, 7, CHG_NZVC, cpu6812 },	673 { "emaxd", OP_D_IDX_2 \| OP_PAGE2, 5, 0x1a, 7, 7, CHG_NZVC, cpu6812\|cpu9s12x , 0 },

504 { "emind", OP_D_IDX_2 \| OP_PAGE2, 5, 0x1b, 7, 7, CHG_NZVC, cpu6812 },	674

505	675 { "emaxm", OP_IDX \| OP_PAGE2, 3, 0x1e, 4, 4, CHG_NZVC, cpu6812\|cpu9s12x , 0 },

506 { "eminm", OP_IDX \| OP_PAGE2, 3, 0x1f, 4, 4, CHG_NZVC, cpu6812 },	676 { "emaxm", OP_IDX_1 \| OP_PAGE2, 4, 0x1e, 5, 5, CHG_NZVC, cpu6812\|cpu9s12x , 0 },

507 { "eminm", OP_IDX_1 \| OP_PAGE2, 4, 0x1f, 5, 5, CHG_NZVC, cpu6812 },	677 { "emaxm", OP_IDX_2 \| OP_PAGE2, 5, 0x1e, 6, 6, CHG_NZVC, cpu6812\|cpu9s12x , 0 },

508 { "eminm", OP_IDX_2 \| OP_PAGE2, 5, 0x1f, 6, 6, CHG_NZVC, cpu6812 },	678 { "emaxm", OP_D_IDX \| OP_PAGE2, 3, 0x1e, 7, 7, CHG_NZVC, cpu6812\|cpu9s12x , 0 },

509 { "eminm", OP_D_IDX \| OP_PAGE2, 3, 0x1f, 7, 7, CHG_NZVC, cpu6812 },	679 { "emaxm", OP_D_IDX_2 \| OP_PAGE2, 5, 0x1e, 7, 7, CHG_NZVC, cpu6812\|cpu9s12x , 0 },

510 { "eminm", OP_D_IDX_2 \| OP_PAGE2, 5, 0x1f, 7, 7, CHG_NZVC, cpu6812 },	680

511	681 { "emind", OP_IDX \| OP_PAGE2, 3, 0x1b, 4, 4, CHG_NZVC, cpu6812\|cpu9s12x , 0 },

512 { "emul", OP_NONE, 1, 0x13, 3, 3, CHG_NZC, cpu6812 },	682 { "emind", OP_IDX_1 \| OP_PAGE2, 4, 0x1b, 4, 4, CHG_NZVC, cpu6812\|cpu9s12x , 0 },

513 { "emuls", OP_NONE \| OP_PAGE2, 2, 0x13, 3, 3, CHG_NZC, cpu6812 },	683 { "emind", OP_IDX_2 \| OP_PAGE2, 5, 0x1b, 5, 5, CHG_NZVC, cpu6812\|cpu9s12x , 0 },

514	684 { "emind", OP_D_IDX \| OP_PAGE2, 3, 0x1b, 7, 7, CHG_NZVC, cpu6812\|cpu9s12x , 0 },

515 { "eora", OP_IMM8, 2, 0x88, 1, 1, CLR_V_CHG_NZ, cpu6811\|cpu6812 },	685 { "emind", OP_D_IDX_2 \| OP_PAGE2, 5, 0x1b, 7, 7, CHG_NZVC, cpu6812\|cpu9s12x , 0 },

516 { "eora", OP_DIRECT, 2, 0x98, 3, 3, CLR_V_CHG_NZ, cpu6811\|cpu6812 },	686

517 { "eora", OP_IND16, 3, 0xb8, 3, 3, CLR_V_CHG_NZ, cpu6811\|cpu6812 },	687 { "eminm", OP_IDX \| OP_PAGE2, 3, 0x1f, 4, 4, CHG_NZVC, cpu6812\|cpu9s12x , 0 },

518 { "eora", OP_IX, 2, 0xa8, 4, 4, CLR_V_CHG_NZ, cpu6811 },	688 { "eminm", OP_IDX_1 \| OP_PAGE2, 4, 0x1f, 5, 5, CHG_NZVC, cpu6812\|cpu9s12x , 0 },

519 { "eora", OP_IY \| OP_PAGE2, 3, 0xa8, 5, 5, CLR_V_CHG_NZ, cpu6811 },	689 { "eminm", OP_IDX_2 \| OP_PAGE2, 5, 0x1f, 6, 6, CHG_NZVC, cpu6812\|cpu9s12x , 0 },

520 { "eora", OP_IDX, 2, 0xa8, 3, 3, CLR_V_CHG_NZ, cpu6812 },	690 { "eminm", OP_D_IDX \| OP_PAGE2, 3, 0x1f, 7, 7, CHG_NZVC, cpu6812\|cpu9s12x , 0 },

521 { "eora", OP_IDX_1, 3, 0xa8, 3, 3, CLR_V_CHG_NZ, cpu6812 },	691 { "eminm", OP_D_IDX_2 \| OP_PAGE2, 5, 0x1f, 7, 7, CHG_NZVC, cpu6812\|cpu9s12x , 0 },

522 { "eora", OP_IDX_2, 4, 0xa8, 4, 4, CLR_V_CHG_NZ, cpu6812 },	692

523 { "eora", OP_D_IDX, 2, 0xa8, 6, 6, CLR_V_CHG_NZ, cpu6812 },	693 { "emul", OP_NONE, 1, 0x13, 3, 3, CHG_NZC, cpu6812\|cpu9s12x, 0 },

524 { "eora", OP_D_IDX_2, 4, 0xa8, 6, 6, CLR_V_CHG_NZ, cpu6812 },	694 { "emuls", OP_NONE \| OP_PAGE2, 2, 0x13, 3, 3, CHG_NZC, cpu6812\|cpu9s12x, 0 },

525	695

526 { "eorb", OP_IMM8, 2, 0xc8, 1, 1, CLR_V_CHG_NZ, cpu6811\|cpu6812 },	696 { "eora", OP_IMM8, 2, 0x88, 1, 1, CLR_V_CHG_NZ, cpu6811\|cpu6812\|cpu 9s12x, 0 },

527 { "eorb", OP_DIRECT, 2, 0xd8, 3, 3, CLR_V_CHG_NZ, cpu6811\|cpu6812 },	697 { "eora", OP_DIRECT, 2, 0x98, 3, 3, CLR_V_CHG_NZ, cpu6811\|cpu6812\|cpu 9s12x, 0 },

528 { "eorb", OP_IND16, 3, 0xf8, 3, 3, CLR_V_CHG_NZ, cpu6811\|cpu6812 },	698 { "eora", OP_IND16, 3, 0xb8, 3, 3, CLR_V_CHG_NZ, cpu6811\|cpu6812\|cpu 9s12x, 0 },

529 { "eorb", OP_IX, 2, 0xe8, 4, 4, CLR_V_CHG_NZ, cpu6811 },	699 { "eora", OP_IX, 2, 0xa8, 4, 4, CLR_V_CHG_NZ, cpu6811, 0 },

530 { "eorb", OP_IY \| OP_PAGE2, 3, 0xe8, 5, 5, CLR_V_CHG_NZ, cpu6811 },	700 { "eora", OP_IY \| OP_PAGE2, 3, 0xa8, 5, 5, CLR_V_CHG_NZ, cpu6811, 0 },

531 { "eorb", OP_IDX, 2, 0xe8, 3, 3, CLR_V_CHG_NZ, cpu6812 },	701 { "eora", OP_IDX, 2, 0xa8, 3, 3, CLR_V_CHG_NZ, cpu6812\|cpu9s12x, 0 },

532 { "eorb", OP_IDX_1, 3, 0xe8, 3, 3, CLR_V_CHG_NZ, cpu6812 },	702 { "eora", OP_IDX_1, 3, 0xa8, 3, 3, CLR_V_CHG_NZ, cpu6812\|cpu9s12x, 0 },

533 { "eorb", OP_IDX_2, 4, 0xe8, 4, 4, CLR_V_CHG_NZ, cpu6812 },	703 { "eora", OP_IDX_2, 4, 0xa8, 4, 4, CLR_V_CHG_NZ, cpu6812\|cpu9s12x, 0 },

534 { "eorb", OP_D_IDX, 2, 0xe8, 6, 6, CLR_V_CHG_NZ, cpu6812 },	704 { "eora", OP_D_IDX, 2, 0xa8, 6, 6, CLR_V_CHG_NZ, cpu6812\|cpu9s12x, 0 },

535 { "eorb", OP_D_IDX_2, 4, 0xe8, 6, 6, CLR_V_CHG_NZ, cpu6812 },	705 { "eora", OP_D_IDX_2, 4, 0xa8, 6, 6, CLR_V_CHG_NZ, cpu6812\|cpu9s12x, 0 },

536	706

537 { "etbl", OP_IDX \| OP_PAGE2,3, 0x3f, 10, 10, CHG_NZC, cpu6812 },	707 { "eorb", OP_IMM8, 2, 0xc8, 1, 1, CLR_V_CHG_NZ, cpu6811\|cpu6812\|cpu 9s12x, 0 },

538	708 { "eorb", OP_DIRECT, 2, 0xd8, 3, 3, CLR_V_CHG_NZ, cpu6811\|cpu6812\|cpu 9s12x, 0 },

	709 { "eorb", OP_IND16, 3, 0xf8, 3, 3, CLR_V_CHG_NZ, cpu6811\|cpu6812\|cpu 9s12x, 0 },

	710 { "eorb", OP_IX, 2, 0xe8, 4, 4, CLR_V_CHG_NZ, cpu6811, 0 },

	711 { "eorb", OP_IY \| OP_PAGE2, 3, 0xe8, 5, 5, CLR_V_CHG_NZ, cpu6811, 0 },

	712 { "eorb", OP_IDX, 2, 0xe8, 3, 3, CLR_V_CHG_NZ, cpu6812\|cpu9s12x, 0 },

	713 { "eorb", OP_IDX_1, 3, 0xe8, 3, 3, CLR_V_CHG_NZ, cpu6812\|cpu9s12x, 0 },

	714 { "eorb", OP_IDX_2, 4, 0xe8, 4, 4, CLR_V_CHG_NZ, cpu6812\|cpu9s12x, 0 },

	715 { "eorb", OP_D_IDX, 2, 0xe8, 6, 6, CLR_V_CHG_NZ, cpu6812\|cpu9s12x, 0 },

	716 { "eorb", OP_D_IDX_2, 4, 0xe8, 6, 6, CLR_V_CHG_NZ, cpu6812\|cpu9s12x, 0 },

	717

	718 { "eorx", OP_IMM16 \| OP_PAGE2, 2, 0x88, 1, 1, CLR_V_CHG_NZ, cpu9s12 x, 0 },

	719 { "eorx", OP_DIRECT \| OP_PAGE2, 2, 0x98, 3, 3, CLR_V_CHG_NZ, cpu9s12x , 0 },

	720 { "eorx", OP_IND16 \| OP_PAGE2, 3, 0xb8, 3, 3, CLR_V_CHG_NZ, cpu9s12x , 0 },

	721 { "eorx", OP_IDX \| OP_PAGE2, 2, 0xa8, 3, 3, CLR_V_CHG_NZ, cpu9s1 2x, 0 },

	722 { "eorx", OP_IDX_1 \| OP_PAGE2, 3, 0xa8, 3, 3, CLR_V_CHG_NZ, cpu9s1 2x, 0 },

	723 { "eorx", OP_IDX_2 \| OP_PAGE2, 4, 0xa8, 4, 4, CLR_V_CHG_NZ, cpu9s1 2x, 0 },

	724 { "eorx", OP_D_IDX \| OP_PAGE2, 2, 0xa8, 6, 6, CLR_V_CHG_NZ, cpu9s1 2x, 0 },

	725 { "eorx", OP_D_IDX_2 \| OP_PAGE2, 4, 0xa8, 6, 6, CLR_V_CHG_NZ, cpu9s1 2x, 0 },

	726

	727 { "eory", OP_IMM16 \| OP_PAGE2, 2, 0xc8, 1, 1, CLR_V_CHG_NZ, cpu9s12 x, 0 },

	728 { "eory", OP_DIRECT \| OP_PAGE2, 2, 0xd8, 3, 3, CLR_V_CHG_NZ, cpu9s12x , 0 },

	729 { "eory", OP_IND16 \| OP_PAGE2, 3, 0xf8, 3, 3, CLR_V_CHG_NZ, cpu9s12x , 0 },

	730 { "eory", OP_IDX \| OP_PAGE2, 2, 0xe8, 3, 3, CLR_V_CHG_NZ, cpu9s1 2x, 0 },

	731 { "eory", OP_IDX_1 \| OP_PAGE2, 3, 0xe8, 3, 3, CLR_V_CHG_NZ, cpu9s1 2x, 0 },

	732 { "eory", OP_IDX_2 \| OP_PAGE2, 4, 0xe8, 4, 4, CLR_V_CHG_NZ, cpu9s1 2x, 0 },

	733 { "eory", OP_D_IDX \| OP_PAGE2, 2, 0xe8, 6, 6, CLR_V_CHG_NZ, cpu9s1 2x, 0 },

	734 { "eory", OP_D_IDX_2 \| OP_PAGE2, 4, 0xe8, 6, 6, CLR_V_CHG_NZ, cpu9s1 2x, 0 },

	735

	736 { "etbl", OP_IDX \| OP_PAGE2,3, 0x3f, 10, 10, CHG_NZC, cpu6812\|cpu9s12x, 0 },

	737

	738 /* S12X has more exg variants, most are pointless so not supported */

539 { "exg", OP_EXG_MARKER	739 { "exg", OP_EXG_MARKER

540 \| OP_REG \| OP_REG_2, 2, 0xb7, 1, 1, CHG_NONE, cpu6812 },	740 \| OP_REG \| OP_REG_2, 2, 0xb7, 1, 1, CHG_NONE, cpu6812\|cpu9s12x, 0 },

541	741

542 { "fdiv", OP_NONE, 1, 0x03, 3, 41, CHG_ZVC, cpu6811},	742 { "fdiv", OP_NONE, 1, 0x03, 3, 41, CHG_ZVC, cpu6811, 0 },

543 { "fdiv", OP_NONE \| OP_PAGE2, 2, 0x11, 12, 12, CHG_ZVC, cpu6812 },	743 { "fdiv", OP_NONE \| OP_PAGE2, 2, 0x11, 12, 12, CHG_ZVC, cpu6812\|cpu9s12x, 0 },

	744

	745 { "gldaa", OP_DIRECT \| OP_PAGE2, 2, 0x96, 3, 3, CLR_V_CHG_NZ, cpu9s12 x, 0 },

	746 { "gldaa", OP_IND16 \| OP_PAGE2, 3, 0xb6, 3, 3, CLR_V_CHG_NZ, cpu9s12 x, 0 },

	747 { "gldaa", OP_IDX \| OP_PAGE2, 2, 0xa6, 3, 3, CLR_V_CHG_NZ, cpu9s 12x, 0 },

	748 { "gldaa", OP_IDX_1 \| OP_PAGE2, 3, 0xa6, 3, 3, CLR_V_CHG_NZ, cpu9s 12x, 0 },

	749 { "gldaa", OP_IDX_2 \| OP_PAGE2, 4, 0xa6, 4, 4, CLR_V_CHG_NZ, cpu9s 12x, 0 },

	750 { "gldaa", OP_D_IDX \| OP_PAGE2, 2, 0xa6, 6, 6, CLR_V_CHG_NZ, cpu9s 12x, 0 },

	751 { "gldaa", OP_D_IDX_2 \| OP_PAGE2, 4, 0xa6, 6, 6, CLR_V_CHG_NZ, cpu9s 12x, 0 },

	752

	753 { "gldab", OP_DIRECT \| OP_PAGE2, 2, 0xd6, 3, 3, CLR_V_CHG_NZ, cpu9s12 x, 0 },

	754 { "gldab", OP_IND16 \| OP_PAGE2, 3, 0xf6, 3, 3, CLR_V_CHG_NZ, cpu9s12 x, 0 },

	755 { "gldab", OP_IDX \| OP_PAGE2, 2, 0xe6, 3, 3, CLR_V_CHG_NZ, cpu9s 12x, 0 },

	756 { "gldab", OP_IDX_1 \| OP_PAGE2, 3, 0xe6, 3, 3, CLR_V_CHG_NZ, cpu9s 12x, 0 },

	757 { "gldab", OP_IDX_2 \| OP_PAGE2, 4, 0xe6, 4, 4, CLR_V_CHG_NZ, cpu9s 12x, 0 },

	758 { "gldab", OP_D_IDX \| OP_PAGE2, 2, 0xe6, 6, 6, CLR_V_CHG_NZ, cpu9s 12x, 0 },

	759 { "gldab", OP_D_IDX_2 \| OP_PAGE2, 4, 0xe6, 6, 6, CLR_V_CHG_NZ, cpu9s 12x, 0 },

	760

	761 { "gldd", OP_DIRECT \| OP_PAGE2, 2, 0xdc, 3, 3, CLR_V_CHG_NZ, cpu9s12x , 0 },

	762 { "gldd", OP_IND16 \| OP_PAGE2, 3, 0xfc, 3, 3, CLR_V_CHG_NZ, cpu9s12x , 0 },

	763 { "gldd", OP_IDX \| OP_PAGE2, 2, 0xec, 3, 3, CLR_V_CHG_NZ, cpu9s1 2x, 0 },

	764 { "gldd", OP_IDX_1 \| OP_PAGE2, 3, 0xec, 3, 3, CLR_V_CHG_NZ, cpu9s1 2x, 0 },

	765 { "gldd", OP_IDX_2 \| OP_PAGE2, 4, 0xec, 4, 4, CLR_V_CHG_NZ, cpu9s1 2x, 0 },

	766 { "gldd", OP_D_IDX \| OP_PAGE2, 2, 0xec, 6, 6, CLR_V_CHG_NZ, cpu9s1 2x, 0 },

	767 { "gldd", OP_D_IDX_2 \| OP_PAGE2, 4, 0xec, 6, 6, CLR_V_CHG_NZ, cpu9s1 2x, 0 },

	768

	769 { "glds", OP_DIRECT \| OP_PAGE2, 2, 0xdf, 3, 3, CLR_V_CHG_NZ, cpu9s12x , 0 },

	770 { "glds", OP_IND16 \| OP_PAGE2, 3, 0xff, 3, 3, CLR_V_CHG_NZ, cpu9s12x , 0 },

	771 { "glds", OP_IDX \| OP_PAGE2, 2, 0xef, 3, 3, CLR_V_CHG_NZ, cpu9s1 2x, 0 },

	772 { "glds", OP_IDX_1 \| OP_PAGE2, 3, 0xef, 3, 3, CLR_V_CHG_NZ, cpu9s1 2x, 0 },

	773 { "glds", OP_IDX_2 \| OP_PAGE2, 4, 0xef, 4, 4, CLR_V_CHG_NZ, cpu9s1 2x, 0 },

	774 { "glds", OP_D_IDX \| OP_PAGE2, 2, 0xef, 6, 6, CLR_V_CHG_NZ, cpu9s1 2x, 0 },

	775 { "glds", OP_D_IDX_2 \| OP_PAGE2, 4, 0xef, 6, 6, CLR_V_CHG_NZ, cpu9s1 2x, 0 },

	776

	777 { "gldx", OP_DIRECT \| OP_PAGE2, 2, 0xde, 3, 3, CLR_V_CHG_NZ, cpu9s12x , 0 },

	778 { "gldx", OP_IND16 \| OP_PAGE2, 3, 0xfe, 3, 3, CLR_V_CHG_NZ, cpu9s12x , 0 },

	779 { "gldx", OP_IDX \| OP_PAGE2, 2, 0xee, 3, 3, CLR_V_CHG_NZ, cpu9s1 2x, 0 },

	780 { "gldx", OP_IDX_1 \| OP_PAGE2, 3, 0xee, 3, 3, CLR_V_CHG_NZ, cpu9s1 2x, 0 },

	781 { "gldx", OP_IDX_2 \| OP_PAGE2, 4, 0xee, 4, 4, CLR_V_CHG_NZ, cpu9s1 2x, 0 },

	782 { "gldx", OP_D_IDX \| OP_PAGE2, 2, 0xee, 6, 6, CLR_V_CHG_NZ, cpu9s1 2x, 0 },

	783 { "gldx", OP_D_IDX_2 \| OP_PAGE2, 4, 0xee, 6, 6, CLR_V_CHG_NZ, cpu9s1 2x, 0 },

	784

	785 { "gldy", OP_DIRECT \| OP_PAGE2, 2, 0xdd, 3, 3, CLR_V_CHG_NZ, cpu9s12x , 0 },

	786 { "gldy", OP_IND16 \| OP_PAGE2, 3, 0xfd, 3, 3, CLR_V_CHG_NZ, cpu9s12x , 0 },

	787 { "gldy", OP_IDX \| OP_PAGE2, 2, 0xed, 3, 3, CLR_V_CHG_NZ, cpu9s1 2x, 0 },

	788 { "gldy", OP_IDX_1 \| OP_PAGE2, 3, 0xed, 3, 3, CLR_V_CHG_NZ, cpu9s1 2x, 0 },

	789 { "gldy", OP_IDX_2 \| OP_PAGE2, 4, 0xed, 4, 4, CLR_V_CHG_NZ, cpu9s1 2x, 0 },

	790 { "gldy", OP_D_IDX \| OP_PAGE2, 2, 0xed, 6, 6, CLR_V_CHG_NZ, cpu9s1 2x, 0 },

	791 { "gldy", OP_D_IDX_2 \| OP_PAGE2, 4, 0xed, 6, 6, CLR_V_CHG_NZ, cpu9s1 2x, 0 },

	792

	793 { "gstaa", OP_DIRECT \| OP_PAGE2, 2, 0x5a, 3, 3, CLR_V_CHG_NZ, cpu9s12 x, 0 },

	794 { "gstaa", OP_IND16 \| OP_PAGE2, 3, 0x7a, 3, 3, CLR_V_CHG_NZ, cpu9s12 x, 0 },

	795 { "gstaa", OP_IDX \| OP_PAGE2, 2, 0x6a, 3, 3, CLR_V_CHG_NZ, cpu9s 12x, 0 },

	796 { "gstaa", OP_IDX_1 \| OP_PAGE2, 3, 0x6a, 3, 3, CLR_V_CHG_NZ, cpu9s 12x, 0 },

	797 { "gstaa", OP_IDX_2 \| OP_PAGE2, 4, 0x6a, 4, 4, CLR_V_CHG_NZ, cpu9s 12x, 0 },

	798 { "gstaa", OP_D_IDX \| OP_PAGE2, 2, 0x6a, 6, 6, CLR_V_CHG_NZ, cpu9s 12x, 0 },

	799 { "gstaa", OP_D_IDX_2 \| OP_PAGE2, 4, 0x6a, 6, 6, CLR_V_CHG_NZ, cpu9s 12x, 0 },

	800

	801 { "gstab", OP_DIRECT \| OP_PAGE2, 2, 0x5b, 3, 3, CLR_V_CHG_NZ, cpu9s12 x, 0 },

	802 { "gstab", OP_IND16 \| OP_PAGE2, 3, 0x7b, 3, 3, CLR_V_CHG_NZ, cpu9s12 x, 0 },

	803 { "gstab", OP_IDX \| OP_PAGE2, 2, 0x6b, 3, 3, CLR_V_CHG_NZ, cpu9s 12x, 0 },

	804 { "gstab", OP_IDX_1 \| OP_PAGE2, 3, 0x6b, 3, 3, CLR_V_CHG_NZ, cpu9s 12x, 0 },

	805 { "gstab", OP_IDX_2 \| OP_PAGE2, 4, 0x6b, 4, 4, CLR_V_CHG_NZ, cpu9s 12x, 0 },

	806 { "gstab", OP_D_IDX \| OP_PAGE2, 2, 0x6b, 6, 6, CLR_V_CHG_NZ, cpu9s 12x, 0 },

	807 { "gstab", OP_D_IDX_2 \| OP_PAGE2, 4, 0x6b, 6, 6, CLR_V_CHG_NZ, cpu9s 12x, 0 },

	808

	809 { "gstd", OP_DIRECT \| OP_PAGE2, 2, 0x5c, 3, 3, CLR_V_CHG_NZ, cpu9s12x , 0 },

	810 { "gstd", OP_IND16 \| OP_PAGE2, 3, 0x7c, 3, 3, CLR_V_CHG_NZ, cpu9s12x , 0 },

	811 { "gstd", OP_IDX \| OP_PAGE2, 2, 0x6c, 3, 3, CLR_V_CHG_NZ, cpu9s1 2x, 0 },

	812 { "gstd", OP_IDX_1 \| OP_PAGE2, 3, 0x6c, 3, 3, CLR_V_CHG_NZ, cpu9s1 2x, 0 },

	813 { "gstd", OP_IDX_2 \| OP_PAGE2, 4, 0x6c, 4, 4, CLR_V_CHG_NZ, cpu9s1 2x, 0 },

	814 { "gstd", OP_D_IDX \| OP_PAGE2, 2, 0x6c, 6, 6, CLR_V_CHG_NZ, cpu9s1 2x, 0 },

	815 { "gstd", OP_D_IDX_2 \| OP_PAGE2, 4, 0x6c, 6, 6, CLR_V_CHG_NZ, cpu9s1 2x, 0 },

	816

	817 { "gsts", OP_DIRECT \| OP_PAGE2, 2, 0x5f, 3, 3, CLR_V_CHG_NZ, cpu9s12x , 0 },

	818 { "gsts", OP_IND16 \| OP_PAGE2, 3, 0x6f, 3, 3, CLR_V_CHG_NZ, cpu9s12x , 0 },

	819 { "gsts", OP_IDX \| OP_PAGE2, 2, 0x6f, 3, 3, CLR_V_CHG_NZ, cpu9s1 2x, 0 },

	820 { "gsts", OP_IDX_1 \| OP_PAGE2, 3, 0x6f, 3, 3, CLR_V_CHG_NZ, cpu9s1 2x, 0 },

	821 { "gsts", OP_IDX_2 \| OP_PAGE2, 4, 0x6f, 4, 4, CLR_V_CHG_NZ, cpu9s1 2x, 0 },

	822 { "gsts", OP_D_IDX \| OP_PAGE2, 2, 0x6f, 6, 6, CLR_V_CHG_NZ, cpu9s1 2x, 0 },

	823 { "gsts", OP_D_IDX_2 \| OP_PAGE2, 4, 0x6f, 6, 6, CLR_V_CHG_NZ, cpu9s1 2x, 0 },

	824

	825 { "gstx", OP_DIRECT \| OP_PAGE2, 2, 0x5e, 3, 3, CLR_V_CHG_NZ, cpu9s12x , 0 },

	826 { "gstx", OP_IND16 \| OP_PAGE2, 3, 0x7e, 3, 3, CLR_V_CHG_NZ, cpu9s12x , 0 },

	827 { "gstx", OP_IDX \| OP_PAGE2, 2, 0x6e, 3, 3, CLR_V_CHG_NZ, cpu9s1 2x, 0 },

	828 { "gstx", OP_IDX_1 \| OP_PAGE2, 3, 0x6e, 3, 3, CLR_V_CHG_NZ, cpu9s1 2x, 0 },

	829 { "gstx", OP_IDX_2 \| OP_PAGE2, 4, 0x6e, 4, 4, CLR_V_CHG_NZ, cpu9s1 2x, 0 },

	830 { "gstx", OP_D_IDX \| OP_PAGE2, 2, 0x6e, 6, 6, CLR_V_CHG_NZ, cpu9s1 2x, 0 },

	831 { "gstx", OP_D_IDX_2 \| OP_PAGE2, 4, 0x6e, 6, 6, CLR_V_CHG_NZ, cpu9s1 2x, 0 },

	832

	833 { "gsty", OP_DIRECT \| OP_PAGE2, 2, 0x5d, 3, 3, CLR_V_CHG_NZ, cpu9s12x , 0 },

	834 { "gsty", OP_IND16 \| OP_PAGE2, 3, 0x7d, 3, 3, CLR_V_CHG_NZ, cpu9s12x , 0 },

	835 { "gsty", OP_IDX \| OP_PAGE2, 2, 0x6d, 3, 3, CLR_V_CHG_NZ, cpu9s1 2x, 0 },

	836 { "gsty", OP_IDX_1 \| OP_PAGE2, 3, 0x6d, 3, 3, CLR_V_CHG_NZ, cpu9s1 2x, 0 },

	837 { "gsty", OP_IDX_2 \| OP_PAGE2, 4, 0x6d, 4, 4, CLR_V_CHG_NZ, cpu9s1 2x, 0 },

	838 { "gsty", OP_D_IDX \| OP_PAGE2, 2, 0x6d, 6, 6, CLR_V_CHG_NZ, cpu9s1 2x, 0 },

	839 { "gsty", OP_D_IDX_2 \| OP_PAGE2, 4, 0x6d, 6, 6, CLR_V_CHG_NZ, cpu9s1 2x, 0 },

544	840

545 { "ibeq", OP_IBEQ_MARKER	841 { "ibeq", OP_IBEQ_MARKER

546 \| OP_REG \| OP_JUMP_REL, 3, 0x04, 3, 3, CHG_NONE, cpu6812 },	842 \| OP_REG \| OP_JUMP_REL, 3, 0x04, 3, 3, CHG_NONE, cpu6812\|cpu9s12x, 0 },

547 { "ibne", OP_IBNE_MARKER	843 { "ibne", OP_IBNE_MARKER

548 \| OP_REG \| OP_JUMP_REL, 3, 0x04, 3, 3, CHG_NONE, cpu6812 },	844 \| OP_REG \| OP_JUMP_REL, 3, 0x04, 3, 3, CHG_NONE, cpu6812\|cpu9s12x, 0 },

549	845

550 { "idiv", OP_NONE, 1, 0x02, 3, 41, CLR_V_CHG_ZC, cpu6811},	846 { "idiv", OP_NONE, 1, 0x02, 3, 41, CLR_V_CHG_ZC, cpu6811, 0 },

551 { "idiv", OP_NONE \| OP_PAGE2, 2, 0x10, 12, 12, CLR_V_CHG_ZC, cpu6812 },	847 { "idiv", OP_NONE \| OP_PAGE2, 2, 0x10, 12, 12, CLR_V_CHG_ZC, cpu6812\|cpu9s12 x, 0 },

552 { "idivs", OP_NONE \| OP_PAGE2, 2, 0x15, 12, 12, CHG_NZVC, cpu6812 },	848 { "idivs", OP_NONE \| OP_PAGE2, 2, 0x15, 12, 12, CHG_NZVC, cpu6812\|cpu9s12x, 0 },

553	849

554 { "inc", OP_IX, 2, 0x6c, 6, 6, CHG_NZV, cpu6811 },	850 { "inc", OP_IX, 2, 0x6c, 6, 6, CHG_NZV, cpu6811, 0 },

555 { "inc", OP_IND16, 3, 0x7c, 6, 6, CHG_NZV, cpu6811 },	851 { "inc", OP_IND16, 3, 0x7c, 6, 6, CHG_NZV, cpu6811, 0 },

556 { "inc", OP_IY \| OP_PAGE2, 3, 0x6c, 7, 7, CHG_NZV, cpu6811 },	852 { "inc", OP_IY \| OP_PAGE2, 3, 0x6c, 7, 7, CHG_NZV, cpu6811, 0 },

557 { "inc", OP_IND16, 3, 0x72, 4, 4, CHG_NZV, cpu6812 },	853 { "inc", OP_IND16, 3, 0x72, 4, 4, CHG_NZV, cpu6812\|cpu9s12x, 0 },

558 { "inc", OP_IDX, 2, 0x62, 3, 3, CHG_NZV, cpu6812 },	854 { "inc", OP_IDX, 2, 0x62, 3, 3, CHG_NZV, cpu6812\|cpu9s12x, 0 },

559 { "inc", OP_IDX_1, 3, 0x62, 4, 4, CHG_NZV, cpu6812 },	855 { "inc", OP_IDX_1, 3, 0x62, 4, 4, CHG_NZV, cpu6812\|cpu9s12x, 0 },

560 { "inc", OP_IDX_2, 4, 0x62, 5, 5, CHG_NZV, cpu6812 },	856 { "inc", OP_IDX_2, 4, 0x62, 5, 5, CHG_NZV, cpu6812\|cpu9s12x, 0 },

561 { "inc", OP_D_IDX, 2, 0x62, 6, 6, CHG_NZV, cpu6812 },	857 { "inc", OP_D_IDX, 2, 0x62, 6, 6, CHG_NZV, cpu6812\|cpu9s12x, 0 },

562 { "inc", OP_D_IDX_2, 4, 0x62, 6, 6, CHG_NZV, cpu6812 },	858 { "inc", OP_D_IDX_2, 4, 0x62, 6, 6, CHG_NZV, cpu6812\|cpu9s12x, 0 },

563	859

564 { "inca", OP_NONE, 1, 0x4c, 2, 2, CHG_NZV, cpu6811 },	860 { "inca", OP_NONE, 1, 0x4c, 2, 2, CHG_NZV, cpu6811, 0 },

565 { "inca", OP_NONE, 1, 0x42, 1, 1, CHG_NZV, cpu6812 },	861 { "inca", OP_NONE, 1, 0x42, 1, 1, CHG_NZV, cpu6812\|cpu9s12x, 0 },

566 { "incb", OP_NONE, 1, 0x5c, 2, 2, CHG_NZV, cpu6811 },	862 { "incb", OP_NONE, 1, 0x5c, 2, 2, CHG_NZV, cpu6811, 0 },

567 { "incb", OP_NONE, 1, 0x52, 1, 1, CHG_NZV, cpu6812 },	863 { "incb", OP_NONE, 1, 0x52, 1, 1, CHG_NZV, cpu6812\|cpu9s12x, 0 },

568	864

569 { "ins", OP_NONE, 1, 0x31, 3, 3, CHG_NONE, cpu6811 },	865 { "incw", OP_IND16 \| OP_PAGE2, 3, 0x72, 4, 4, CHG_NZV, cpu9s12x, 0 },

570	866 { "incw", OP_IDX \| OP_PAGE2, 2, 0x62, 3, 3, CHG_NZV, cpu9s12x, 0 },

571 { "inx", OP_NONE, 1, 0x08, 1, 1, CHG_Z, cpu6811\|cpu6812 },	867 { "incw", OP_IDX_1 \| OP_PAGE2, 3, 0x62, 4, 4, CHG_NZV, cpu9s12x, 0 },

572 { "iny", OP_NONE \|OP_PAGE2, 2, 0x08, 4, 4, CHG_Z, cpu6811 },	868 { "incw", OP_IDX_2 \| OP_PAGE2, 4, 0x62, 5, 5, CHG_NZV, cpu9s12x, 0 },

573 { "iny", OP_NONE, 1, 0x02, 1, 1, CHG_Z, cpu6812 },	869 { "incw", OP_D_IDX \| OP_PAGE2, 2, 0x62, 6, 6, CHG_NZV, cpu9s12x, 0 },

574	870 { "incw", OP_D_IDX_2 \| OP_PAGE2, 4, 0x62, 6, 6, CHG_NZV, cpu9s12x, 0 },

575 { "jmp", OP_IND16 \| OP_BRANCH, 3, 0x7e, 3, 3, CHG_NONE, cpu6811 },	871

576 { "jmp", OP_IX, 2, 0x6e, 3, 3, CHG_NONE, cpu6811 },	872 { "incx", OP_NONE \| OP_PAGE2, 3, 0x42, 4, 4, CHG_NZV, cpu9s12x, 0 },

577 { "jmp", OP_IY \| OP_PAGE2, 3, 0x6e, 4, 4, CHG_NONE, cpu6811 },	873

578 { "jmp", OP_IND16 \| OP_BRANCH, 3, 0x06, 3, 3, CHG_NONE, cpu6812 },	874 { "incy", OP_NONE \| OP_PAGE2, 3, 0x52, 4, 4, CHG_NZV, cpu9s12x, 0 },

579 { "jmp", OP_IDX, 2, 0x05, 3, 3, CHG_NONE, cpu6812 },	875

580 { "jmp", OP_IDX_1, 3, 0x05, 3, 3, CHG_NONE, cpu6812 },	876 { "ins", OP_NONE, 1, 0x31, 3, 3, CHG_NONE, cpu6811, 0 },

581 { "jmp", OP_IDX_2, 4, 0x05, 4, 4, CHG_NONE, cpu6812 },	877

582 { "jmp", OP_D_IDX, 2, 0x05, 6, 6, CHG_NONE, cpu6812 },	878 { "inx", OP_NONE, 1, 0x08, 1, 1, CHG_Z, cpu6811\|cpu6812\|cpu9 s12x, 0 },

583 { "jmp", OP_D_IDX_2, 4, 0x05, 6, 6, CHG_NONE, cpu6812 },	879 { "iny", OP_NONE \|OP_PAGE2, 2, 0x08, 4, 4, CHG_Z, cpu6811, 0 },

584	880 { "iny", OP_NONE, 1, 0x02, 1, 1, CHG_Z, cpu6812\|cpu9s12x, 0 },

585 { "jsr", OP_DIRECT \| OP_BRANCH, 2, 0x9d, 5, 5, CHG_NONE, cpu6811 },	881

586 { "jsr", OP_IND16 \| OP_BRANCH, 3, 0xbd, 6, 6, CHG_NONE, cpu6811 },	882 { "jmp", OP_IND16 \| OP_BRANCH, 3, 0x7e, 3, 3, CHG_NONE, cpu6811, 0 },

587 { "jsr", OP_IX, 2, 0xad, 6, 6, CHG_NONE, cpu6811 },	883 { "jmp", OP_IX, 2, 0x6e, 3, 3, CHG_NONE, cpu6811, 0 },

588 { "jsr", OP_IY \| OP_PAGE2, 3, 0xad, 6, 6, CHG_NONE, cpu6811 },	884 { "jmp", OP_IY \| OP_PAGE2, 3, 0x6e, 4, 4, CHG_NONE, cpu6811, 0 },

589 { "jsr", OP_DIRECT \| OP_BRANCH, 2, 0x17, 4, 4, CHG_NONE, cpu6812 },	885 { "jmp", OP_IND16 \| OP_BRANCH, 3, 0x06, 3, 3, CHG_NONE, cpu6812\|cpu9s12x, 0 },

590 { "jsr", OP_IND16 \| OP_BRANCH, 3, 0x16, 4, 3, CHG_NONE, cpu6812 },	886 { "jmp", OP_IDX, 2, 0x05, 3, 3, CHG_NONE, cpu6812\|cpu9s12x, 0 },

591 { "jsr", OP_IDX, 2, 0x15, 4, 4, CHG_NONE, cpu6812 },	887 { "jmp", OP_IDX_1, 3, 0x05, 3, 3, CHG_NONE, cpu6812\|cpu9s12x, 0 },

592 { "jsr", OP_IDX_1, 3, 0x15, 4, 4, CHG_NONE, cpu6812 },	888 { "jmp", OP_IDX_2, 4, 0x05, 4, 4, CHG_NONE, cpu6812\|cpu9s12x, 0 },

593 { "jsr", OP_IDX_2, 4, 0x15, 5, 5, CHG_NONE, cpu6812 },	889 { "jmp", OP_D_IDX, 2, 0x05, 6, 6, CHG_NONE, cpu6812\|cpu9s12x, 0 },

594 { "jsr", OP_D_IDX, 2, 0x15, 7, 7, CHG_NONE, cpu6812 },	890 { "jmp", OP_D_IDX_2, 4, 0x05, 6, 6, CHG_NONE, cpu6812\|cpu9s12x, 0 },

595 { "jsr", OP_D_IDX_2, 4, 0x15, 7, 7, CHG_NONE, cpu6812 },	891

596	892 { "jsr", OP_DIRECT \| OP_BRANCH, 2, 0x9d, 5, 5, CHG_NONE, cpu6811, 0 },

597 { "lbcc", OP_JUMP_REL16 \| OP_PAGE2, 4, 0x24, 3, 4, CHG_NONE, cpu6812 },	893 { "jsr", OP_IND16 \| OP_BRANCH, 3, 0xbd, 6, 6, CHG_NONE, cpu6811, 0 },

598 { "lbcs", OP_JUMP_REL16 \| OP_PAGE2, 4, 0x25, 3, 4, CHG_NONE, cpu6812 },	894 { "jsr", OP_IX, 2, 0xad, 6, 6, CHG_NONE, cpu6811, 0 },

599 { "lbeq", OP_JUMP_REL16 \| OP_PAGE2, 4, 0x27, 3, 4, CHG_NONE, cpu6812 },	895 { "jsr", OP_IY \| OP_PAGE2, 3, 0xad, 6, 6, CHG_NONE, cpu6811, 0 },

600 { "lbge", OP_JUMP_REL16 \| OP_PAGE2, 4, 0x2c, 3, 4, CHG_NONE, cpu6812 },	896 { "jsr", OP_DIRECT \| OP_BRANCH, 2, 0x17, 4, 4, CHG_NONE, cpu6812\|cpu9s12x, 0 },

601 { "lbgt", OP_JUMP_REL16 \| OP_PAGE2, 4, 0x2e, 3, 4, CHG_NONE, cpu6812 },	897 { "jsr", OP_IND16 \| OP_BRANCH, 3, 0x16, 4, 3, CHG_NONE, cpu6812\|cpu9s12x, 0 },

602 { "lbhi", OP_JUMP_REL16 \| OP_PAGE2, 4, 0x22, 3, 4, CHG_NONE, cpu6812 },	898 { "jsr", OP_IDX, 2, 0x15, 4, 4, CHG_NONE, cpu6812\|cpu9s12x, 0 },

603 { "lbhs", OP_JUMP_REL16 \| OP_PAGE2, 4, 0x24, 3, 4, CHG_NONE, cpu6812 },	899 { "jsr", OP_IDX_1, 3, 0x15, 4, 4, CHG_NONE, cpu6812\|cpu9s12x, 0 },

604 { "lble", OP_JUMP_REL16 \| OP_PAGE2, 4, 0x2f, 3, 4, CHG_NONE, cpu6812 },	900 { "jsr", OP_IDX_2, 4, 0x15, 5, 5, CHG_NONE, cpu6812\|cpu9s12x, 0 },

605 { "lblo", OP_JUMP_REL16 \| OP_PAGE2, 4, 0x25, 3, 4, CHG_NONE, cpu6812 },	901 { "jsr", OP_D_IDX, 2, 0x15, 7, 7, CHG_NONE, cpu6812\|cpu9s12x, 0 },

606 { "lbls", OP_JUMP_REL16 \| OP_PAGE2, 4, 0x23, 3, 4, CHG_NONE, cpu6812 },	902 { "jsr", OP_D_IDX_2, 4, 0x15, 7, 7, CHG_NONE, cpu6812\|cpu9s12x, 0 },

607 { "lblt", OP_JUMP_REL16 \| OP_PAGE2, 4, 0x2d, 3, 4, CHG_NONE, cpu6812 },	903

608 { "lbmi", OP_JUMP_REL16 \| OP_PAGE2, 4, 0x2b, 3, 4, CHG_NONE, cpu6812 },	904 { "lbcc", OP_JUMP_REL16 \| OP_PAGE2, 4, 0x24, 3, 4, CHG_NONE, cpu6812\|cpu9s1 2x, 0 },

609 { "lbne", OP_JUMP_REL16 \| OP_PAGE2, 4, 0x26, 3, 4, CHG_NONE, cpu6812 },	905 { "lbcs", OP_JUMP_REL16 \| OP_PAGE2, 4, 0x25, 3, 4, CHG_NONE, cpu6812\|cpu9s1 2x, 0 },

610 { "lbpl", OP_JUMP_REL16 \| OP_PAGE2, 4, 0x2a, 3, 4, CHG_NONE, cpu6812 },	906 { "lbeq", OP_JUMP_REL16 \| OP_PAGE2, 4, 0x27, 3, 4, CHG_NONE, cpu6812\|cpu9s1 2x, 0 },

611 { "lbra", OP_JUMP_REL16 \| OP_PAGE2, 4, 0x20, 4, 4, CHG_NONE, cpu6812 },	907 { "lbge", OP_JUMP_REL16 \| OP_PAGE2, 4, 0x2c, 3, 4, CHG_NONE, cpu6812\|cpu9s1 2x, 0 },

612 { "lbrn", OP_JUMP_REL16 \| OP_PAGE2, 4, 0x21, 3, 3, CHG_NONE, cpu6812 },	908 { "lbgt", OP_JUMP_REL16 \| OP_PAGE2, 4, 0x2e, 3, 4, CHG_NONE, cpu6812\|cpu9s1 2x, 0 },

613 { "lbvc", OP_JUMP_REL16 \| OP_PAGE2, 4, 0x28, 3, 4, CHG_NONE, cpu6812 },	909 { "lbhi", OP_JUMP_REL16 \| OP_PAGE2, 4, 0x22, 3, 4, CHG_NONE, cpu6812\|cpu9s1 2x, 0 },

614 { "lbvs", OP_JUMP_REL16 \| OP_PAGE2, 4, 0x29, 3, 4, CHG_NONE, cpu6812 },	910 { "lbhs", OP_JUMP_REL16 \| OP_PAGE2, 4, 0x24, 3, 4, CHG_NONE, cpu6812\|cpu9s1 2x, 0 },

615	911 { "lble", OP_JUMP_REL16 \| OP_PAGE2, 4, 0x2f, 3, 4, CHG_NONE, cpu6812\|cpu9s1 2x, 0 },

616 { "ldaa", OP_IMM8, 2, 0x86, 1, 1, CLR_V_CHG_NZ, cpu6811\|cpu6812 },	912 { "lblo", OP_JUMP_REL16 \| OP_PAGE2, 4, 0x25, 3, 4, CHG_NONE, cpu6812\|cpu9s1 2x, 0 },

617 { "ldaa", OP_DIRECT, 2, 0x96, 3, 3, CLR_V_CHG_NZ, cpu6811\|cpu6812 },	913 { "lbls", OP_JUMP_REL16 \| OP_PAGE2, 4, 0x23, 3, 4, CHG_NONE, cpu6812\|cpu9s1 2x, 0 },

618 { "ldaa", OP_IND16, 3, 0xb6, 3, 3, CLR_V_CHG_NZ, cpu6811\|cpu6812 },	914 { "lblt", OP_JUMP_REL16 \| OP_PAGE2, 4, 0x2d, 3, 4, CHG_NONE, cpu6812\|cpu9s1 2x, 0 },

619 { "ldaa", OP_IX, 2, 0xa6, 4, 4, CLR_V_CHG_NZ, cpu6811 },	915 { "lbmi", OP_JUMP_REL16 \| OP_PAGE2, 4, 0x2b, 3, 4, CHG_NONE, cpu6812\|cpu9s1 2x, 0 },

620 { "ldaa", OP_IY \| OP_PAGE2, 3, 0xa6, 5, 5, CLR_V_CHG_NZ, cpu6811 },	916 { "lbne", OP_JUMP_REL16 \| OP_PAGE2, 4, 0x26, 3, 4, CHG_NONE, cpu6812\|cpu9s1 2x, 0 },

621 { "ldaa", OP_IDX, 2, 0xa6, 3, 3, CLR_V_CHG_NZ, cpu6812 },	917 { "lbpl", OP_JUMP_REL16 \| OP_PAGE2, 4, 0x2a, 3, 4, CHG_NONE, cpu6812\|cpu9s1 2x, 0 },

622 { "ldaa", OP_IDX_1, 3, 0xa6, 3, 3, CLR_V_CHG_NZ, cpu6812 },	918 { "lbra", OP_JUMP_REL16 \| OP_PAGE2, 4, 0x20, 4, 4, CHG_NONE, cpu6812\|cpu9s1 2x, 0 },

623 { "ldaa", OP_IDX_2, 4, 0xa6, 4, 4, CLR_V_CHG_NZ, cpu6812 },	919 { "lbrn", OP_JUMP_REL16 \| OP_PAGE2, 4, 0x21, 3, 3, CHG_NONE, cpu6812\|cpu9s1 2x, 0 },

624 { "ldaa", OP_D_IDX, 2, 0xa6, 6, 6, CLR_V_CHG_NZ, cpu6812 },	920 { "lbvc", OP_JUMP_REL16 \| OP_PAGE2, 4, 0x28, 3, 4, CHG_NONE, cpu6812\|cpu9s1 2x, 0 },

625 { "ldaa", OP_D_IDX_2, 4, 0xa6, 6, 6, CLR_V_CHG_NZ, cpu6812 },	921 { "lbvs", OP_JUMP_REL16 \| OP_PAGE2, 4, 0x29, 3, 4, CHG_NONE, cpu6812\|cpu9s1 2x, 0 },

626	922

627 { "ldab", OP_IMM8, 2, 0xc6, 1, 1, CLR_V_CHG_NZ, cpu6811\|cpu6812 },	923 { "ldaa", OP_IMM8, 2, 0x86, 1, 1, CLR_V_CHG_NZ, cpu6811\|cpu6812\|cpu 9s12x, 0 },

628 { "ldab", OP_DIRECT, 2, 0xd6, 3, 3, CLR_V_CHG_NZ, cpu6811\|cpu6812 },	924 { "ldaa", OP_DIRECT, 2, 0x96, 3, 3, CLR_V_CHG_NZ, cpu6811\|cpu6812\|cpu 9s12x, 0 },

629 { "ldab", OP_IND16, 3, 0xf6, 3, 3, CLR_V_CHG_NZ, cpu6811\|cpu6812 },	925 { "ldaa", OP_IND16, 3, 0xb6, 3, 3, CLR_V_CHG_NZ, cpu6811\|cpu6812\|cpu 9s12x, 0 },

630 { "ldab", OP_IX, 2, 0xe6, 4, 4, CLR_V_CHG_NZ, cpu6811 },	926 { "ldaa", OP_IX, 2, 0xa6, 4, 4, CLR_V_CHG_NZ, cpu6811, 0 },

631 { "ldab", OP_IY \| OP_PAGE2, 3, 0xe6, 5, 5, CLR_V_CHG_NZ, cpu6811 },	927 { "ldaa", OP_IY \| OP_PAGE2, 3, 0xa6, 5, 5, CLR_V_CHG_NZ, cpu6811, 0 },

632 { "ldab", OP_IDX, 2, 0xe6, 3, 3, CLR_V_CHG_NZ, cpu6812 },	928 { "ldaa", OP_IDX, 2, 0xa6, 3, 3, CLR_V_CHG_NZ, cpu6812\|cpu9s12x, 0 },

633 { "ldab", OP_IDX_1, 3, 0xe6, 3, 3, CLR_V_CHG_NZ, cpu6812 },	929 { "ldaa", OP_IDX_1, 3, 0xa6, 3, 3, CLR_V_CHG_NZ, cpu6812\|cpu9s12x, 0 },

634 { "ldab", OP_IDX_2, 4, 0xe6, 4, 4, CLR_V_CHG_NZ, cpu6812 },	930 { "ldaa", OP_IDX_2, 4, 0xa6, 4, 4, CLR_V_CHG_NZ, cpu6812\|cpu9s12x, 0 },

635 { "ldab", OP_D_IDX, 2, 0xe6, 6, 6, CLR_V_CHG_NZ, cpu6812 },	931 { "ldaa", OP_D_IDX, 2, 0xa6, 6, 6, CLR_V_CHG_NZ, cpu6812\|cpu9s12x, 0 },

636 { "ldab", OP_D_IDX_2, 4, 0xe6, 6, 6, CLR_V_CHG_NZ, cpu6812 },	932 { "ldaa", OP_D_IDX_2, 4, 0xa6, 6, 6, CLR_V_CHG_NZ, cpu6812\|cpu9s12x, 0 },

637	933

638 { "ldd", OP_IMM16, 3, 0xcc, 2, 2, CLR_V_CHG_NZ, cpu6811\|cpu6812 },	934 { "ldab", OP_IMM8, 2, 0xc6, 1, 1, CLR_V_CHG_NZ, cpu6811\|cpu6812\|cpu 9s12x, 0 },

639 { "ldd", OP_DIRECT, 2, 0xdc, 3, 3, CLR_V_CHG_NZ, cpu6811\|cpu6812 },	935 { "ldab", OP_DIRECT, 2, 0xd6, 3, 3, CLR_V_CHG_NZ, cpu6811\|cpu6812\|cpu 9s12x, 0 },

640 { "ldd", OP_IND16, 3, 0xfc, 3, 3, CLR_V_CHG_NZ, cpu6811\|cpu6812 },	936 { "ldab", OP_IND16, 3, 0xf6, 3, 3, CLR_V_CHG_NZ, cpu6811\|cpu6812\|cpu 9s12x, 0 },

641 { "ldd", OP_IX, 2, 0xec, 5, 5, CLR_V_CHG_NZ, cpu6811 },	937 { "ldab", OP_IX, 2, 0xe6, 4, 4, CLR_V_CHG_NZ, cpu6811, 0 },

642 { "ldd", OP_IY \| OP_PAGE2, 3, 0xec, 6, 6, CLR_V_CHG_NZ, cpu6811 },	938 { "ldab", OP_IY \| OP_PAGE2, 3, 0xe6, 5, 5, CLR_V_CHG_NZ, cpu6811, 0 },

643 { "ldd", OP_IDX, 2, 0xec, 3, 3, CLR_V_CHG_NZ, cpu6812 },	939 { "ldab", OP_IDX, 2, 0xe6, 3, 3, CLR_V_CHG_NZ, cpu6812\|cpu9s12x, 0 },

644 { "ldd", OP_IDX_1, 3, 0xec, 3, 3, CLR_V_CHG_NZ, cpu6812 },	940 { "ldab", OP_IDX_1, 3, 0xe6, 3, 3, CLR_V_CHG_NZ, cpu6812\|cpu9s12x, 0 },

645 { "ldd", OP_IDX_2, 4, 0xec, 4, 4, CLR_V_CHG_NZ, cpu6812 },	941 { "ldab", OP_IDX_2, 4, 0xe6, 4, 4, CLR_V_CHG_NZ, cpu6812\|cpu9s12x, 0 },

646 { "ldd", OP_D_IDX, 2, 0xec, 6, 6, CLR_V_CHG_NZ, cpu6812 },	942 { "ldab", OP_D_IDX, 2, 0xe6, 6, 6, CLR_V_CHG_NZ, cpu6812\|cpu9s12x, 0 },

647 { "ldd", OP_D_IDX_2, 4, 0xec, 6, 6, CLR_V_CHG_NZ, cpu6812 },	943 { "ldab", OP_D_IDX_2, 4, 0xe6, 6, 6, CLR_V_CHG_NZ, cpu6812\|cpu9s12x, 0 },

648	944

649 { "lds", OP_IMM16, 3, 0x8e, 3, 3, CLR_V_CHG_NZ, cpu6811 },	945 { "ldd", OP_IMM16, 3, 0xcc, 2, 2, CLR_V_CHG_NZ, cpu6811\|cpu6812\|cpu 9s12x, 0 },

650 { "lds", OP_DIRECT, 2, 0x9e, 4, 4, CLR_V_CHG_NZ, cpu6811 },	946 { "ldd", OP_DIRECT, 2, 0xdc, 3, 3, CLR_V_CHG_NZ, cpu6811\|cpu6812\|cpu 9s12x, 0 },

651 { "lds", OP_IND16, 3, 0xbe, 5, 5, CLR_V_CHG_NZ, cpu6811 },	947 { "ldd", OP_IND16, 3, 0xfc, 3, 3, CLR_V_CHG_NZ, cpu6811\|cpu6812\|cpu 9s12x, 0 },

652 { "lds", OP_IX, 2, 0xae, 5, 5, CLR_V_CHG_NZ, cpu6811 },	948 { "ldd", OP_IX, 2, 0xec, 5, 5, CLR_V_CHG_NZ, cpu6811, 0 },

653 { "lds", OP_IY \| OP_PAGE2, 3, 0xae, 6, 6, CLR_V_CHG_NZ, cpu6811 },	949 { "ldd", OP_IY \| OP_PAGE2, 3, 0xec, 6, 6, CLR_V_CHG_NZ, cpu6811, 0 },

654 { "lds", OP_IMM16, 3, 0xcf, 2, 2, CLR_V_CHG_NZ, cpu6812 },	950 { "ldd", OP_IDX, 2, 0xec, 3, 3, CLR_V_CHG_NZ, cpu6812\|cpu9s12x, 0 },

655 { "lds", OP_DIRECT, 2, 0xdf, 3, 3, CLR_V_CHG_NZ, cpu6812 },	951 { "ldd", OP_IDX_1, 3, 0xec, 3, 3, CLR_V_CHG_NZ, cpu6812\|cpu9s12x, 0 },

656 { "lds", OP_IND16, 3, 0xff, 3, 3, CLR_V_CHG_NZ, cpu6812 },	952 { "ldd", OP_IDX_2, 4, 0xec, 4, 4, CLR_V_CHG_NZ, cpu6812\|cpu9s12x, 0 },

657 { "lds", OP_IDX, 2, 0xef, 3, 3, CLR_V_CHG_NZ, cpu6812 },	953 { "ldd", OP_D_IDX, 2, 0xec, 6, 6, CLR_V_CHG_NZ, cpu6812\|cpu9s12x, 0 },

658 { "lds", OP_IDX_1, 3, 0xef, 3, 3, CLR_V_CHG_NZ, cpu6812 },	954 { "ldd", OP_D_IDX_2, 4, 0xec, 6, 6, CLR_V_CHG_NZ, cpu6812\|cpu9s12x, 0 },

659 { "lds", OP_IDX_2, 4, 0xef, 4, 4, CLR_V_CHG_NZ, cpu6812 },	955

660 { "lds", OP_D_IDX, 2, 0xef, 6, 6, CLR_V_CHG_NZ, cpu6812 },	956 { "lds", OP_IMM16, 3, 0x8e, 3, 3, CLR_V_CHG_NZ, cpu6811, 0 },

661 { "lds", OP_D_IDX_2, 4, 0xef, 6, 6, CLR_V_CHG_NZ, cpu6812 },	957 { "lds", OP_DIRECT, 2, 0x9e, 4, 4, CLR_V_CHG_NZ, cpu6811, 0 },

662	958 { "lds", OP_IND16, 3, 0xbe, 5, 5, CLR_V_CHG_NZ, cpu6811, 0 },

663 { "ldx", OP_IMM16, 3, 0xce, 2, 2, CLR_V_CHG_NZ, cpu6811\|cpu6812 },	959 { "lds", OP_IX, 2, 0xae, 5, 5, CLR_V_CHG_NZ, cpu6811, 0 },

664 { "ldx", OP_DIRECT, 2, 0xde, 3, 3, CLR_V_CHG_NZ, cpu6811\|cpu6812 },	960 { "lds", OP_IY \| OP_PAGE2, 3, 0xae, 6, 6, CLR_V_CHG_NZ, cpu6811, 0 },

665 { "ldx", OP_IND16, 3, 0xfe, 3, 3, CLR_V_CHG_NZ, cpu6811\|cpu6812 },	961 { "lds", OP_IMM16, 3, 0xcf, 2, 2, CLR_V_CHG_NZ, cpu6812\|cpu9s12x, 0 },

666 { "ldx", OP_IX, 2, 0xee, 5, 5, CLR_V_CHG_NZ, cpu6811 },	962 { "lds", OP_DIRECT, 2, 0xdf, 3, 3, CLR_V_CHG_NZ, cpu6812\|cpu9s12x, 0 },

667 { "ldx", OP_IY \| OP_PAGE4, 3, 0xee, 6, 6, CLR_V_CHG_NZ, cpu6811 },	963 { "lds", OP_IND16, 3, 0xff, 3, 3, CLR_V_CHG_NZ, cpu6812\|cpu9s12x, 0 },

668 { "ldx", OP_IDX, 2, 0xee, 3, 3, CLR_V_CHG_NZ, cpu6812 },	964 { "lds", OP_IDX, 2, 0xef, 3, 3, CLR_V_CHG_NZ, cpu6812\|cpu9s12x, 0 },

669 { "ldx", OP_IDX_1, 3, 0xee, 3, 3, CLR_V_CHG_NZ, cpu6812 },	965 { "lds", OP_IDX_1, 3, 0xef, 3, 3, CLR_V_CHG_NZ, cpu6812\|cpu9s12x, 0 },

670 { "ldx", OP_IDX_2, 4, 0xee, 4, 4, CLR_V_CHG_NZ, cpu6812 },	966 { "lds", OP_IDX_2, 4, 0xef, 4, 4, CLR_V_CHG_NZ, cpu6812\|cpu9s12x, 0 },

671 { "ldx", OP_D_IDX, 2, 0xee, 6, 6, CLR_V_CHG_NZ, cpu6812 },	967 { "lds", OP_D_IDX, 2, 0xef, 6, 6, CLR_V_CHG_NZ, cpu6812\|cpu9s12x, 0 },

672 { "ldx", OP_D_IDX_2, 4, 0xee, 6, 6, CLR_V_CHG_NZ, cpu6812 },	968 { "lds", OP_D_IDX_2, 4, 0xef, 6, 6, CLR_V_CHG_NZ, cpu6812\|cpu9s12x, 0 },

673	969

674 { "ldy", OP_IMM16 \| OP_PAGE2, 4, 0xce, 4, 4, CLR_V_CHG_NZ, cpu6811 },	970 { "ldx", OP_IMM16, 3, 0xce, 2, 2, CLR_V_CHG_NZ, cpu6811\|cpu6812\|cpu 9s12x, 0 },

675 { "ldy", OP_DIRECT \| OP_PAGE2, 3, 0xde, 5, 5, CLR_V_CHG_NZ, cpu6811 },	971 { "ldx", OP_DIRECT, 2, 0xde, 3, 3, CLR_V_CHG_NZ, cpu6811\|cpu6812\|cpu 9s12x, 0 },

676 { "ldy", OP_IND16 \| OP_PAGE2, 4, 0xfe, 6, 6, CLR_V_CHG_NZ, cpu6811 },	972 { "ldx", OP_IND16, 3, 0xfe, 3, 3, CLR_V_CHG_NZ, cpu6811\|cpu6812\|cpu 9s12x, 0 },

677 { "ldy", OP_IX \| OP_PAGE3, 3, 0xee, 6, 6, CLR_V_CHG_NZ, cpu6811 },	973 { "ldx", OP_IX, 2, 0xee, 5, 5, CLR_V_CHG_NZ, cpu6811, 0 },

678 { "ldy", OP_IY \| OP_PAGE2, 3, 0xee, 6, 6, CLR_V_CHG_NZ, cpu6811 },	974 { "ldx", OP_IY \| OP_PAGE4, 3, 0xee, 6, 6, CLR_V_CHG_NZ, cpu6811, 0 },

679 { "ldy", OP_IMM16, 3, 0xcd, 2, 2, CLR_V_CHG_NZ, cpu6812 },	975 { "ldx", OP_IDX, 2, 0xee, 3, 3, CLR_V_CHG_NZ, cpu6812\|cpu9s12x, 0 },

680 { "ldy", OP_DIRECT, 2, 0xdd, 3, 3, CLR_V_CHG_NZ, cpu6812 },	976 { "ldx", OP_IDX_1, 3, 0xee, 3, 3, CLR_V_CHG_NZ, cpu6812\|cpu9s12x, 0 },

681 { "ldy", OP_IND16, 3, 0xfd, 3, 3, CLR_V_CHG_NZ, cpu6812 },	977 { "ldx", OP_IDX_2, 4, 0xee, 4, 4, CLR_V_CHG_NZ, cpu6812\|cpu9s12x, 0 },

682 { "ldy", OP_IDX, 2, 0xed, 3, 3, CLR_V_CHG_NZ, cpu6812 },	978 { "ldx", OP_D_IDX, 2, 0xee, 6, 6, CLR_V_CHG_NZ, cpu6812\|cpu9s12x, 0 },

683 { "ldy", OP_IDX_1, 3, 0xed, 3, 3, CLR_V_CHG_NZ, cpu6812 },	979 { "ldx", OP_D_IDX_2, 4, 0xee, 6, 6, CLR_V_CHG_NZ, cpu6812\|cpu9s12x, 0 },

684 { "ldy", OP_IDX_2, 4, 0xed, 4, 4, CLR_V_CHG_NZ, cpu6812 },	980

685 { "ldy", OP_D_IDX, 2, 0xed, 6, 6, CLR_V_CHG_NZ, cpu6812 },	981 { "ldy", OP_IMM16 \| OP_PAGE2, 4, 0xce, 4, 4, CLR_V_CHG_NZ, cpu6811, 0 },

686 { "ldy", OP_D_IDX_2, 4, 0xed, 6, 6, CLR_V_CHG_NZ, cpu6812 },	982 { "ldy", OP_DIRECT \| OP_PAGE2, 3, 0xde, 5, 5, CLR_V_CHG_NZ, cpu6811, 0 },

687	983 { "ldy", OP_IND16 \| OP_PAGE2, 4, 0xfe, 6, 6, CLR_V_CHG_NZ, cpu6811, 0 },

688 { "leas", OP_IDX, 2, 0x1b, 2, 2, CHG_NONE, cpu6812 },	984 { "ldy", OP_IX \| OP_PAGE3, 3, 0xee, 6, 6, CLR_V_CHG_NZ, cpu6811, 0 },

689 { "leas", OP_IDX_1, 3, 0x1b, 2, 2, CHG_NONE, cpu6812 },	985 { "ldy", OP_IY \| OP_PAGE2, 3, 0xee, 6, 6, CLR_V_CHG_NZ, cpu6811, 0 },

690 { "leas", OP_IDX_2, 4, 0x1b, 2, 2, CHG_NONE, cpu6812 },	986 { "ldy", OP_IMM16, 3, 0xcd, 2, 2, CLR_V_CHG_NZ, cpu6812\|cpu9s12x, 0 },

691	987 { "ldy", OP_DIRECT, 2, 0xdd, 3, 3, CLR_V_CHG_NZ, cpu6812\|cpu9s12x, 0 },

692 { "leax", OP_IDX, 2, 0x1a, 2, 2, CHG_NONE, cpu6812 },	988 { "ldy", OP_IND16, 3, 0xfd, 3, 3, CLR_V_CHG_NZ, cpu6812\|cpu9s12x, 0 },

693 { "leax", OP_IDX_1, 3, 0x1a, 2, 2, CHG_NONE, cpu6812 },	989 { "ldy", OP_IDX, 2, 0xed, 3, 3, CLR_V_CHG_NZ, cpu6812\|cpu9s12x, 0 },

694 { "leax", OP_IDX_2, 4, 0x1a, 2, 2, CHG_NONE, cpu6812 },	990 { "ldy", OP_IDX_1, 3, 0xed, 3, 3, CLR_V_CHG_NZ, cpu6812\|cpu9s12x, 0 },

695	991 { "ldy", OP_IDX_2, 4, 0xed, 4, 4, CLR_V_CHG_NZ, cpu6812\|cpu9s12x, 0 },

696 { "leay", OP_IDX, 2, 0x19, 2, 2, CHG_NONE, cpu6812 },	992 { "ldy", OP_D_IDX, 2, 0xed, 6, 6, CLR_V_CHG_NZ, cpu6812\|cpu9s12x, 0 },

697 { "leay", OP_IDX_1, 3, 0x19, 2, 2, CHG_NONE, cpu6812 },	993 { "ldy", OP_D_IDX_2, 4, 0xed, 6, 6, CLR_V_CHG_NZ, cpu6812\|cpu9s12x, 0 },

698 { "leay", OP_IDX_2, 4, 0x19, 2, 2, CHG_NONE, cpu6812 },	994

699	995 { "leas", OP_IDX, 2, 0x1b, 2, 2, CHG_NONE, cpu6812\|cpu9s12x, 0 } ,

700 { "lsl", OP_IND16, 3, 0x78, 4, 4, CHG_NZVC, cpu6811\|cpu6812 },	996 { "leas", OP_IDX_1, 3, 0x1b, 2, 2, CHG_NONE, cpu6812\|cpu9s12x, 0 } ,

701 { "lsl", OP_IX, 2, 0x68, 6, 6, CHG_NZVC, cpu6811 },	997 { "leas", OP_IDX_2, 4, 0x1b, 2, 2, CHG_NONE, cpu6812\|cpu9s12x, 0 } ,

702 { "lsl", OP_IY \| OP_PAGE2, 3, 0x68, 7, 7, CHG_NZVC, cpu6811 },	998

703 { "lsl", OP_IDX, 2, 0x68, 3, 3, CHG_NZVC, cpu6812 },	999 { "leax", OP_IDX, 2, 0x1a, 2, 2, CHG_NONE, cpu6812\|cpu9s12x, 0 } ,

704 { "lsl", OP_IDX_1, 3, 0x68, 4, 4, CHG_NZVC, cpu6812 },	1000 { "leax", OP_IDX_1, 3, 0x1a, 2, 2, CHG_NONE, cpu6812\|cpu9s12x, 0 } ,

705 { "lsl", OP_IDX_2, 4, 0x68, 5, 5, CHG_NZVC, cpu6812 },	1001 { "leax", OP_IDX_2, 4, 0x1a, 2, 2, CHG_NONE, cpu6812\|cpu9s12x, 0 } ,

706 { "lsl", OP_D_IDX, 2, 0x68, 6, 6, CHG_NZVC, cpu6812 },	1002

707 { "lsl", OP_D_IDX_2, 4, 0x68, 6, 6, CHG_NZVC, cpu6812 },	1003 { "leay", OP_IDX, 2, 0x19, 2, 2, CHG_NONE, cpu6812\|cpu9s12x, 0 } ,

708	1004 { "leay", OP_IDX_1, 3, 0x19, 2, 2, CHG_NONE, cpu6812\|cpu9s12x, 0 } ,

709 { "lsla", OP_NONE, 1, 0x48, 1, 1, CHG_NZVC, cpu6811\|cpu6812 },	1005 { "leay", OP_IDX_2, 4, 0x19, 2, 2, CHG_NONE, cpu6812\|cpu9s12x, 0 } ,

710 { "lslb", OP_NONE, 1, 0x58, 1, 1, CHG_NZVC, cpu6811\|cpu6812 },	1006

711 { "lsld", OP_NONE, 1, 0x05, 3, 3, CHG_NZVC, cpu6811 },	1007 { "lsl", OP_IND16, 3, 0x78, 4, 4, CHG_NZVC, cpu6811\|cpu6812\|cpu9s 12x, 0 },

712 { "lsld", OP_NONE, 1, 0x59, 1, 1, CHG_NZVC, cpu6812 },	1008 { "lsl", OP_IX, 2, 0x68, 6, 6, CHG_NZVC, cpu6811, 0 },

713	1009 { "lsl", OP_IY \| OP_PAGE2, 3, 0x68, 7, 7, CHG_NZVC, cpu6811, 0 },

714 { "lsr", OP_IND16, 3, 0x74, 4, 4, CLR_N_CHG_ZVC, cpu6811\|cpu6812},	1010 { "lsl", OP_IDX, 2, 0x68, 3, 3, CHG_NZVC, cpu6812\|cpu9s12x, 0 } ,

715 { "lsr", OP_IX, 2, 0x64, 6, 6, CLR_N_CHG_ZVC, cpu6811 },	1011 { "lsl", OP_IDX_1, 3, 0x68, 4, 4, CHG_NZVC, cpu6812\|cpu9s12x, 0 } ,

716 { "lsr", OP_IY \| OP_PAGE2, 3, 0x64, 7, 7, CLR_V_CHG_ZVC, cpu6811 },	1012 { "lsl", OP_IDX_2, 4, 0x68, 5, 5, CHG_NZVC, cpu6812\|cpu9s12x, 0 } ,

717 { "lsr", OP_IDX, 2, 0x64, 3, 3, CLR_N_CHG_ZVC, cpu6812 },	1013 { "lsl", OP_D_IDX, 2, 0x68, 6, 6, CHG_NZVC, cpu6812\|cpu9s12x, 0 } ,

718 { "lsr", OP_IDX_1, 3, 0x64, 4, 4, CLR_N_CHG_ZVC, cpu6812 },	1014 { "lsl", OP_D_IDX_2, 4, 0x68, 6, 6, CHG_NZVC, cpu6812\|cpu9s12x, 0 } ,

719 { "lsr", OP_IDX_2, 4, 0x64, 5, 5, CLR_N_CHG_ZVC, cpu6812 },	1015

720 { "lsr", OP_D_IDX, 2, 0x64, 6, 6, CLR_N_CHG_ZVC, cpu6812 },	1016 { "lsla", OP_NONE, 1, 0x48, 1, 1, CHG_NZVC, cpu6811\|cpu6812\|cpu9s 12x, 0 },

721 { "lsr", OP_D_IDX_2, 4, 0x64, 6, 6, CLR_N_CHG_ZVC, cpu6812 },	1017 { "lslb", OP_NONE, 1, 0x58, 1, 1, CHG_NZVC, cpu6811\|cpu6812\|cpu9s 12x, 0 },

722	1018 { "lsld", OP_NONE, 1, 0x05, 3, 3, CHG_NZVC, cpu6811, 0 },

723 { "lsra", OP_NONE, 1, 0x44, 1, 1, CLR_N_CHG_ZVC, cpu6811\|cpu6812},	1019 { "lsld", OP_NONE, 1, 0x59, 1, 1, CHG_NZVC, cpu6812\|cpu9s12x, 0 } ,

724 { "lsrb", OP_NONE, 1, 0x54, 1, 1, CLR_N_CHG_ZVC, cpu6811\|cpu6812},	1020 /* lslw is the same as aslw. */

725 { "lsrd", OP_NONE, 1, 0x04, 3, 3, CLR_N_CHG_ZVC, cpu6811 },	1021 { "lslw", OP_IND16 \| OP_PAGE2, 3, 0x78, 4, 4, CHG_NZVC, cpu9s12x, 0 },

726 { "lsrd", OP_NONE, 1, 0x49, 1, 1, CLR_N_CHG_ZVC, cpu6812 },	1022 { "lslw", OP_IDX \| OP_PAGE2, 2, 0x68, 3, 3, CHG_NZVC, cpu9s12x, 0 },

727	1023 { "lslw", OP_IDX_1 \| OP_PAGE2, 3, 0x68, 4, 4, CHG_NZVC, cpu9s12x, 0 },

728 { "maxa", OP_IDX \| OP_PAGE2, 3, 0x18, 4, 4, CHG_NZVC, cpu6812 },	1024 { "lslw", OP_IDX_2 \| OP_PAGE2, 4, 0x68, 5, 5, CHG_NZVC, cpu9s12x, 0 },

729 { "maxa", OP_IDX_1 \| OP_PAGE2, 4, 0x18, 4, 4, CHG_NZVC, cpu6812 },	1025 { "lslw", OP_D_IDX \| OP_PAGE2, 2, 0x68, 6, 6, CHG_NZVC, cpu9s12x, 0 },

730 { "maxa", OP_IDX_2 \| OP_PAGE2, 5, 0x18, 5, 5, CHG_NZVC, cpu6812 },	1026 { "lslw", OP_D_IDX_2 \| OP_PAGE2, 4, 0x68, 6, 6, CHG_NZVC, cpu9s12x, 0 },

731 { "maxa", OP_D_IDX \| OP_PAGE2, 3, 0x18, 7, 7, CHG_NZVC, cpu6812 },	1027 /* lslx is same as aslx. */

732 { "maxa", OP_D_IDX_2 \| OP_PAGE2, 5, 0x18, 7, 7, CHG_NZVC, cpu6812 },	1028 { "lslx", OP_NONE \| OP_PAGE2, 1, 0x48, 1, 1, CHG_NZVC, cpu9s12x, 0 },

733	1029 /* lsly is the same as asly. */

734 { "maxm", OP_IDX \| OP_PAGE2, 3, 0x1c, 4, 4, CHG_NZVC, cpu6812 },	1030 { "lsly", OP_NONE \| OP_PAGE2, 1, 0x58, 1, 1, CHG_NZVC, cpu9s12x, 0 },

735 { "maxm", OP_IDX_1 \| OP_PAGE2, 4, 0x1c, 5, 5, CHG_NZVC, cpu6812 },	1031

736 { "maxm", OP_IDX_2 \| OP_PAGE2, 5, 0x1c, 6, 6, CHG_NZVC, cpu6812 },	1032 { "lsr", OP_IND16, 3, 0x74, 4, 4, CLR_N_CHG_ZVC, cpu6811\|cpu6812\|cp u9s12x, 0 },

737 { "maxm", OP_D_IDX \| OP_PAGE2, 3, 0x1c, 7, 7, CHG_NZVC, cpu6812 },	1033 { "lsr", OP_IX, 2, 0x64, 6, 6, CLR_N_CHG_ZVC, cpu6811, 0 },

738 { "maxm", OP_D_IDX_2 \| OP_PAGE2, 5, 0x1c, 7, 7, CHG_NZVC, cpu6812 },	1034 { "lsr", OP_IY \| OP_PAGE2, 3, 0x64, 7, 7, CLR_V_CHG_ZVC, cpu6811, 0 },

739	1035 { "lsr", OP_IDX, 2, 0x64, 3, 3, CLR_N_CHG_ZVC, cpu6812\|cpu9s12x , 0 },

740 { "mem", OP_NONE, 1, 0x01, 5, 5, CHG_HNZVC, cpu6812 },	1036 { "lsr", OP_IDX_1, 3, 0x64, 4, 4, CLR_N_CHG_ZVC, cpu6812\|cpu9s12x , 0 },

741	1037 { "lsr", OP_IDX_2, 4, 0x64, 5, 5, CLR_N_CHG_ZVC, cpu6812\|cpu9s12x , 0 },

742 { "mina", OP_IDX \| OP_PAGE2, 3, 0x19, 4, 4, CHG_NZVC, cpu6812 },	1038 { "lsr", OP_D_IDX, 2, 0x64, 6, 6, CLR_N_CHG_ZVC, cpu6812\|cpu9s12x , 0 },

743 { "mina", OP_IDX_1 \| OP_PAGE2, 4, 0x19, 4, 4, CHG_NZVC, cpu6812 },	1039 { "lsr", OP_D_IDX_2, 4, 0x64, 6, 6, CLR_N_CHG_ZVC, cpu6812\|cpu9s12x , 0 },

744 { "mina", OP_IDX_2 \| OP_PAGE2, 5, 0x19, 5, 5, CHG_NZVC, cpu6812 },	1040

745 { "mina", OP_D_IDX \| OP_PAGE2, 3, 0x19, 7, 7, CHG_NZVC, cpu6812 },	1041 { "lsra", OP_NONE, 1, 0x44, 1, 1, CLR_N_CHG_ZVC, cpu6811\|cpu6812\|cp u9s12x, 0 },

746 { "mina", OP_D_IDX_2 \| OP_PAGE2, 5, 0x19, 7, 7, CHG_NZVC, cpu6812 },	1042 { "lsrb", OP_NONE, 1, 0x54, 1, 1, CLR_N_CHG_ZVC, cpu6811\|cpu6812\|cp u9s12x, 0 },

747	1043 { "lsrd", OP_NONE, 1, 0x04, 3, 3, CLR_N_CHG_ZVC, cpu6811, 0 },

748 { "minm", OP_IDX \| OP_PAGE2, 3, 0x1d, 4, 4, CHG_NZVC, cpu6812 },	1044 { "lsrd", OP_NONE, 1, 0x49, 1, 1, CLR_N_CHG_ZVC, cpu6812\|cpu9s12x , 0 },

749 { "minm", OP_IDX_1 \| OP_PAGE2, 4, 0x1d, 5, 5, CHG_NZVC, cpu6812 },	1045

750 { "minm", OP_IDX_2 \| OP_PAGE2, 5, 0x1d, 6, 6, CHG_NZVC, cpu6812 },	1046 { "lsrw", OP_IND16 \| OP_PAGE2, 3, 0x74, 4, 4, CHG_NZVC, cpu9s12x, 0 },

751 { "minm", OP_D_IDX \| OP_PAGE2, 3, 0x1d, 7, 7, CHG_NZVC, cpu6812 },	1047 { "lsrw", OP_IDX \| OP_PAGE2, 2, 0x64, 3, 3, CHG_NZVC, cpu9s12x, 0 },

752 { "minm", OP_D_IDX_2 \| OP_PAGE2, 5, 0x1d, 7, 7, CHG_NZVC, cpu6812 },	1048 { "lsrw", OP_IDX_1 \| OP_PAGE2, 3, 0x64, 4, 4, CHG_NZVC, cpu9s12x, 0 },

753	1049 { "lsrw", OP_IDX_2 \| OP_PAGE2, 4, 0x64, 5, 5, CHG_NZVC, cpu9s12x, 0 },

754 { "movb", OP_IMM8\|OP_IND16_p2\|OP_PAGE2, 5, 0x0b, 4, 4, CHG_NONE, cpu6812 },	1050 { "lsrw", OP_D_IDX \| OP_PAGE2, 2, 0x64, 6, 6, CHG_NZVC, cpu9s12x, 0 },

755 { "movb", OP_IMM8\|OP_IDX_p2\|OP_PAGE2, 4, 0x08, 4, 4, CHG_NONE, cpu6812 },	1051 { "lsrw", OP_D_IDX_2 \| OP_PAGE2, 4, 0x64, 6, 6, CHG_NZVC, cpu9s12x, 0 },

756 { "movb", OP_IND16\|OP_IND16_p2\|OP_PAGE2, 6, 0x0c, 6, 6, CHG_NONE, cpu6812 },	1052

757 { "movb", OP_IND16 \| OP_IDX_p2 \| OP_PAGE2, 5, 0x09, 5, 5, CHG_NONE, cpu6 812 },	1053 { "lsrx", OP_NONE \| OP_PAGE2, 1, 0x44, 1, 1, CHG_NZVC, cpu9s12x, 0 },

758 { "movb", OP_IDX \| OP_IND16_p2 \| OP_PAGE2, 5, 0x0d, 5, 5, CHG_NONE, cpu6 812 },	1054

759 { "movb", OP_IDX \| OP_IDX_p2 \| OP_PAGE2, 4, 0x0a, 5, 5, CHG_NONE, cpu6 812 },	1055 { "lsry", OP_NONE \| OP_PAGE2, 1, 0x54, 1, 1, CHG_NZVC, cpu9s12x, 0 },

760	1056

761 { "movw", OP_IMM16 \| OP_IND16_p2 \| OP_PAGE2, 6, 0x03, 5, 5, CHG_NONE, cpu6 812 },	1057 { "maxa", OP_IDX \| OP_PAGE2, 3, 0x18, 4, 4, CHG_NZVC, cpu6812\|cpu9s12x, 0 },

762 { "movw", OP_IMM16 \| OP_IDX_p2 \| OP_PAGE2, 5, 0x00, 4, 4, CHG_NONE, cpu6 812 },	1058 { "maxa", OP_IDX_1 \| OP_PAGE2, 4, 0x18, 4, 4, CHG_NZVC, cpu6812\|cpu9s12x, 0 },

763 { "movw", OP_IND16 \| OP_IND16_p2 \| OP_PAGE2, 6, 0x04, 6, 6, CHG_NONE, cpu6 812 },	1059 { "maxa", OP_IDX_2 \| OP_PAGE2, 5, 0x18, 5, 5, CHG_NZVC, cpu6812\|cpu9s12x, 0 },

764 { "movw", OP_IND16 \| OP_IDX_p2 \| OP_PAGE2, 5, 0x01, 5, 5, CHG_NONE, cpu6 812 },	1060 { "maxa", OP_D_IDX \| OP_PAGE2, 3, 0x18, 7, 7, CHG_NZVC, cpu6812\|cpu9s12x, 0 },

765 { "movw", OP_IDX \| OP_IND16_p2 \| OP_PAGE2, 5, 0x05, 5, 5, CHG_NONE, cpu6 812 },	1061 { "maxa", OP_D_IDX_2 \| OP_PAGE2, 5, 0x18, 7, 7, CHG_NZVC, cpu6812\|cpu9s12x, 0 },

766 { "movw", OP_IDX \| OP_IDX_p2 \| OP_PAGE2, 4, 0x02, 5, 5, CHG_NONE, cpu6 812 },	1062

767	1063 { "maxm", OP_IDX \| OP_PAGE2, 3, 0x1c, 4, 4, CHG_NZVC, cpu6812\|cpu9s12x, 0 },

768 { "mul", OP_NONE, 1, 0x3d, 3, 10, CHG_C, cpu6811 },	1064 { "maxm", OP_IDX_1 \| OP_PAGE2, 4, 0x1c, 5, 5, CHG_NZVC, cpu6812\|cpu9s12x, 0 },

769 { "mul", OP_NONE, 1, 0x12, 3, 3, CHG_C, cpu6812 },	1065 { "maxm", OP_IDX_2 \| OP_PAGE2, 5, 0x1c, 6, 6, CHG_NZVC, cpu6812\|cpu9s12x, 0 },

770	1066 { "maxm", OP_D_IDX \| OP_PAGE2, 3, 0x1c, 7, 7, CHG_NZVC, cpu6812\|cpu9s12x, 0 },

771 { "neg", OP_IND16, 3, 0x70, 4, 4, CHG_NZVC, cpu6811\|cpu6812 },	1067 { "maxm", OP_D_IDX_2 \| OP_PAGE2, 5, 0x1c, 7, 7, CHG_NZVC, cpu6812\|cpu9s12x, 0 },

772 { "neg", OP_IX, 2, 0x60, 6, 6, CHG_NZVC, cpu6811 },	1068

773 { "neg", OP_IY \| OP_PAGE2, 3, 0x60, 7, 7, CHG_NZVC, cpu6811 },	1069 { "mem", OP_NONE, 1, 0x01, 5, 5, CHG_HNZVC, cpu6812\|cpu9s12 x, 0 },

774 { "neg", OP_IDX, 2, 0x60, 3, 3, CHG_NZVC, cpu6812 },	1070

775 { "neg", OP_IDX_1, 3, 0x60, 4, 4, CHG_NZVC, cpu6812 },	1071 { "mina", OP_IDX \| OP_PAGE2, 3, 0x19, 4, 4, CHG_NZVC, cpu6812\|cpu9s12x, 0 },

776 { "neg", OP_IDX_2, 4, 0x60, 5, 5, CHG_NZVC, cpu6812 },	1072 { "mina", OP_IDX_1 \| OP_PAGE2, 4, 0x19, 4, 4, CHG_NZVC, cpu6812\|cpu9s12x, 0 },

777 { "neg", OP_D_IDX, 2, 0x60, 6, 6, CHG_NZVC, cpu6812 },	1073 { "mina", OP_IDX_2 \| OP_PAGE2, 5, 0x19, 5, 5, CHG_NZVC, cpu6812\|cpu9s12x, 0 },

778 { "neg", OP_D_IDX_2, 4, 0x60, 6, 6, CHG_NZVC, cpu6812 },	1074 { "mina", OP_D_IDX \| OP_PAGE2, 3, 0x19, 7, 7, CHG_NZVC, cpu6812\|cpu9s12x, 0 },

779	1075 { "mina", OP_D_IDX_2 \| OP_PAGE2, 5, 0x19, 7, 7, CHG_NZVC, cpu6812\|cpu9s12x, 0 },

780 { "nega", OP_NONE, 1, 0x40, 1, 1, CHG_NZVC, cpu6811\|cpu6812 },	1076

781 { "negb", OP_NONE, 1, 0x50, 1, 1, CHG_NZVC, cpu6811\|cpu6812 },	1077 { "minm", OP_IDX \| OP_PAGE2, 3, 0x1d, 4, 4, CHG_NZVC, cpu6812\|cpu9s12x, 0 },

782 { "nop", OP_NONE, 1, 0x01, 2, 2, CHG_NONE, cpu6811 },	1078 { "minm", OP_IDX_1 \| OP_PAGE2, 4, 0x1d, 5, 5, CHG_NZVC, cpu6812\|cpu9s12x, 0 },

783 { "nop", OP_NONE, 1, 0xa7, 1, 1, CHG_NONE, cpu6812 },	1079 { "minm", OP_IDX_2 \| OP_PAGE2, 5, 0x1d, 6, 6, CHG_NZVC, cpu6812\|cpu9s12x, 0 },

784	1080 { "minm", OP_D_IDX \| OP_PAGE2, 3, 0x1d, 7, 7, CHG_NZVC, cpu6812\|cpu9s12x, 0 },

785 { "oraa", OP_IMM8, 2, 0x8a, 1, 1, CLR_V_CHG_NZ, cpu6811\|cpu6812 },	1081 { "minm", OP_D_IDX_2 \| OP_PAGE2, 5, 0x1d, 7, 7, CHG_NZVC, cpu6812\|cpu9s12x, 0 },

786 { "oraa", OP_DIRECT, 2, 0x9a, 3, 3, CLR_V_CHG_NZ, cpu6811\|cpu6812 },	1082

787 { "oraa", OP_IND16, 3, 0xba, 3, 3, CLR_V_CHG_NZ, cpu6811\|cpu6812 },	1083 /* The S12X additional modes are implemented, but uncommenting here causes a pro blem */

788 { "oraa", OP_IX, 2, 0xaa, 4, 4, CLR_V_CHG_NZ, cpu6811 },	1084 { "movb", OP_IMM8\|OP_IND16_p2\|OP_PAGE2, 5, 0x0b, 4, 4, CHG_NONE, cpu6 812\|cpu9s12x, 0 },

789 { "oraa", OP_IY \| OP_PAGE2, 3, 0xaa, 5, 5, CLR_V_CHG_NZ, cpu6811 },	1085 { "movb", OP_IMM8\|OP_IDX_p2\|OP_PAGE2, 4, 0x08, 4, 4, CHG_NONE, cpu6 812\|cpu9s12x, 0 },

790 { "oraa", OP_IDX, 2, 0xaa, 3, 3, CLR_V_CHG_NZ, cpu6812 },	1086 /* { "movb", OP_IMM8\|OP_IDX1_p2\|OP_PAGE2, 5, 0x08, 4, 4, CHG_NONE, cp u9s12x, 0 },

791 { "oraa", OP_IDX_1, 3, 0xaa, 3, 3, CLR_V_CHG_NZ, cpu6812 },	1087 { "movb", OP_IMM8\|OP_IDX2_p2\|OP_PAGE2, 4, 0x08, 4, 4, CHG_NONE, cpu9 s12x, 0 },

792 { "oraa", OP_IDX_2, 4, 0xaa, 4, 4, CLR_V_CHG_NZ, cpu6812 },	1088 { "movb", OP_IMM8\|OP_D_IDX\|OP_PAGE2, 5, 0x08, 4, 4, CHG_NONE, cpu9s12 x, 0 },

793 { "oraa", OP_D_IDX, 2, 0xaa, 6, 6, CLR_V_CHG_NZ, cpu6812 },	1089 { "movb", OP_IMM8\|OP_D_IDX2_p2\|OP_PAGE2, 4, 0x08, 4, 4, CHG_NONE, cpu9 s12x, 0 },*/

794 { "oraa", OP_D_IDX_2, 4, 0xaa, 6, 6, CLR_V_CHG_NZ, cpu6812 },	1090

795	1091 { "movb", OP_IND16\|OP_IND16_p2\|OP_PAGE2, 6, 0x0c, 6, 6, CHG_NONE, cpu6 812\|cpu9s12x, 0 },

796 { "orab", OP_IMM8, 2, 0xca, 1, 1, CLR_V_CHG_NZ, cpu6811\|cpu6812 },	1092 { "movb", OP_IND16\|OP_IDX_p2\|OP_PAGE2, 5, 0x09, 5, 5, CHG_NONE, cpu6 812\|cpu9s12x, 0 },

797 { "orab", OP_DIRECT, 2, 0xda, 3, 3, CLR_V_CHG_NZ, cpu6811\|cpu6812 },	1093 /* { "movb", OP_IND16\|OP_IDX1_p2\|OP_PAGE2, 6, 0x09, 6, 6, CHG_NONE, cp u9s12x, 0 },

798 { "orab", OP_IND16, 3, 0xfa, 3, 3, CLR_V_CHG_NZ, cpu6811\|cpu6812 },	1094 { "movb", OP_IND16\|OP_IDX2_p2\|OP_PAGE2, 5, 0x09, 5, 5, CHG_NONE, cpu9 s12x, 0 },

799 { "orab", OP_IX, 2, 0xea, 4, 4, CLR_V_CHG_NZ, cpu6811 },	1095 { "movb", OP_IND16\|OP_D_IDX_p2\|OP_PAGE2, 6, 0x09, 6, 6, CHG_NONE, cpu9s1 2x, 0 },

800 { "orab", OP_IY \| OP_PAGE2, 3, 0xea, 5, 5, CLR_V_CHG_NZ, cpu6811 },	1096 { "movb", OP_IND16\|OP_D_IDX2_p2\|OP_PAGE2, 5, 0x09, 5, 5, CHG_NONE, cpu9 s12x, 0 }, */

801 { "orab", OP_IDX, 2, 0xea, 3, 3, CLR_V_CHG_NZ, cpu6812 },	1097

802 { "orab", OP_IDX_1, 3, 0xea, 3, 3, CLR_V_CHG_NZ, cpu6812 },	1098 { "movb", OP_IDX\|OP_IND16_p2\|OP_PAGE2, 5, 0x0d, 5, 5, CHG_NONE, cpu6 812\|cpu9s12x, 0 },

803 { "orab", OP_IDX_2, 4, 0xea, 4, 4, CLR_V_CHG_NZ, cpu6812 },	1099 { "movb", OP_IDX\|OP_IDX_p2\|OP_PAGE2, 4, 0x0a, 5, 5, CHG_NONE, cpu6 812\|cpu9s12x, 0 },

804 { "orab", OP_D_IDX, 2, 0xea, 6, 6, CLR_V_CHG_NZ, cpu6812 },	1100 /* { "movb", OP_IDX\|OP_IDX1_p2\|OP_PAGE2, 5, 0x0a, 5, 5, CHG_NONE, cp u9s12x, 0 },

805 { "orab", OP_D_IDX_2, 4, 0xea, 6, 6, CLR_V_CHG_NZ, cpu6812 },	1101 { "movb", OP_IDX\|OP_IDX2_p2\|OP_PAGE2, 4, 0x0a, 5, 5, CHG_NONE, cpu9 s12x, 0 },

806	1102 { "movb", OP_IDX\|OP_D_IDX_p2\|OP_PAGE2, 5, 0x0d, 5, 5, CHG_NONE, cpu9 s12x, 0 },

807 { "orcc", OP_IMM8, 2, 0x14, 1, 1, CHG_ALL, cpu6812 },	1103 { "movb", OP_IDX\|OP_D_IDX2_p2\|OP_PAGE2, 4, 0x0a, 5, 5, CHG_NONE, cpu9 s12x, 0 },

808	1104

809 { "psha", OP_NONE, 1, 0x36, 2, 2, CHG_NONE, cpu6811\|cpu6812 },	1105 { "movb", OP_IDX_1\|OP_IND16_p2\|OP_PAGE2, 5, 0x0d, 5, 5, CHG_NONE, cpu 9s12x, 0 },

810 { "pshb", OP_NONE, 1, 0x37, 2, 2, CHG_NONE, cpu6811\|cpu6812 },	1106 { "movb", OP_IDX_1\|OP_IDX_p2\|OP_PAGE2, 4, 0x0a, 5, 5, CHG_NONE, cpu 9s12x, 0 },

811 { "pshc", OP_NONE, 1, 0x39, 2, 2, CHG_NONE, cpu6812 },	1107 { "movb", OP_IDX_1\|OP_IDX1_p2\|OP_PAGE2, 6, 0x0a, 6, 6, CHG_NONE, cpu 9s12x, 0 },

812 { "pshd", OP_NONE, 1, 0x3b, 2, 2, CHG_NONE, cpu6812 },	1108 { "movb", OP_IDX_1\|OP_IDX2_p2\|OP_PAGE2, 5, 0x0a, 5, 5, CHG_NONE, cpu 9s12x, 0 },

813 { "pshx", OP_NONE, 1, 0x3c, 4, 4, CHG_NONE, cpu6811 },	1109 { "movb", OP_IDX_1\|OP_D_IDX_p2\|OP_PAGE2, 6, 0x0a, 6, 6, CHG_NONE, cpu 9s12x, 0 },

814 { "pshx", OP_NONE, 1, 0x34, 2, 2, CHG_NONE, cpu6812 },	1110 { "movb", OP_IDX_1\|OP_D_IDX2_p2\|OP_PAGE2, 5, 0x0a, 5, 5, CHG_NONE, cpu 9s12x, 0 },

815 { "pshy", OP_NONE \| OP_PAGE2,2, 0x3c, 5, 5, CHG_NONE, cpu6811 },	1111

816 { "pshy", OP_NONE, 1, 0x35, 2, 2, CHG_NONE, cpu6812 },	1112 { "movb", OP_IDX_2\|OP_IND16_p2\|OP_PAGE2, 5, 0x0d, 5, 5, CHG_NONE, cpu 9s12x, 0 },

817	1113 { "movb", OP_IDX_2\|OP_IDX_p2\|OP_PAGE2, 4, 0x0a, 5, 5, CHG_NONE, cpu 9s12x, 0 },

818 { "pula", OP_NONE, 1, 0x32, 3, 3, CHG_NONE, cpu6811\|cpu6812 },	1114 { "movb", OP_IDX_2\|OP_IDX1_p2\|OP_PAGE2, 6, 0x0a, 6, 6, CHG_NONE, cpu 9s12x, 0 },

819 { "pulb", OP_NONE, 1, 0x33, 3, 3, CHG_NONE, cpu6811\|cpu6812 },	1115 { "movb", OP_IDX_2\|OP_IDX2_p2\|OP_PAGE2, 5, 0x0a, 5, 5, CHG_NONE, cpu 9s12x, 0 },

820 { "pulc", OP_NONE, 1, 0x38, 3, 3, CHG_NONE, cpu6812 },	1116 { "movb", OP_IDX_2\|OP_D_IDX_p2\|OP_PAGE2, 6, 0x0a, 6, 6, CHG_NONE, cpu 9s12x, 0 },

821 { "puld", OP_NONE, 1, 0x3a, 3, 3, CHG_NONE, cpu6812 },	1117 { "movb", OP_IDX_2\|OP_D_IDX2_p2\|OP_PAGE2, 5, 0x0a, 5, 5, CHG_NONE, cpu 9s12x, 0 },

822 { "pulx", OP_NONE, 1, 0x38, 5, 5, CHG_NONE, cpu6811 },	1118

823 { "pulx", OP_NONE, 1, 0x30, 3, 3, CHG_NONE, cpu6812 },	1119 { "movb", OP_D_IDX\|OP_IND16_p2\|OP_PAGE2, 5, 0x0d, 5, 5, CHG_NONE, cpu 9s12x, 0 },

824 { "puly", OP_NONE \| OP_PAGE2,2, 0x38, 6, 6, CHG_NONE, cpu6811 },	1120 { "movb", OP_D_IDX\|OP_IDX_p2\|OP_PAGE2, 4, 0x0a, 5, 5, CHG_NONE, cpu 9s12x, 0 },

825 { "puly", OP_NONE, 1, 0x31, 3, 3, CHG_NONE, cpu6812 },	1121 { "movb", OP_D_IDX\|OP_IDX1_p2\|OP_PAGE2, 6, 0x0a, 6, 6, CHG_NONE, cpu 9s12x, 0 },

826	1122 { "movb", OP_D_IDX\|OP_IDX2_p2\|OP_PAGE2, 5, 0x0a, 5, 5, CHG_NONE, cpu 9s12x, 0 },

827 { "rev", OP_NONE \| OP_PAGE2, 2, 0x3a, _M, _M, CHG_HNZVC, cpu6812 },	1123 { "movb", OP_D_IDX\|OP_D_IDX_p2\|OP_PAGE2, 6, 0x0a, 6, 6, CHG_NONE, cpu 9s12x, 0 },

828 { "revw", OP_NONE \| OP_PAGE2, 2, 0x3b, _M, _M, CHG_HNZVC, cpu6812 },	1124 { "movb", OP_D_IDX\|OP_D_IDX2_p2\|OP_PAGE2, 5, 0x0a, 5, 5, CHG_NONE, cpu 9s12x, 0 },

829	1125

830 { "rol", OP_IND16, 3, 0x79, 6, 6, CHG_NZVC, cpu6811 },	1126 { "movb", OP_D_IDX_2\|OP_IND16_p2\|OP_PAGE2, 5, 0x0d, 5, 5, CHG_NONE, c pu9s12x, 0 },

831 { "rol", OP_IX, 2, 0x69, 6, 6, CHG_NZVC, cpu6811 },	1127 { "movb", OP_D_IDX_2\|OP_IDX_p2\|OP_PAGE2, 4, 0x0a, 5, 5, CHG_NONE, c pu9s12x, 0 },

832 { "rol", OP_IY \| OP_PAGE2, 3, 0x69, 7, 7, CHG_NZVC, cpu6811 },	1128 { "movb", OP_D_IDX_2\|OP_IDX1_p2\|OP_PAGE2, 6, 0x0a, 6, 6, CHG_NONE, c pu9s12x, 0 },

833 { "rol", OP_IND16, 3, 0x75, 4, 4, CHG_NZVC, cpu6812 },	1129 { "movb", OP_D_IDX_2\|OP_IDX2_p2\|OP_PAGE2, 5, 0x0a, 5, 5, CHG_NONE, c pu9s12x, 0 },

834 { "rol", OP_IDX, 2, 0x65, 3, 3, CHG_NZVC, cpu6812 },	1130 { "movb", OP_D_IDX_2\|OP_D_IDX_p2\|OP_PAGE2, 6, 0x0a, 6, 6, CHG_NONE, c pu9s12x, 0 },

835 { "rol", OP_IDX_1, 3, 0x65, 4, 4, CHG_NZVC, cpu6812 },	1131 { "movb", OP_D_IDX_2\|OP_D_IDX2_p2\|OP_PAGE2, 5, 0x0a, 5, 5, CHG_NONE, c pu9s12x, 0 },*/

836 { "rol", OP_IDX_2, 4, 0x65, 5, 5, CHG_NZVC, cpu6812 },	1132

837 { "rol", OP_D_IDX, 2, 0x65, 6, 6, CHG_NZVC, cpu6812 },	1133 { "movw", OP_IMM16 \| OP_IND16_p2 \| OP_PAGE2, 6, 0x03, 5, 5, CHG_NONE, cpu6 812\|cpu9s12x, 0 },

838 { "rol", OP_D_IDX_2, 4, 0x65, 6, 6, CHG_NZVC, cpu6812 },	1134 { "movw", OP_IMM16 \| OP_IDX_p2 \| OP_PAGE2, 5, 0x00, 4, 4, CHG_NONE, cpu6 812\|cpu9s12x, 0 },

839	1135 /* { "movw", OP_IMM16\|OP_IDX1_p2\|OP_PAGE2, 5, 0x00, 4, 4, CHG_NONE, c pu9s12x, 0 },

840 { "rola", OP_NONE, 1, 0x49, 2, 2, CHG_NZVC, cpu6811 },	1136 { "movw", OP_IMM16\|OP_IDX2_p2\|OP_PAGE2, 4, 0x00, 4, 4, CHG_NONE, cpu 9s12x, 0 },

841 { "rola", OP_NONE, 1, 0x45, 1, 1, CHG_NZVC, cpu6812 },	1137 { "movw", OP_IMM16\|OP_D_IDX_p2\|OP_PAGE2, 5, 0x00, 4, 4, CHG_NONE, cpu 9s12x, 0 },

842 { "rolb", OP_NONE, 1, 0x59, 2, 2, CHG_NZVC, cpu6811 },	1138 { "movw", OP_IMM16\|OP_D_IDX2_p2\|OP_PAGE2, 4, 0x00, 4, 4, CHG_NONE, cpu 9s12x, 0 },*/

843 { "rolb", OP_NONE, 1, 0x55, 1, 1, CHG_NZVC, cpu6812 },	1139

844	1140 { "movw", OP_IND16 \| OP_IND16_p2 \| OP_PAGE2, 6, 0x04, 6, 6, CHG_NONE, cpu6 812\|cpu9s12x, 0 },

845 { "ror", OP_IND16, 3, 0x76, 4, 4, CHG_NZVC, cpu6811\|cpu6812 },	1141 { "movw", OP_IND16 \| OP_IDX_p2 \| OP_PAGE2, 5, 0x01, 5, 5, CHG_NONE, cpu6 812\|cpu9s12x, 0 },

846 { "ror", OP_IX, 2, 0x66, 6, 6, CHG_NZVC, cpu6811 },	1142 /* { "movw", OP_IND16\|OP_IDX1_p2\|OP_PAGE2, 6, 0x01, 6, 6, CHG_NONE, cp u9s12x, 0 },

847 { "ror", OP_IY \| OP_PAGE2, 3, 0x66, 7, 7, CHG_NZVC, cpu6811 },	1143 { "movw", OP_IND16\|OP_IDX2_p2\|OP_PAGE2, 5, 0x01, 5, 5, CHG_NONE, cpu9 s12x, 0 },

848 { "ror", OP_IDX, 2, 0x66, 3, 3, CHG_NZVC, cpu6812 },	1144 { "movw", OP_IND16\|OP_D_IDX_p2\|OP_PAGE2, 6, 0x01, 6, 6, CHG_NONE, cpu9 s12x, 0 },

849 { "ror", OP_IDX_1, 3, 0x66, 4, 4, CHG_NZVC, cpu6812 },	1145 { "movw", OP_IND16\|OP_D_IDX2_p2\|OP_PAGE2, 5, 0x01, 5, 5, CHG_NONE, cpu9 s12x, 0 },*/

850 { "ror", OP_IDX_2, 4, 0x66, 5, 5, CHG_NZVC, cpu6812 },	1146

851 { "ror", OP_D_IDX, 2, 0x66, 6, 6, CHG_NZVC, cpu6812 },	1147 { "movw", OP_IDX \| OP_IND16_p2 \| OP_PAGE2, 5, 0x05, 5, 5, CHG_NONE, cpu6 812\|cpu9s12x, 0 },

852 { "ror", OP_D_IDX_2, 4, 0x66, 6, 6, CHG_NZVC, cpu6812 },	1148 { "movw", OP_IDX \| OP_IDX_p2 \| OP_PAGE2, 4, 0x02, 5, 5, CHG_NONE, cpu6 812\|cpu9s12x, 0 },

853	1149 /* { "movw", OP_IDX\|OP_IDX1_p2\|OP_PAGE2, 5, 0x02, 5, 5, CHG_NONE, cp u9s12x, 0 },

854 { "rora", OP_NONE, 1, 0x46, 1, 1, CHG_NZVC, cpu6811\|cpu6812 },	1150 { "movw", OP_IDX\|OP_IDX2_p2\|OP_PAGE2, 4, 0x02, 5, 5, CHG_NONE, cpu9 s12x, 0 },

855 { "rorb", OP_NONE, 1, 0x56, 1, 1, CHG_NZVC, cpu6811\|cpu6812 },	1151 { "movw", OP_IDX\|OP_D_IDX_p2\|OP_PAGE2, 5, 0x02, 5, 5, CHG_NONE, cpu9 s12x, 0 },

856	1152 { "movw", OP_IDX\|OP_D_IDX2_p2\|OP_PAGE2, 4, 0x02, 5, 5, CHG_NONE, cpu9 s12x, 0 },

857 { "rtc", OP_NONE, 1, 0x0a, 6, 6, CHG_NONE, cpu6812 },	1153

858 { "rti", OP_NONE, 1, 0x3b, 12, 12, CHG_ALL, cpu6811},	1154 { "movw", OP_IDX_1\|OP_IND16_p2\|OP_PAGE2, 5, 0x05, 5, 5, CHG_NONE, cpu 9s12x, 0 },

859 { "rti", OP_NONE, 1, 0x0b, 8, 10, CHG_ALL, cpu6812},	1155 { "movw", OP_IDX_1\|OP_IDX_p2\|OP_PAGE2, 4, 0x02, 5, 5, CHG_NONE, cpu 9s12x, 0 },

860 { "rts", OP_NONE, 1, 0x39, 5, 5, CHG_NONE, cpu6811 },	1156 { "movw", OP_IDX_1\|OP_IDX1_p2\|OP_PAGE2, 6, 0x02, 6, 6, CHG_NONE, cpu 9s12x, 0 },

861 { "rts", OP_NONE, 1, 0x3d, 5, 5, CHG_NONE, cpu6812 },	1157 { "movw", OP_IDX_1\|OP_IDX2_p2\|OP_PAGE2, 5, 0x02, 5, 5, CHG_NONE, cpu 9s12x, 0 },

862	1158 { "movw", OP_IDX_1\|OP_D_IDX_p2\|OP_PAGE2, 6, 0x02, 6, 6, CHG_NONE, cpu 9s12x, 0 },

863 { "sba", OP_NONE, 1, 0x10, 2, 2, CHG_NZVC, cpu6811 },	1159 { "movw", OP_IDX_1\|OP_D_IDX2_p2\|OP_PAGE2, 5, 0x02, 5, 5, CHG_NONE, cpu 9s12x, 0 },

864 { "sba", OP_NONE \| OP_PAGE2, 2, 0x16, 2, 2, CHG_NZVC, cpu6812 },	1160

865	1161 { "movw", OP_IDX_2\|OP_IND16_p2\|OP_PAGE2, 5, 0x05, 5, 5, CHG_NONE, cpu 9s12x, 0 },

866 { "sbca", OP_IMM8, 2, 0x82, 1, 1, CHG_NZVC, cpu6811\|cpu6812 },	1162 { "movw", OP_IDX_2\|OP_IDX_p2\|OP_PAGE2, 4, 0x02, 5, 5, CHG_NONE, cpu 9s12x, 0 },

867 { "sbca", OP_DIRECT, 2, 0x92, 3, 3, CHG_NZVC, cpu6811\|cpu6812 },	1163 { "movw", OP_IDX_2\|OP_IDX1_p2\|OP_PAGE2, 6, 0x02, 6, 6, CHG_NONE, cpu 9s12x, 0 },

868 { "sbca", OP_IND16, 3, 0xb2, 3, 3, CHG_NZVC, cpu6811\|cpu6812 },	1164 { "movw", OP_IDX_2\|OP_IDX2_p2\|OP_PAGE2, 5, 0x02, 5, 5, CHG_NONE, cpu 9s12x, 0 },

869 { "sbca", OP_IX, 2, 0xa2, 4, 4, CHG_NZVC, cpu6811 },	1165 { "movw", OP_IDX_2\|OP_D_IDX_p2\|OP_PAGE2, 6, 0x02, 6, 6, CHG_NONE, cpu 9s12x, 0 },

870 { "sbca", OP_IY \| OP_PAGE2, 3, 0xa2, 5, 5, CHG_NZVC, cpu6811 },	1166 { "movw", OP_IDX_2\|OP_D_IDX2_p2\|OP_PAGE2, 5, 0x02, 5, 5, CHG_NONE, cpu 9s12x, 0 },

871 { "sbca", OP_IDX, 2, 0xa2, 3, 3, CHG_NZVC, cpu6812 },	1167

872 { "sbca", OP_IDX_1, 3, 0xa2, 3, 3, CHG_NZVC, cpu6812 },	1168 { "movw", OP_D_IDX\|OP_IND16_p2\|OP_PAGE2, 5, 0x05, 5, 5, CHG_NONE, cpu 9s12x, 0 },

873 { "sbca", OP_IDX_2, 4, 0xa2, 4, 4, CHG_NZVC, cpu6812 },	1169 { "movw", OP_D_IDX\|OP_IDX_p2\|OP_PAGE2, 4, 0x02, 5, 5, CHG_NONE, cpu 9s12x, 0 },

874 { "sbca", OP_D_IDX, 2, 0xa2, 6, 6, CHG_NZVC, cpu6812 },	1170 { "movw", OP_D_IDX\|OP_IDX1_p2\|OP_PAGE2, 6, 0x02, 6, 6, CHG_NONE, cpu 9s12x, 0 },

875 { "sbca", OP_D_IDX_2, 4, 0xa2, 6, 6, CHG_NZVC, cpu6812 },	1171 { "movw", OP_D_IDX\|OP_IDX2_p2\|OP_PAGE2, 5, 0x02, 5, 5, CHG_NONE, cpu 9s12x, 0 },

876	1172 { "movw", OP_D_IDX\|OP_D_IDX_p2\|OP_PAGE2, 6, 0x02, 6, 6, CHG_NONE, cpu 9s12x, 0 },

877 { "sbcb", OP_IMM8, 2, 0xc2, 1, 1, CHG_NZVC, cpu6811\|cpu6812 },	1173 { "movw", OP_D_IDX\|OP_D_IDX2_p2\|OP_PAGE2, 5, 0x02, 5, 5, CHG_NONE, cpu 9s12x, 0 },

878 { "sbcb", OP_DIRECT, 2, 0xd2, 3, 3, CHG_NZVC, cpu6811\|cpu6812 },	1174

879 { "sbcb", OP_IND16, 3, 0xf2, 3, 3, CHG_NZVC, cpu6811\|cpu6812 },	1175 { "movw", OP_D_IDX_2\|OP_IND16_p2\|OP_PAGE2, 5, 0x05, 5, 5, CHG_NONE, c pu9s12x, 0 },

880 { "sbcb", OP_IX, 2, 0xe2, 4, 4, CHG_NZVC, cpu6811 },	1176 { "movw", OP_D_IDX_2\|OP_IDX_p2\|OP_PAGE2, 4, 0x02, 5, 5, CHG_NONE, c pu9s12x, 0 },

881 { "sbcb", OP_IY \| OP_PAGE2, 3, 0xe2, 5, 5, CHG_NZVC, cpu6811 },	1177 { "movw", OP_D_IDX_2\|OP_IDX1_p2\|OP_PAGE2, 6, 0x02, 6, 6, CHG_NONE, c pu9s12x, 0 },

882 { "sbcb", OP_IDX, 2, 0xe2, 3, 3, CHG_NZVC, cpu6812 },	1178 { "movw", OP_D_IDX_2\|OP_IDX2_p2\|OP_PAGE2, 5, 0x02, 5, 5, CHG_NONE, c pu9s12x, 0 },

883 { "sbcb", OP_IDX_1, 3, 0xe2, 3, 3, CHG_NZVC, cpu6812 },	1179 { "movw", OP_D_IDX_2\|OP_D_IDX_p2\|OP_PAGE2, 6, 0x02, 6, 6, CHG_NONE, c pu9s12x, 0 },

884 { "sbcb", OP_IDX_2, 4, 0xe2, 4, 4, CHG_NZVC, cpu6812 },	1180 { "movw", OP_D_IDX_2\|OP_D_IDX2_p2\|OP_PAGE2, 5, 0x02, 5, 5, CHG_NONE, c pu9s12x, 0 },*/

885 { "sbcb", OP_D_IDX, 2, 0xe2, 6, 6, CHG_NZVC, cpu6812 },	1181

886 { "sbcb", OP_D_IDX_2, 4, 0xe2, 6, 6, CHG_NZVC, cpu6812 },	1182 { "mul", OP_NONE, 1, 0x3d, 3, 10, CHG_C, cpu6811, 0 },

887	1183 { "mul", OP_NONE, 1, 0x12, 3, 3, CHG_C, cpu6812\|cpu9s12x, 0 },

888 { "sec", OP_NONE, 1, 0x0d, 2, 2, SET_C, cpu6811 },	1184

889 { "sei", OP_NONE, 1, 0x0f, 2, 2, SET_I, cpu6811 },	1185 { "neg", OP_IND16, 3, 0x70, 4, 4, CHG_NZVC, cpu6811\|cpu6812\|cpu9s 12x, 0 },

890 { "sev", OP_NONE, 1, 0x0b, 2, 2, SET_V, cpu6811 },	1186 { "neg", OP_IX, 2, 0x60, 6, 6, CHG_NZVC, cpu6811, 0 },

891	1187 { "neg", OP_IY \| OP_PAGE2, 3, 0x60, 7, 7, CHG_NZVC, cpu6811, 0 },

	1188 { "neg", OP_IDX, 2, 0x60, 3, 3, CHG_NZVC, cpu6812\|cpu9s12x, 0 } ,

	1189 { "neg", OP_IDX_1, 3, 0x60, 4, 4, CHG_NZVC, cpu6812\|cpu9s12x, 0 } ,

	1190 { "neg", OP_IDX_2, 4, 0x60, 5, 5, CHG_NZVC, cpu6812\|cpu9s12x, 0 } ,

	1191 { "neg", OP_D_IDX, 2, 0x60, 6, 6, CHG_NZVC, cpu6812\|cpu9s12x, 0 } ,

	1192 { "neg", OP_D_IDX_2, 4, 0x60, 6, 6, CHG_NZVC, cpu6812\|cpu9s12x, 0 } ,

	1193

	1194 { "nega", OP_NONE, 1, 0x40, 1, 1, CHG_NZVC, cpu6811\|cpu6812\|cpu9s 12x, 0 },

	1195 { "negb", OP_NONE, 1, 0x50, 1, 1, CHG_NZVC, cpu6811\|cpu6812\|cpu9s 12x, 0 },

	1196

	1197 { "negw", OP_IND16\| OP_PAGE2, 3, 0x70, 4, 4, CHG_NZVC, cpu9s12x, 0 },

	1198 { "negw", OP_IDX\| OP_PAGE2, 2, 0x60, 3, 3, CHG_NZVC, cpu9s12x, 0 },

	1199 { "negw", OP_IDX_1\| OP_PAGE2, 3, 0x60, 4, 4, CHG_NZVC, cpu9s12x, 0 },

	1200 { "negw", OP_IDX_2\| OP_PAGE2, 4, 0x60, 5, 5, CHG_NZVC, cpu9s12x, 0 },

	1201 { "negw", OP_D_IDX\| OP_PAGE2, 2, 0x60, 6, 6, CHG_NZVC, cpu9s12x, 0 },

	1202 { "negw", OP_D_IDX_2\| OP_PAGE2, 4, 0x60, 6, 6, CHG_NZVC, cpu9s12x, 0 },

	1203

	1204 { "negx", OP_NONE\| OP_PAGE2, 1, 0x40, 1, 1, CHG_NZVC, cpu9s12x, 0 },

	1205

	1206 { "negy", OP_NONE\| OP_PAGE2, 1, 0x50, 1, 1, CHG_NZVC, cpu9s12x, 0 },

	1207

	1208 { "nop", OP_NONE, 1, 0x01, 2, 2, CHG_NONE, cpu6811, 0 },

	1209 { "nop", OP_NONE, 1, 0xa7, 1, 1, CHG_NONE, cpu6812\|cpu9s12x, 0 } ,

	1210

	1211 { "oraa", OP_IMM8, 2, 0x8a, 1, 1, CLR_V_CHG_NZ, cpu6811\|cpu6812\|cpu 9s12x, 0 },

	1212 { "oraa", OP_DIRECT, 2, 0x9a, 3, 3, CLR_V_CHG_NZ, cpu6811\|cpu6812\|cpu 9s12x, 0 },

	1213 { "oraa", OP_IND16, 3, 0xba, 3, 3, CLR_V_CHG_NZ, cpu6811\|cpu6812\|cpu 9s12x, 0 },

	1214 { "oraa", OP_IX, 2, 0xaa, 4, 4, CLR_V_CHG_NZ, cpu6811, 0 },

	1215 { "oraa", OP_IY \| OP_PAGE2, 3, 0xaa, 5, 5, CLR_V_CHG_NZ, cpu6811, 0 },

	1216 { "oraa", OP_IDX, 2, 0xaa, 3, 3, CLR_V_CHG_NZ, cpu6812\|cpu9s12x, 0 },

	1217 { "oraa", OP_IDX_1, 3, 0xaa, 3, 3, CLR_V_CHG_NZ, cpu6812\|cpu9s12x, 0 },

	1218 { "oraa", OP_IDX_2, 4, 0xaa, 4, 4, CLR_V_CHG_NZ, cpu6812\|cpu9s12x, 0 },

	1219 { "oraa", OP_D_IDX, 2, 0xaa, 6, 6, CLR_V_CHG_NZ, cpu6812\|cpu9s12x, 0 },

	1220 { "oraa", OP_D_IDX_2, 4, 0xaa, 6, 6, CLR_V_CHG_NZ, cpu6812\|cpu9s12x, 0 },

	1221

	1222 { "orab", OP_IMM8, 2, 0xca, 1, 1, CLR_V_CHG_NZ, cpu6811\|cpu6812\|cpu 9s12x, 0 },

	1223 { "orab", OP_DIRECT, 2, 0xda, 3, 3, CLR_V_CHG_NZ, cpu6811\|cpu6812\|cpu 9s12x, 0 },

	1224 { "orab", OP_IND16, 3, 0xfa, 3, 3, CLR_V_CHG_NZ, cpu6811\|cpu6812\|cpu 9s12x, 0 },

	1225 { "orab", OP_IX, 2, 0xea, 4, 4, CLR_V_CHG_NZ, cpu6811, 0 },

	1226 { "orab", OP_IY \| OP_PAGE2, 3, 0xea, 5, 5, CLR_V_CHG_NZ, cpu6811, 0 },

	1227 { "orab", OP_IDX, 2, 0xea, 3, 3, CLR_V_CHG_NZ, cpu6812\|cpu9s12x, 0 },

	1228 { "orab", OP_IDX_1, 3, 0xea, 3, 3, CLR_V_CHG_NZ, cpu6812\|cpu9s12x, 0 },

	1229 { "orab", OP_IDX_2, 4, 0xea, 4, 4, CLR_V_CHG_NZ, cpu6812\|cpu9s12x, 0 },

	1230 { "orab", OP_D_IDX, 2, 0xea, 6, 6, CLR_V_CHG_NZ, cpu6812\|cpu9s12x, 0 },

	1231 { "orab", OP_D_IDX_2, 4, 0xea, 6, 6, CLR_V_CHG_NZ, cpu6812\|cpu9s12x, 0 },

	1232

	1233 { "orcc", OP_IMM8, 2, 0x14, 1, 1, CHG_ALL, cpu6812\|cpu9s12x, 0 },

	1234

	1235 { "orx", OP_IMM16\| OP_PAGE2, 2, 0x8a, 1, 1, CLR_V_CHG_NZ, cpu9s12x, 0 },

	1236 { "orx", OP_DIRECT\| OP_PAGE2, 2, 0x9a, 3, 3, CLR_V_CHG_NZ, cpu9s12x, 0 },

	1237 { "orx", OP_IND16\| OP_PAGE2, 3, 0xba, 3, 3, CLR_V_CHG_NZ, cpu9s12x, 0 },

	1238 { "orx", OP_IDX\| OP_PAGE2, 2, 0xaa, 3, 3, CLR_V_CHG_NZ, cpu9s12x, 0 },

	1239 { "orx", OP_IDX_1\| OP_PAGE2, 3, 0xaa, 3, 3, CLR_V_CHG_NZ, cpu9s12x, 0 },

	1240 { "orx", OP_IDX_2\| OP_PAGE2, 4, 0xaa, 4, 4, CLR_V_CHG_NZ, cpu9s12x, 0 },

	1241 { "orx", OP_D_IDX\| OP_PAGE2, 2, 0xaa, 6, 6, CLR_V_CHG_NZ, cpu9s12x, 0 },

	1242 { "orx", OP_D_IDX_2\| OP_PAGE2,4, 0xaa, 6, 6, CLR_V_CHG_NZ, cpu9s12x, 0 },

	1243

	1244 { "ory", OP_IMM16\| OP_PAGE2, 2, 0xca, 1, 1, CLR_V_CHG_NZ, cpu9s12x, 0 },

	1245 { "ory", OP_DIRECT\| OP_PAGE2, 2, 0xda, 3, 3, CLR_V_CHG_NZ, cpu9s12x, 0 },

	1246 { "ory", OP_IND16\| OP_PAGE2, 3, 0xfa, 3, 3, CLR_V_CHG_NZ, cpu9s12x, 0 },

	1247 { "ory", OP_IDX\| OP_PAGE2, 2, 0xea, 3, 3, CLR_V_CHG_NZ, cpu9s12x, 0 },

	1248 { "ory", OP_IDX_1\| OP_PAGE2, 3, 0xea, 3, 3, CLR_V_CHG_NZ, cpu9s12x, 0 },

	1249 { "ory", OP_IDX_2\| OP_PAGE2, 4, 0xea, 4, 4, CLR_V_CHG_NZ, cpu9s12x, 0 },

	1250 { "ory", OP_D_IDX\| OP_PAGE2, 2, 0xea, 6, 6, CLR_V_CHG_NZ, cpu9s12x, 0 },

	1251 { "ory", OP_D_IDX_2\| OP_PAGE2,4, 0xea, 6, 6, CLR_V_CHG_NZ, cpu9s12x, 0 },

	1252

	1253 { "psha", OP_NONE, 1, 0x36, 2, 2, CHG_NONE, cpu6811\|cpu6812\|cpu9s 12x, 0 },

	1254 { "pshb", OP_NONE, 1, 0x37, 2, 2, CHG_NONE, cpu6811\|cpu6812\|cpu9s 12x, 0 },

	1255 { "pshc", OP_NONE, 1, 0x39, 2, 2, CHG_NONE, cpu6812\|cpu9s12x, 0 } ,

	1256 { "pshcw", OP_NONE\| OP_PAGE2,1, 0x39, 2, 2, CHG_NONE, cpu9s12x, 0 },

	1257 { "pshd", OP_NONE, 1, 0x3b, 2, 2, CHG_NONE, cpu6812\|cpu9s12x, 0 } ,

	1258 { "pshx", OP_NONE, 1, 0x3c, 4, 4, CHG_NONE, cpu6811, 0 },

	1259 { "pshx", OP_NONE, 1, 0x34, 2, 2, CHG_NONE, cpu6812\|cpu9s12x, 0 } ,

	1260 { "pshy", OP_NONE \| OP_PAGE2,2, 0x3c, 5, 5, CHG_NONE, cpu6811, 0 },

	1261 { "pshy", OP_NONE, 1, 0x35, 2, 2, CHG_NONE, cpu6812\|cpu9s12x, 0 } ,

	1262

	1263 { "pula", OP_NONE, 1, 0x32, 3, 3, CHG_NONE, cpu6811\|cpu6812\|cpu9s 12x, 0 },

	1264 { "pulb", OP_NONE, 1, 0x33, 3, 3, CHG_NONE, cpu6811\|cpu6812\|cpu9s 12x, 0 },

	1265 { "pulc", OP_NONE, 1, 0x38, 3, 3, CHG_NONE, cpu6812\|cpu9s12x, 0 } ,

	1266 { "pulcw", OP_NONE\| OP_PAGE2,1, 0x38, 2, 2, CHG_NONE, cpu9s12x, 0 },

	1267 { "puld", OP_NONE, 1, 0x3a, 3, 3, CHG_NONE, cpu6812\|cpu9s12x, 0 } ,

	1268 { "pulx", OP_NONE, 1, 0x38, 5, 5, CHG_NONE, cpu6811, 0 },

	1269 { "pulx", OP_NONE, 1, 0x30, 3, 3, CHG_NONE, cpu6812\|cpu9s12x, 0 } ,

	1270 { "puly", OP_NONE \| OP_PAGE2,2, 0x38, 6, 6, CHG_NONE, cpu6811, 0 },

	1271 { "puly", OP_NONE, 1, 0x31, 3, 3, CHG_NONE, cpu6812\|cpu9s12x, 0 } ,

	1272

	1273 { "rev", OP_NONE \| OP_PAGE2, 2, 0x3a, _M, _M, CHG_HNZVC, cpu6812\|cpu9s12x, 0 },

	1274 { "revw", OP_NONE \| OP_PAGE2, 2, 0x3b, _M, _M, CHG_HNZVC, cpu6812\|cpu9s12x, 0 },

	1275

	1276 { "rol", OP_IND16, 3, 0x79, 6, 6, CHG_NZVC, cpu6811, 0 },

	1277 { "rol", OP_IX, 2, 0x69, 6, 6, CHG_NZVC, cpu6811, 0 },

	1278 { "rol", OP_IY \| OP_PAGE2, 3, 0x69, 7, 7, CHG_NZVC, cpu6811, 0 },

	1279 { "rol", OP_IND16, 3, 0x75, 4, 4, CHG_NZVC, cpu6812\|cpu9s12x, 0 } ,

	1280 { "rol", OP_IDX, 2, 0x65, 3, 3, CHG_NZVC, cpu6812\|cpu9s12x, 0 } ,

	1281 { "rol", OP_IDX_1, 3, 0x65, 4, 4, CHG_NZVC, cpu6812\|cpu9s12x, 0 } ,

	1282 { "rol", OP_IDX_2, 4, 0x65, 5, 5, CHG_NZVC, cpu6812\|cpu9s12x, 0 } ,

	1283 { "rol", OP_D_IDX, 2, 0x65, 6, 6, CHG_NZVC, cpu6812\|cpu9s12x, 0 } ,

	1284 { "rol", OP_D_IDX_2, 4, 0x65, 6, 6, CHG_NZVC, cpu6812\|cpu9s12x, 0 } ,

	1285

	1286 { "rola", OP_NONE, 1, 0x49, 2, 2, CHG_NZVC, cpu6811, 0 },

	1287 { "rola", OP_NONE, 1, 0x45, 1, 1, CHG_NZVC, cpu6812\|cpu9s12x, 0 } ,

	1288 { "rolb", OP_NONE, 1, 0x59, 2, 2, CHG_NZVC, cpu6811, 0 },

	1289 { "rolb", OP_NONE, 1, 0x55, 1, 1, CHG_NZVC, cpu6812\|cpu9s12x, 0 } ,

	1290

	1291 { "rolw", OP_IND16 \| OP_PAGE2, 3, 0x75, 4, 4, CHG_NZVC, cpu9s12x, 0 },

	1292 { "rolw", OP_IDX \| OP_PAGE2, 2, 0x65, 3, 3, CHG_NZVC, cpu9s12x, 0 },

	1293 { "rolw", OP_IDX_1 \| OP_PAGE2, 3, 0x65, 4, 4, CHG_NZVC, cpu9s12x, 0 },

	1294 { "rolw", OP_IDX_2 \| OP_PAGE2, 4, 0x65, 5, 5, CHG_NZVC, cpu9s12x, 0 },

	1295 { "rolw", OP_D_IDX \| OP_PAGE2, 2, 0x65, 6, 6, CHG_NZVC, cpu9s12x, 0 },

	1296 { "rolw", OP_D_IDX_2 \| OP_PAGE2, 4, 0x65, 6, 6, CHG_NZVC, cpu9s12x, 0 },

	1297

	1298 { "rolx", OP_NONE \| OP_PAGE2, 1, 0x45, 1, 1, CHG_NZVC, cpu9s12x, 0 },

	1299 { "roly", OP_NONE \| OP_PAGE2, 1, 0x55, 1, 1, CHG_NZVC, cpu9s12x, 0 },

	1300

	1301 { "ror", OP_IND16, 3, 0x76, 4, 4, CHG_NZVC, cpu6811\|cpu6812\|cpu9s 12x, 0 },

	1302 { "ror", OP_IX, 2, 0x66, 6, 6, CHG_NZVC, cpu6811, 0 },

	1303 { "ror", OP_IY \| OP_PAGE2, 3, 0x66, 7, 7, CHG_NZVC, cpu6811, 0 },

	1304 { "ror", OP_IDX, 2, 0x66, 3, 3, CHG_NZVC, cpu6812\|cpu9s12x, 0 } ,

	1305 { "ror", OP_IDX_1, 3, 0x66, 4, 4, CHG_NZVC, cpu6812\|cpu9s12x, 0 } ,

	1306 { "ror", OP_IDX_2, 4, 0x66, 5, 5, CHG_NZVC, cpu6812\|cpu9s12x, 0 } ,

	1307 { "ror", OP_D_IDX, 2, 0x66, 6, 6, CHG_NZVC, cpu6812\|cpu9s12x, 0 } ,

	1308 { "ror", OP_D_IDX_2, 4, 0x66, 6, 6, CHG_NZVC, cpu6812\|cpu9s12x, 0 } ,

	1309

	1310 { "rora", OP_NONE, 1, 0x46, 1, 1, CHG_NZVC, cpu6811\|cpu6812\|cpu9s 12x, 0 },

	1311 { "rorb", OP_NONE, 1, 0x56, 1, 1, CHG_NZVC, cpu6811\|cpu6812\|cpu9s 12x, 0 },

	1312

	1313 { "rorw", OP_IND16 \| OP_PAGE2, 3, 0x76, 4, 4, CHG_NZVC, cpu9s12x, 0 },

	1314 { "rorw", OP_IDX \| OP_PAGE2, 2, 0x66, 3, 3, CHG_NZVC, cpu9s12x, 0 },

	1315 { "rorw", OP_IDX_1 \| OP_PAGE2, 3, 0x66, 4, 4, CHG_NZVC, cpu9s12x, 0 },

	1316 { "rorw", OP_IDX_2 \| OP_PAGE2, 4, 0x66, 5, 5, CHG_NZVC, cpu9s12x, 0 },

	1317 { "rorw", OP_D_IDX \| OP_PAGE2, 2, 0x66, 6, 6, CHG_NZVC, cpu9s12x, 0 },

	1318 { "rorw", OP_D_IDX_2 \| OP_PAGE2, 4, 0x66, 6, 6, CHG_NZVC, cpu9s12x, 0 },

	1319

	1320 { "rorx", OP_NONE \| OP_PAGE2, 1, 0x46, 1, 1, CHG_NZVC, cpu9s12x, 0 },

	1321 { "rory", OP_NONE \| OP_PAGE2, 1, 0x56, 1, 1, CHG_NZVC, cpu9s12x, 0 },

	1322

	1323 { "rtc", OP_NONE, 1, 0x0a, 6, 6, CHG_NONE, cpu6812\|cpu9s12x, 0 } ,

	1324 { "rti", OP_NONE, 1, 0x3b, 12, 12, CHG_ALL, cpu6811, 0 },

	1325 { "rti", OP_NONE, 1, 0x0b, 8, 10, CHG_ALL, cpu6812\|cpu9s12x, 0 },

	1326 { "rts", OP_NONE, 1, 0x39, 5, 5, CHG_NONE, cpu6811, 0 },

	1327 { "rts", OP_NONE, 1, 0x3d, 5, 5, CHG_NONE, cpu6812\|cpu9s12x, 0 } ,

	1328

	1329 { "sba", OP_NONE, 1, 0x10, 2, 2, CHG_NZVC, cpu6811, 0 },

	1330 { "sba", OP_NONE \| OP_PAGE2, 2, 0x16, 2, 2, CHG_NZVC, cpu6812\|cpu9s12x, 0 },

	1331

	1332 { "sbca", OP_IMM8, 2, 0x82, 1, 1, CHG_NZVC, cpu6811\|cpu6812\|cpu9s 12x, 0 },

	1333 { "sbca", OP_DIRECT, 2, 0x92, 3, 3, CHG_NZVC, cpu6811\|cpu6812\|cpu9s 12x, 0 },

	1334 { "sbca", OP_IND16, 3, 0xb2, 3, 3, CHG_NZVC, cpu6811\|cpu6812\|cpu9s 12x, 0 },

	1335 { "sbca", OP_IX, 2, 0xa2, 4, 4, CHG_NZVC, cpu6811, 0 },

	1336 { "sbca", OP_IY \| OP_PAGE2, 3, 0xa2, 5, 5, CHG_NZVC, cpu6811, 0 },

	1337 { "sbca", OP_IDX, 2, 0xa2, 3, 3, CHG_NZVC, cpu6812\|cpu9s12x, 0 } ,

	1338 { "sbca", OP_IDX_1, 3, 0xa2, 3, 3, CHG_NZVC, cpu6812\|cpu9s12x, 0 } ,

	1339 { "sbca", OP_IDX_2, 4, 0xa2, 4, 4, CHG_NZVC, cpu6812\|cpu9s12x, 0 } ,

	1340 { "sbca", OP_D_IDX, 2, 0xa2, 6, 6, CHG_NZVC, cpu6812\|cpu9s12x, 0 } ,

	1341 { "sbca", OP_D_IDX_2, 4, 0xa2, 6, 6, CHG_NZVC, cpu6812\|cpu9s12x, 0 } ,

	1342

	1343 { "sbcb", OP_IMM8, 2, 0xc2, 1, 1, CHG_NZVC, cpu6811\|cpu6812\|cpu9s 12x, 0 },

	1344 { "sbcb", OP_DIRECT, 2, 0xd2, 3, 3, CHG_NZVC, cpu6811\|cpu6812\|cpu9s 12x, 0 },

	1345 { "sbcb", OP_IND16, 3, 0xf2, 3, 3, CHG_NZVC, cpu6811\|cpu6812\|cpu9s 12x, 0 },

	1346 { "sbcb", OP_IX, 2, 0xe2, 4, 4, CHG_NZVC, cpu6811, 0 },

	1347 { "sbcb", OP_IY \| OP_PAGE2, 3, 0xe2, 5, 5, CHG_NZVC, cpu6811, 0 },

	1348 { "sbcb", OP_IDX, 2, 0xe2, 3, 3, CHG_NZVC, cpu6812\|cpu9s12x, 0 } ,

	1349 { "sbcb", OP_IDX_1, 3, 0xe2, 3, 3, CHG_NZVC, cpu6812\|cpu9s12x, 0 } ,

	1350 { "sbcb", OP_IDX_2, 4, 0xe2, 4, 4, CHG_NZVC, cpu6812\|cpu9s12x, 0 } ,

	1351 { "sbcb", OP_D_IDX, 2, 0xe2, 6, 6, CHG_NZVC, cpu6812\|cpu9s12x, 0 } ,

	1352 { "sbcb", OP_D_IDX_2, 4, 0xe2, 6, 6, CHG_NZVC, cpu6812\|cpu9s12x, 0 } ,

	1353

	1354 { "sbed", OP_IMM16 \| OP_PAGE2, 3, 0x83, 2, 2, CHG_NZVC, cpu9s12x, 0 },

	1355 { "sbed", OP_DIRECT \| OP_PAGE2, 2, 0x93, 3, 3, CHG_NZVC, cpu9s12x, 0 },

	1356 { "sbed", OP_IND16 \| OP_PAGE2, 3, 0xb3, 3, 3, CHG_NZVC, cpu9s12x, 0 },

	1357 { "sbed", OP_IDX \| OP_PAGE2, 2, 0xa3, 3, 3, CHG_NZVC, cpu9s12x, 0 },

	1358 { "sbed", OP_IDX_1 \| OP_PAGE2, 3, 0xa3, 3, 3, CHG_NZVC, cpu9s12x, 0 },

	1359 { "sbed", OP_IDX_2 \| OP_PAGE2, 4, 0xa3, 4, 4, CHG_NZVC, cpu9s12x, 0 },

	1360 { "sbed", OP_D_IDX \| OP_PAGE2, 2, 0xa3, 6, 6, CHG_NZVC, cpu9s12x, 0 },

	1361 { "sbed", OP_D_IDX_2 \| OP_PAGE2, 4, 0xa3, 6, 6, CHG_NZVC, cpu9s12x, 0 },

	1362

	1363 { "sbex", OP_IMM16 \| OP_PAGE2, 3, 0x82, 2, 2, CHG_NZVC, cpu9s12x, 0 },

	1364 { "sbex", OP_DIRECT \| OP_PAGE2, 2, 0x92, 3, 3, CHG_NZVC, cpu9s12x, 0 },

	1365 { "sbex", OP_IND16 \| OP_PAGE2, 3, 0xb2, 3, 3, CHG_NZVC, cpu9s12x, 0 },

	1366 { "sbex", OP_IDX \| OP_PAGE2, 2, 0xa2, 3, 3, CHG_NZVC, cpu9s12x, 0 },

	1367 { "sbex", OP_IDX_1 \| OP_PAGE2, 3, 0xa2, 3, 3, CHG_NZVC, cpu9s12x, 0 },

	1368 { "sbex", OP_IDX_2 \| OP_PAGE2, 4, 0xa2, 4, 4, CHG_NZVC, cpu9s12x, 0 },

	1369 { "sbex", OP_D_IDX \| OP_PAGE2, 2, 0xa2, 6, 6, CHG_NZVC, cpu9s12x, 0 },

	1370 { "sbex", OP_D_IDX_2 \| OP_PAGE2, 4, 0xa2, 6, 6, CHG_NZVC, cpu9s12x, 0 },

	1371

	1372 { "sbey", OP_IMM16 \| OP_PAGE2, 3, 0xc2, 2, 2, CHG_NZVC, cpu9s12x, 0 },

	1373 { "sbey", OP_DIRECT \| OP_PAGE2, 2, 0xd2, 3, 3, CHG_NZVC, cpu9s12x, 0 },

	1374 { "sbey", OP_IND16 \| OP_PAGE2, 3, 0xf2, 3, 3, CHG_NZVC, cpu9s12x, 0 },

	1375 { "sbey", OP_IDX \| OP_PAGE2, 2, 0xe2, 3, 3, CHG_NZVC, cpu9s12x, 0 },

	1376 { "sbey", OP_IDX_1 \| OP_PAGE2, 3, 0xe2, 3, 3, CHG_NZVC, cpu9s12x, 0 },

	1377 { "sbey", OP_IDX_2 \| OP_PAGE2, 4, 0xe2, 4, 4, CHG_NZVC, cpu9s12x, 0 },

	1378 { "sbey", OP_D_IDX \| OP_PAGE2, 2, 0xe2, 6, 6, CHG_NZVC, cpu9s12x, 0 },

	1379 { "sbey", OP_D_IDX_2 \| OP_PAGE2, 4, 0xe2, 6, 6, CHG_NZVC, cpu9s12x, 0 },

	1380

	1381 { "sec", OP_NONE, 1, 0x0d, 2, 2, SET_C, cpu6811, 0 },

	1382 { "sei", OP_NONE, 1, 0x0f, 2, 2, SET_I, cpu6811, 0 },

	1383 { "sev", OP_NONE, 1, 0x0b, 2, 2, SET_V, cpu6811, 0 },

	1384

	1385 /* Some sex opcodes are synonyms for tfr. */

892 { "sex", M6812_OP_SEX_MARKER	1386 { "sex", M6812_OP_SEX_MARKER

893 \| OP_REG \| OP_REG_2, 2, 0xb7, 1, 1, CHG_NONE, cpu6812 },	1387 \| OP_REG \| OP_REG_2, 2, 0xb7, 1, 1, CHG_NONE, cpu6812\|cpu9s12x, 0 } ,

894	1388

895 { "staa", OP_IND16, 3, 0xb7, 4, 4, CLR_V_CHG_NZ, cpu6811 },	1389 { "staa", OP_IND16, 3, 0xb7, 4, 4, CLR_V_CHG_NZ, cpu6811, 0 },

896 { "staa", OP_DIRECT, 2, 0x97, 3, 3, CLR_V_CHG_NZ, cpu6811 },	1390 { "staa", OP_DIRECT, 2, 0x97, 3, 3, CLR_V_CHG_NZ, cpu6811, 0 },

897 { "staa", OP_IX, 2, 0xa7, 4, 4, CLR_V_CHG_NZ, cpu6811 },	1391 { "staa", OP_IX, 2, 0xa7, 4, 4, CLR_V_CHG_NZ, cpu6811, 0 },

898 { "staa", OP_IY \| OP_PAGE2, 3, 0xa7, 5, 5, CLR_V_CHG_NZ, cpu6811 },	1392 { "staa", OP_IY \| OP_PAGE2, 3, 0xa7, 5, 5, CLR_V_CHG_NZ, cpu6811, 0 },

899 { "staa", OP_DIRECT, 2, 0x5a, 2, 2, CLR_V_CHG_NZ, cpu6812 },	1393 { "staa", OP_DIRECT, 2, 0x5a, 2, 2, CLR_V_CHG_NZ, cpu6812\|cpu9s12x, 0 },

900 { "staa", OP_IND16, 3, 0x7a, 3, 3, CLR_V_CHG_NZ, cpu6812 },	1394 { "staa", OP_IND16, 3, 0x7a, 3, 3, CLR_V_CHG_NZ, cpu6812\|cpu9s12x, 0 },

901 { "staa", OP_IDX, 2, 0x6a, 2, 2, CLR_V_CHG_NZ, cpu6812 },	1395 { "staa", OP_IDX, 2, 0x6a, 2, 2, CLR_V_CHG_NZ, cpu6812\|cpu9s12x, 0 },

902 { "staa", OP_IDX_1, 3, 0x6a, 3, 3, CLR_V_CHG_NZ, cpu6812 },	1396 { "staa", OP_IDX_1, 3, 0x6a, 3, 3, CLR_V_CHG_NZ, cpu6812\|cpu9s12x, 0 },

903 { "staa", OP_IDX_2, 4, 0x6a, 3, 3, CLR_V_CHG_NZ, cpu6812 },	1397 { "staa", OP_IDX_2, 4, 0x6a, 3, 3, CLR_V_CHG_NZ, cpu6812\|cpu9s12x, 0 },

904 { "staa", OP_D_IDX, 2, 0x6a, 5, 5, CLR_V_CHG_NZ, cpu6812 },	1398 { "staa", OP_D_IDX, 2, 0x6a, 5, 5, CLR_V_CHG_NZ, cpu6812\|cpu9s12x, 0 },

905 { "staa", OP_D_IDX_2, 4, 0x6a, 5, 5, CLR_V_CHG_NZ, cpu6812 },	1399 { "staa", OP_D_IDX_2, 4, 0x6a, 5, 5, CLR_V_CHG_NZ, cpu6812\|cpu9s12x, 0 },

906	1400

907 { "stab", OP_IND16, 3, 0xf7, 4, 4, CLR_V_CHG_NZ, cpu6811 },	1401 { "stab", OP_IND16, 3, 0xf7, 4, 4, CLR_V_CHG_NZ, cpu6811, 0 },

908 { "stab", OP_DIRECT, 2, 0xd7, 3, 3, CLR_V_CHG_NZ, cpu6811 },	1402 { "stab", OP_DIRECT, 2, 0xd7, 3, 3, CLR_V_CHG_NZ, cpu6811, 0 },

909 { "stab", OP_IX, 2, 0xe7, 4, 4, CLR_V_CHG_NZ, cpu6811 },	1403 { "stab", OP_IX, 2, 0xe7, 4, 4, CLR_V_CHG_NZ, cpu6811, 0 },

910 { "stab", OP_IY \| OP_PAGE2, 3, 0xe7, 5, 5, CLR_V_CHG_NZ, cpu6811 },	1404 { "stab", OP_IY \| OP_PAGE2, 3, 0xe7, 5, 5, CLR_V_CHG_NZ, cpu6811, 0 },

911 { "stab", OP_DIRECT, 2, 0x5b, 2, 2, CLR_V_CHG_NZ, cpu6812 },	1405 { "stab", OP_DIRECT, 2, 0x5b, 2, 2, CLR_V_CHG_NZ, cpu6812\|cpu9s12x, 0 },

912 { "stab", OP_IND16, 3, 0x7b, 3, 3, CLR_V_CHG_NZ, cpu6812 },	1406 { "stab", OP_IND16, 3, 0x7b, 3, 3, CLR_V_CHG_NZ, cpu6812\|cpu9s12x, 0 },

913 { "stab", OP_IDX, 2, 0x6b, 2, 2, CLR_V_CHG_NZ, cpu6812 },	1407 { "stab", OP_IDX, 2, 0x6b, 2, 2, CLR_V_CHG_NZ, cpu6812\|cpu9s12x, 0 },

914 { "stab", OP_IDX_1, 3, 0x6b, 3, 3, CLR_V_CHG_NZ, cpu6812 },	1408 { "stab", OP_IDX_1, 3, 0x6b, 3, 3, CLR_V_CHG_NZ, cpu6812\|cpu9s12x, 0 },

915 { "stab", OP_IDX_2, 4, 0x6b, 3, 3, CLR_V_CHG_NZ, cpu6812 },	1409 { "stab", OP_IDX_2, 4, 0x6b, 3, 3, CLR_V_CHG_NZ, cpu6812\|cpu9s12x, 0 },

916 { "stab", OP_D_IDX, 2, 0x6b, 5, 5, CLR_V_CHG_NZ, cpu6812 },	1410 { "stab", OP_D_IDX, 2, 0x6b, 5, 5, CLR_V_CHG_NZ, cpu6812\|cpu9s12x, 0 },

917 { "stab", OP_D_IDX_2, 4, 0x6b, 5, 5, CLR_V_CHG_NZ, cpu6812 },	1411 { "stab", OP_D_IDX_2, 4, 0x6b, 5, 5, CLR_V_CHG_NZ, cpu6812\|cpu9s12x, 0 },

918	1412

919 { "std", OP_IND16, 3, 0xfd, 5, 5, CLR_V_CHG_NZ, cpu6811 },	1413 { "std", OP_IND16, 3, 0xfd, 5, 5, CLR_V_CHG_NZ, cpu6811, 0 },

920 { "std", OP_DIRECT, 2, 0xdd, 4, 4, CLR_V_CHG_NZ, cpu6811 },	1414 { "std", OP_DIRECT, 2, 0xdd, 4, 4, CLR_V_CHG_NZ, cpu6811, 0 },

921 { "std", OP_IX, 2, 0xed, 5, 5, CLR_V_CHG_NZ, cpu6811 },	1415 { "std", OP_IX, 2, 0xed, 5, 5, CLR_V_CHG_NZ, cpu6811, 0 },

922 { "std", OP_IY \| OP_PAGE2, 3, 0xed, 6, 6, CLR_V_CHG_NZ, cpu6811 },	1416 { "std", OP_IY \| OP_PAGE2, 3, 0xed, 6, 6, CLR_V_CHG_NZ, cpu6811, 0 },

923 { "std", OP_DIRECT, 2, 0x5c, 2, 2, CLR_V_CHG_NZ, cpu6812 },	1417 { "std", OP_DIRECT, 2, 0x5c, 2, 2, CLR_V_CHG_NZ, cpu6812\|cpu9s12x, 0 },

924 { "std", OP_IND16, 3, 0x7c, 3, 3, CLR_V_CHG_NZ, cpu6812 },	1418 { "std", OP_IND16, 3, 0x7c, 3, 3, CLR_V_CHG_NZ, cpu6812\|cpu9s12x, 0 },

925 { "std", OP_IDX, 2, 0x6c, 2, 2, CLR_V_CHG_NZ, cpu6812 },	1419 { "std", OP_IDX, 2, 0x6c, 2, 2, CLR_V_CHG_NZ, cpu6812\|cpu9s12x, 0 },

926 { "std", OP_IDX_1, 3, 0x6c, 3, 3, CLR_V_CHG_NZ, cpu6812 },	1420 { "std", OP_IDX_1, 3, 0x6c, 3, 3, CLR_V_CHG_NZ, cpu6812\|cpu9s12x, 0 },

927 { "std", OP_IDX_2, 4, 0x6c, 3, 3, CLR_V_CHG_NZ, cpu6812 },	1421 { "std", OP_IDX_2, 4, 0x6c, 3, 3, CLR_V_CHG_NZ, cpu6812\|cpu9s12x, 0 },

928 { "std", OP_D_IDX, 2, 0x6c, 5, 5, CLR_V_CHG_NZ, cpu6812 },	1422 { "std", OP_D_IDX, 2, 0x6c, 5, 5, CLR_V_CHG_NZ, cpu6812\|cpu9s12x, 0 },

929 { "std", OP_D_IDX_2, 4, 0x6c, 5, 5, CLR_V_CHG_NZ, cpu6812 },	1423 { "std", OP_D_IDX_2, 4, 0x6c, 5, 5, CLR_V_CHG_NZ, cpu6812\|cpu9s12x, 0 },

930	1424

931 { "stop", OP_NONE, 1, 0xcf, 2, 2, CHG_NONE, cpu6811 },	1425 { "stop", OP_NONE, 1, 0xcf, 2, 2, CHG_NONE, cpu6811, 0 },

932 { "stop", OP_NONE \| OP_PAGE2,2, 0x3e, 2, 9, CHG_NONE, cpu6812 },	1426 { "stop", OP_NONE \| OP_PAGE2,2, 0x3e, 2, 9, CHG_NONE, cpu6812\|cpu9s12x, 0 } ,

933	1427

934 { "sts", OP_IND16, 3, 0xbf, 5, 5, CLR_V_CHG_NZ, cpu6811 },	1428 { "sts", OP_IND16, 3, 0xbf, 5, 5, CLR_V_CHG_NZ, cpu6811, 0 },

935 { "sts", OP_DIRECT, 2, 0x9f, 4, 4, CLR_V_CHG_NZ, cpu6811 },	1429 { "sts", OP_DIRECT, 2, 0x9f, 4, 4, CLR_V_CHG_NZ, cpu6811, 0 },

936 { "sts", OP_IX, 2, 0xaf, 5, 5, CLR_V_CHG_NZ, cpu6811 },	1430 { "sts", OP_IX, 2, 0xaf, 5, 5, CLR_V_CHG_NZ, cpu6811, 0 },

937 { "sts", OP_IY \| OP_PAGE2, 3, 0xaf, 6, 6, CLR_V_CHG_NZ, cpu6811 },	1431 { "sts", OP_IY \| OP_PAGE2, 3, 0xaf, 6, 6, CLR_V_CHG_NZ, cpu6811, 0 },

938 { "sts", OP_DIRECT, 2, 0x5f, 2, 2, CLR_V_CHG_NZ, cpu6812 },	1432 { "sts", OP_DIRECT, 2, 0x5f, 2, 2, CLR_V_CHG_NZ, cpu6812\|cpu9s12x, 0 },

939 { "sts", OP_IND16, 3, 0x7f, 3, 3, CLR_V_CHG_NZ, cpu6812 },	1433 { "sts", OP_IND16, 3, 0x7f, 3, 3, CLR_V_CHG_NZ, cpu6812\|cpu9s12x, 0 },

940 { "sts", OP_IDX, 2, 0x6f, 2, 2, CLR_V_CHG_NZ, cpu6812 },	1434 { "sts", OP_IDX, 2, 0x6f, 2, 2, CLR_V_CHG_NZ, cpu6812\|cpu9s12x, 0 },

941 { "sts", OP_IDX_1, 3, 0x6f, 3, 3, CLR_V_CHG_NZ, cpu6812 },	1435 { "sts", OP_IDX_1, 3, 0x6f, 3, 3, CLR_V_CHG_NZ, cpu6812\|cpu9s12x, 0 },

942 { "sts", OP_IDX_2, 4, 0x6f, 3, 3, CLR_V_CHG_NZ, cpu6812 },	1436 { "sts", OP_IDX_2, 4, 0x6f, 3, 3, CLR_V_CHG_NZ, cpu6812\|cpu9s12x, 0 },

943 { "sts", OP_D_IDX, 2, 0x6f, 5, 5, CLR_V_CHG_NZ, cpu6812 },	1437 { "sts", OP_D_IDX, 2, 0x6f, 5, 5, CLR_V_CHG_NZ, cpu6812\|cpu9s12x, 0 },

944 { "sts", OP_D_IDX_2, 4, 0x6f, 5, 5, CLR_V_CHG_NZ, cpu6812 },	1438 { "sts", OP_D_IDX_2, 4, 0x6f, 5, 5, CLR_V_CHG_NZ, cpu6812\|cpu9s12x, 0 },

945	1439

946 { "stx", OP_IND16, 3, 0xff, 5, 5, CLR_V_CHG_NZ, cpu6811 },	1440 { "stx", OP_IND16, 3, 0xff, 5, 5, CLR_V_CHG_NZ, cpu6811, 0 },

947 { "stx", OP_DIRECT, 2, 0xdf, 4, 4, CLR_V_CHG_NZ, cpu6811 },	1441 { "stx", OP_DIRECT, 2, 0xdf, 4, 4, CLR_V_CHG_NZ, cpu6811, 0 },

948 { "stx", OP_IX, 2, 0xef, 5, 5, CLR_V_CHG_NZ, cpu6811 },	1442 { "stx", OP_IX, 2, 0xef, 5, 5, CLR_V_CHG_NZ, cpu6811, 0 },

949 { "stx", OP_IY \| OP_PAGE4, 3, 0xef, 6, 6, CLR_V_CHG_NZ, cpu6811 },	1443 { "stx", OP_IY \| OP_PAGE4, 3, 0xef, 6, 6, CLR_V_CHG_NZ, cpu6811, 0 },

950 { "stx", OP_DIRECT, 2, 0x5e, 2, 2, CLR_V_CHG_NZ, cpu6812 },	1444 { "stx", OP_DIRECT, 2, 0x5e, 2, 2, CLR_V_CHG_NZ, cpu6812\|cpu9s12x, 0 },

951 { "stx", OP_IND16, 3, 0x7e, 3, 3, CLR_V_CHG_NZ, cpu6812 },	1445 { "stx", OP_IND16, 3, 0x7e, 3, 3, CLR_V_CHG_NZ, cpu6812\|cpu9s12x, 0 },

952 { "stx", OP_IDX, 2, 0x6e, 2, 2, CLR_V_CHG_NZ, cpu6812 },	1446 { "stx", OP_IDX, 2, 0x6e, 2, 2, CLR_V_CHG_NZ, cpu6812\|cpu9s12x, 0 },

953 { "stx", OP_IDX_1, 3, 0x6e, 3, 3, CLR_V_CHG_NZ, cpu6812 },	1447 { "stx", OP_IDX_1, 3, 0x6e, 3, 3, CLR_V_CHG_NZ, cpu6812\|cpu9s12x, 0 },

954 { "stx", OP_IDX_2, 4, 0x6e, 3, 3, CLR_V_CHG_NZ, cpu6812 },	1448 { "stx", OP_IDX_2, 4, 0x6e, 3, 3, CLR_V_CHG_NZ, cpu6812\|cpu9s12x, 0 },

955 { "stx", OP_D_IDX, 2, 0x6e, 5, 5, CLR_V_CHG_NZ, cpu6812 },	1449 { "stx", OP_D_IDX, 2, 0x6e, 5, 5, CLR_V_CHG_NZ, cpu6812\|cpu9s12x, 0 },

956 { "stx", OP_D_IDX_2, 4, 0x6e, 5, 5, CLR_V_CHG_NZ, cpu6812 },	1450 { "stx", OP_D_IDX_2, 4, 0x6e, 5, 5, CLR_V_CHG_NZ, cpu6812\|cpu9s12x, 0 },

957	1451

958 { "sty", OP_IND16 \| OP_PAGE2, 4, 0xff, 6, 6, CLR_V_CHG_NZ, cpu6811 },	1452 { "sty", OP_IND16 \| OP_PAGE2, 4, 0xff, 6, 6, CLR_V_CHG_NZ, cpu6811, 0 },

959 { "sty", OP_DIRECT \| OP_PAGE2, 3, 0xdf, 5, 5, CLR_V_CHG_NZ, cpu6811 },	1453 { "sty", OP_DIRECT \| OP_PAGE2, 3, 0xdf, 5, 5, CLR_V_CHG_NZ, cpu6811, 0 },

960 { "sty", OP_IY \| OP_PAGE2, 3, 0xef, 6, 6, CLR_V_CHG_NZ, cpu6811 },	1454 { "sty", OP_IY \| OP_PAGE2, 3, 0xef, 6, 6, CLR_V_CHG_NZ, cpu6811, 0 },

961 { "sty", OP_IX \| OP_PAGE3, 3, 0xef, 6, 6, CLR_V_CHG_NZ, cpu6811 },	1455 { "sty", OP_IX \| OP_PAGE3, 3, 0xef, 6, 6, CLR_V_CHG_NZ, cpu6811, 0 },

962 { "sty", OP_DIRECT, 2, 0x5d, 2, 2, CLR_V_CHG_NZ, cpu6812 },	1456 { "sty", OP_DIRECT, 2, 0x5d, 2, 2, CLR_V_CHG_NZ, cpu6812\|cpu9s12x, 0 },

963 { "sty", OP_IND16, 3, 0x7d, 3, 3, CLR_V_CHG_NZ, cpu6812 },	1457 { "sty", OP_IND16, 3, 0x7d, 3, 3, CLR_V_CHG_NZ, cpu6812\|cpu9s12x, 0 },

964 { "sty", OP_IDX, 2, 0x6d, 2, 2, CLR_V_CHG_NZ, cpu6812 },	1458 { "sty", OP_IDX, 2, 0x6d, 2, 2, CLR_V_CHG_NZ, cpu6812\|cpu9s12x, 0 },

965 { "sty", OP_IDX_1, 3, 0x6d, 3, 3, CLR_V_CHG_NZ, cpu6812 },	1459 { "sty", OP_IDX_1, 3, 0x6d, 3, 3, CLR_V_CHG_NZ, cpu6812\|cpu9s12x, 0 },

966 { "sty", OP_IDX_2, 4, 0x6d, 3, 3, CLR_V_CHG_NZ, cpu6812 },	1460 { "sty", OP_IDX_2, 4, 0x6d, 3, 3, CLR_V_CHG_NZ, cpu6812\|cpu9s12x, 0 },

967 { "sty", OP_D_IDX, 2, 0x6d, 5, 5, CLR_V_CHG_NZ, cpu6812 },	1461 { "sty", OP_D_IDX, 2, 0x6d, 5, 5, CLR_V_CHG_NZ, cpu6812\|cpu9s12x, 0 },

968 { "sty", OP_D_IDX_2, 4, 0x6d, 5, 5, CLR_V_CHG_NZ, cpu6812 },	1462 { "sty", OP_D_IDX_2, 4, 0x6d, 5, 5, CLR_V_CHG_NZ, cpu6812\|cpu9s12x, 0 },

969	1463

970 { "suba", OP_IMM8, 2, 0x80, 1, 1, CHG_NZVC, cpu6811\|cpu6812 },	1464 { "suba", OP_IMM8, 2, 0x80, 1, 1, CHG_NZVC, cpu6811\|cpu6812\|cpu9s 12x, 0 },

971 { "suba", OP_DIRECT, 2, 0x90, 3, 3, CHG_NZVC, cpu6811\|cpu6812 },	1465 { "suba", OP_DIRECT, 2, 0x90, 3, 3, CHG_NZVC, cpu6811\|cpu6812\|cpu9s 12x, 0 },

972 { "suba", OP_IND16, 3, 0xb0, 3, 3, CHG_NZVC, cpu6811\|cpu6812 },	1466 { "suba", OP_IND16, 3, 0xb0, 3, 3, CHG_NZVC, cpu6811\|cpu6812\|cpu9s 12x, 0 },

973 { "suba", OP_IX, 2, 0xa0, 4, 4, CHG_NZVC, cpu6811 },	1467 { "suba", OP_IX, 2, 0xa0, 4, 4, CHG_NZVC, cpu6811, 0 },

974 { "suba", OP_IY \| OP_PAGE2, 3, 0xa0, 5, 5, CHG_NZVC, cpu6811 },	1468 { "suba", OP_IY \| OP_PAGE2, 3, 0xa0, 5, 5, CHG_NZVC, cpu6811, 0 },

975 { "suba", OP_IDX, 2, 0xa0, 3, 3, CHG_NZVC, cpu6812 },	1469 { "suba", OP_IDX, 2, 0xa0, 3, 3, CHG_NZVC, cpu6812\|cpu9s12x, 0 } ,

976 { "suba", OP_IDX_1, 3, 0xa0, 3, 3, CHG_NZVC, cpu6812 },	1470 { "suba", OP_IDX_1, 3, 0xa0, 3, 3, CHG_NZVC, cpu6812\|cpu9s12x, 0 } ,

977 { "suba", OP_IDX_2, 4, 0xa0, 4, 4, CHG_NZVC, cpu6812 },	1471 { "suba", OP_IDX_2, 4, 0xa0, 4, 4, CHG_NZVC, cpu6812\|cpu9s12x, 0 } ,

978 { "suba", OP_D_IDX, 2, 0xa0, 6, 6, CHG_NZVC, cpu6812 },	1472 { "suba", OP_D_IDX, 2, 0xa0, 6, 6, CHG_NZVC, cpu6812\|cpu9s12x, 0 } ,

979 { "suba", OP_D_IDX_2, 4, 0xa0, 6, 6, CHG_NZVC, cpu6812 },	1473 { "suba", OP_D_IDX_2, 4, 0xa0, 6, 6, CHG_NZVC, cpu6812\|cpu9s12x, 0 } ,

980	1474

981 { "subb", OP_IMM8, 2, 0xc0, 1, 1, CHG_NZVC, cpu6811\|cpu6812 },	1475 { "subb", OP_IMM8, 2, 0xc0, 1, 1, CHG_NZVC, cpu6811\|cpu6812\|cpu9s 12x, 0 },

982 { "subb", OP_DIRECT, 2, 0xd0, 3, 3, CHG_NZVC, cpu6811\|cpu6812 },	1476 { "subb", OP_DIRECT, 2, 0xd0, 3, 3, CHG_NZVC, cpu6811\|cpu6812\|cpu9s 12x, 0 },

983 { "subb", OP_IND16, 3, 0xf0, 3, 3, CHG_NZVC, cpu6811\|cpu6812 },	1477 { "subb", OP_IND16, 3, 0xf0, 3, 3, CHG_NZVC, cpu6811\|cpu6812\|cpu9s 12x, 0 },

984 { "subb", OP_IX, 2, 0xe0, 4, 4, CHG_NZVC, cpu6811 },	1478 { "subb", OP_IX, 2, 0xe0, 4, 4, CHG_NZVC, cpu6811, 0 },

985 { "subb", OP_IY \| OP_PAGE2, 3, 0xe0, 5, 5, CHG_NZVC, cpu6811 },	1479 { "subb", OP_IY \| OP_PAGE2, 3, 0xe0, 5, 5, CHG_NZVC, cpu6811, 0 },

986 { "subb", OP_IDX, 2, 0xe0, 3, 3, CHG_NZVC, cpu6812 },	1480 { "subb", OP_IDX, 2, 0xe0, 3, 3, CHG_NZVC, cpu6812\|cpu9s12x, 0 } ,

987 { "subb", OP_IDX_1, 3, 0xe0, 3, 3, CHG_NZVC, cpu6812 },	1481 { "subb", OP_IDX_1, 3, 0xe0, 3, 3, CHG_NZVC, cpu6812\|cpu9s12x, 0 } ,

988 { "subb", OP_IDX_2, 4, 0xe0, 4, 4, CHG_NZVC, cpu6812 },	1482 { "subb", OP_IDX_2, 4, 0xe0, 4, 4, CHG_NZVC, cpu6812\|cpu9s12x, 0 } ,

989 { "subb", OP_D_IDX, 2, 0xe0, 6, 6, CHG_NZVC, cpu6812 },	1483 { "subb", OP_D_IDX, 2, 0xe0, 6, 6, CHG_NZVC, cpu6812\|cpu9s12x, 0 } ,

990 { "subb", OP_D_IDX_2, 4, 0xe0, 6, 6, CHG_NZVC, cpu6812 },	1484 { "subb", OP_D_IDX_2, 4, 0xe0, 6, 6, CHG_NZVC, cpu6812\|cpu9s12x, 0 } ,

991	1485

992 { "subd", OP_IMM16, 3, 0x83, 2, 2, CHG_NZVC, cpu6811\|cpu6812 },	1486 { "subd", OP_IMM16, 3, 0x83, 2, 2, CHG_NZVC, cpu6811\|cpu6812\|cpu9s 12x, 0 },

993 { "subd", OP_DIRECT, 2, 0x93, 3, 3, CHG_NZVC, cpu6811\|cpu6812 },	1487 { "subd", OP_DIRECT, 2, 0x93, 3, 3, CHG_NZVC, cpu6811\|cpu6812\|cpu9s 12x, 0 },

994 { "subd", OP_IND16, 3, 0xb3, 3, 3, CHG_NZVC, cpu6811\|cpu6812 },	1488 { "subd", OP_IND16, 3, 0xb3, 3, 3, CHG_NZVC, cpu6811\|cpu6812\|cpu9s 12x, 0 },

995 { "subd", OP_IX, 2, 0xa3, 6, 6, CHG_NZVC, cpu6811 },	1489 { "subd", OP_IX, 2, 0xa3, 6, 6, CHG_NZVC, cpu6811, 0 },

996 { "subd", OP_IY \| OP_PAGE2, 3, 0xa3, 7, 7, CHG_NZVC, cpu6811 },	1490 { "subd", OP_IY \| OP_PAGE2, 3, 0xa3, 7, 7, CHG_NZVC, cpu6811, 0 },

997 { "subd", OP_IDX, 2, 0xa3, 3, 3, CHG_NZVC, cpu6812 },	1491 { "subd", OP_IDX, 2, 0xa3, 3, 3, CHG_NZVC, cpu6812\|cpu9s12x, 0 } ,

998 { "subd", OP_IDX_1, 3, 0xa3, 3, 3, CHG_NZVC, cpu6812 },	1492 { "subd", OP_IDX_1, 3, 0xa3, 3, 3, CHG_NZVC, cpu6812\|cpu9s12x, 0 } ,

999 { "subd", OP_IDX_2, 4, 0xa3, 4, 4, CHG_NZVC, cpu6812 },	1493 { "subd", OP_IDX_2, 4, 0xa3, 4, 4, CHG_NZVC, cpu6812\|cpu9s12x, 0 } ,

1000 { "subd", OP_D_IDX, 2, 0xa3, 6, 6, CHG_NZVC, cpu6812 },	1494 { "subd", OP_D_IDX, 2, 0xa3, 6, 6, CHG_NZVC, cpu6812\|cpu9s12x, 0 } ,

1001 { "subd", OP_D_IDX_2, 4, 0xa3, 6, 6, CHG_NZVC, cpu6812 },	1495 { "subd", OP_D_IDX_2, 4, 0xa3, 6, 6, CHG_NZVC, cpu6812\|cpu9s12x, 0 } ,

1002	1496

1003 { "swi", OP_NONE, 1, 0x3f, 9, 9, CHG_NONE, cpu6811\|cpu6812 },	1497 { "subx", OP_IMM16 \| OP_PAGE2, 3, 0x80, 2, 2, CHG_NZVC, cpu9s12x, 0 },

1004	1498 { "subx", OP_DIRECT \| OP_PAGE2, 2, 0x90, 3, 3, CHG_NZVC, cpu9s12x, 0 },

1005 { "tab", OP_NONE, 1, 0x16, 2, 2, CLR_V_CHG_NZ, cpu6811 },	1499 { "subx", OP_IND16 \| OP_PAGE2, 3, 0xb0, 3, 3, CHG_NZVC, cpu9s12x, 0 },

1006 { "tab", OP_NONE \| OP_PAGE2,2, 0x0e, 2, 2, CLR_V_CHG_NZ, cpu6812 },	1500 { "subx", OP_IDX \| OP_PAGE2, 2, 0xa0, 3, 3, CHG_NZVC, cpu9s12x, 0 },

1007	1501 { "subx", OP_IDX_1 \| OP_PAGE2, 3, 0xa0, 3, 3, CHG_NZVC, cpu9s12x, 0 },

1008 { "tap", OP_NONE, 1, 0x06, 2, 2, CHG_ALL, cpu6811 },	1502 { "subx", OP_IDX_2 \| OP_PAGE2, 4, 0xa0, 4, 4, CHG_NZVC, cpu9s12x, 0 },

1009	1503 { "subx", OP_D_IDX \| OP_PAGE2, 2, 0xa0, 6, 6, CHG_NZVC, cpu9s12x, 0 },

1010 { "tba", OP_NONE, 1, 0x17, 2, 2, CLR_V_CHG_NZ, cpu6811 },	1504 { "subx", OP_D_IDX_2 \| OP_PAGE2, 4, 0xa0, 6, 6, CHG_NZVC, cpu9s12x, 0 },

1011 { "tba", OP_NONE \| OP_PAGE2,2, 0x0f, 2, 2, CLR_V_CHG_NZ, cpu6812 },	1505

1012	1506 { "suby", OP_IMM16 \| OP_PAGE2, 3, 0xc0, 2, 2, CHG_NZVC, cpu9s12x, 0 },

1013 { "test", OP_NONE, 1, 0x00, 5, _M, CHG_NONE, cpu6811 },	1507 { "suby", OP_DIRECT \| OP_PAGE2, 2, 0xd0, 3, 3, CHG_NZVC, cpu9s12x, 0 },

1014	1508 { "suby", OP_IND16 \| OP_PAGE2, 3, 0xf0, 3, 3, CHG_NZVC, cpu9s12x, 0 },

1015 { "tpa", OP_NONE, 1, 0x07, 2, 2, CHG_NONE, cpu6811 },	1509 { "suby", OP_IDX \| OP_PAGE2, 2, 0xe0, 3, 3, CHG_NZVC, cpu9s12x, 0 },

	1510 { "suby", OP_IDX_1 \| OP_PAGE2, 3, 0xe0, 3, 3, CHG_NZVC, cpu9s12x, 0 },

	1511 { "suby", OP_IDX_2 \| OP_PAGE2, 4, 0xe0, 4, 4, CHG_NZVC, cpu9s12x, 0 },

	1512 { "suby", OP_D_IDX \| OP_PAGE2, 2, 0xe0, 6, 6, CHG_NZVC, cpu9s12x, 0 },

	1513 { "suby", OP_D_IDX_2 \| OP_PAGE2, 4, 0xe0, 6, 6, CHG_NZVC, cpu9s12x, 0 },

	1514

	1515 { "swi", OP_NONE, 1, 0x3f, 9, 9, CHG_NONE, cpu6811\|cpu6812\|cpu9s 12x, 0 },

	1516 { "sys", OP_NONE \| OP_PAGE2,2, 0xa7, 9, 9, SET_I, cpu9s12x, 0 },

	1517

	1518 { "tab", OP_NONE, 1, 0x16, 2, 2, CLR_V_CHG_NZ, cpu6811, 0 },

	1519 { "tab", OP_NONE \| OP_PAGE2,2, 0x0e, 2, 2, CLR_V_CHG_NZ, cpu6812\|cpu9s12x, 0 },

	1520

	1521 { "tap", OP_NONE, 1, 0x06, 2, 2, CHG_ALL, cpu6811, 0 },

	1522

	1523 { "tba", OP_NONE, 1, 0x17, 2, 2, CLR_V_CHG_NZ, cpu6811, 0 },

	1524 { "tba", OP_NONE \| OP_PAGE2,2, 0x0f, 2, 2, CLR_V_CHG_NZ, cpu6812\|cpu9s12x, 0 },

	1525

	1526 { "test", OP_NONE, 1, 0x00, 5, _M, CHG_NONE, cpu6811, 0 },

	1527

	1528 { "tpa", OP_NONE, 1, 0x07, 2, 2, CHG_NONE, cpu6811, 0 },

1016	1529

1017 { "tbeq", OP_TBEQ_MARKER	1530 { "tbeq", OP_TBEQ_MARKER

1018 \| OP_REG \| OP_JUMP_REL, 3, 0x04, 3, 3, CHG_NONE, cpu6812 },	1531 \| OP_REG \| OP_JUMP_REL, 3, 0x04, 3, 3, CHG_NONE, cpu6812\|cpu9s12x, 0 },

1019	1532

1020 { "tbl", OP_IDX \| OP_PAGE2, 3, 0x3d, 8, 8, CHG_NZC, cpu6812 },	1533 { "tbl", OP_IDX \| OP_PAGE2, 3, 0x3d, 8, 8, CHG_NZC, cpu6812\|cpu9s12x, 0 },

1021	1534

1022 { "tbne", OP_TBNE_MARKER	1535 { "tbne", OP_TBNE_MARKER

1023 \| OP_REG \| OP_JUMP_REL, 3, 0x04, 3, 3, CHG_NONE, cpu6812 },	1536 \| OP_REG \| OP_JUMP_REL, 3, 0x04, 3, 3, CHG_NONE, cpu6812\|cpu9s12x, 0 },

1024	1537

	1538 /* The S12X has more tfr variants, but most are pointless so not supported. */

1025 { "tfr", OP_TFR_MARKER	1539 { "tfr", OP_TFR_MARKER

1026 \| OP_REG_1 \| OP_REG_2, 2, 0xb7, 1, 1, CHG_NONE, cpu6812 },	1540 \| OP_REG_1 \| OP_REG_2, 2, 0xb7, 1, 1, CHG_NONE, cpu6812\|cpu9s12x, 0 } ,

1027	1541

1028 { "trap", OP_IMM8 \| OP_TRAP_ID, 2, 0x18, 11, 11, SET_I, cpu6812 },	1542 { "trap", OP_IMM8 \| OP_TRAP_ID, 2, 0x18, 11, 11, SET_I, cpu6812\|cpu9s12x, 0 },

1029	1543

1030 { "tst", OP_IND16, 3, 0x7d, 6, 6, CLR_VC_CHG_NZ, cpu6811 },	1544 { "tst", OP_IND16, 3, 0x7d, 6, 6, CLR_VC_CHG_NZ, cpu6811, 0 },

1031 { "tst", OP_IX, 2, 0x6d, 6, 6, CLR_VC_CHG_NZ, cpu6811 },	1545 { "tst", OP_IX, 2, 0x6d, 6, 6, CLR_VC_CHG_NZ, cpu6811, 0 },

1032 { "tst", OP_IY \| OP_PAGE2, 3, 0x6d, 7, 7, CLR_VC_CHG_NZ, cpu6811 },	1546 { "tst", OP_IY \| OP_PAGE2, 3, 0x6d, 7, 7, CLR_VC_CHG_NZ, cpu6811, 0 },

1033 { "tst", OP_IND16, 3, 0xf7, 3, 3, CLR_VC_CHG_NZ, cpu6812 },	1547 { "tst", OP_IND16, 3, 0xf7, 3, 3, CLR_VC_CHG_NZ, cpu6812\|cpu9s12x , 0 },

1034 { "tst", OP_IDX, 2, 0xe7, 3, 3, CLR_VC_CHG_NZ, cpu6812 },	1548 { "tst", OP_IDX, 2, 0xe7, 3, 3, CLR_VC_CHG_NZ, cpu6812\|cpu9s12x , 0 },

1035 { "tst", OP_IDX_1, 3, 0xe7, 3, 3, CLR_VC_CHG_NZ, cpu6812 },	1549 { "tst", OP_IDX_1, 3, 0xe7, 3, 3, CLR_VC_CHG_NZ, cpu6812\|cpu9s12x , 0 },

1036 { "tst", OP_IDX_2, 4, 0xe7, 4, 4, CLR_VC_CHG_NZ, cpu6812 },	1550 { "tst", OP_IDX_2, 4, 0xe7, 4, 4, CLR_VC_CHG_NZ, cpu6812\|cpu9s12x , 0 },

1037 { "tst", OP_D_IDX, 2, 0xe7, 6, 6, CLR_VC_CHG_NZ, cpu6812 },	1551 { "tst", OP_D_IDX, 2, 0xe7, 6, 6, CLR_VC_CHG_NZ, cpu6812\|cpu9s12x , 0 },

1038 { "tst", OP_D_IDX_2, 4, 0xe7, 6, 6, CLR_VC_CHG_NZ, cpu6812 },	1552 { "tst", OP_D_IDX_2, 4, 0xe7, 6, 6, CLR_VC_CHG_NZ, cpu6812\|cpu9s12x , 0 },

1039	1553

1040 { "tsta", OP_NONE, 1, 0x4d, 2, 2, CLR_VC_CHG_NZ, cpu6811 },	1554 { "tsta", OP_NONE, 1, 0x4d, 2, 2, CLR_VC_CHG_NZ, cpu6811, 0 },

1041 { "tsta", OP_NONE, 1, 0x97, 1, 1, CLR_VC_CHG_NZ, cpu6812 },	1555 { "tsta", OP_NONE, 1, 0x97, 1, 1, CLR_VC_CHG_NZ, cpu6812\|cpu9s12x , 0 },

1042 { "tstb", OP_NONE, 1, 0x5d, 2, 2, CLR_VC_CHG_NZ, cpu6811 },	1556 { "tstb", OP_NONE, 1, 0x5d, 2, 2, CLR_VC_CHG_NZ, cpu6811, 0 },

1043 { "tstb", OP_NONE, 1, 0xd7, 1, 1, CLR_VC_CHG_NZ, cpu6812 },	1557 { "tstb", OP_NONE, 1, 0xd7, 1, 1, CLR_VC_CHG_NZ, cpu6812\|cpu9s12x , 0 },

1044	1558

1045 { "tsx", OP_NONE, 1, 0x30, 3, 3, CHG_NONE, cpu6811 },	1559 { "tstw", OP_IND16\| OP_PAGE2, 3, 0xf7, 3, 3, CLR_VC_CHG_NZ, cpu9s 12x, 0 },

1046 { "tsy", OP_NONE \| OP_PAGE2,2, 0x30, 4, 4, CHG_NONE, cpu6811 },	1560 { "tstw", OP_IDX\| OP_PAGE2, 2, 0xe7, 3, 3, CLR_VC_CHG_NZ, cpu9s 12x, 0 },

1047 { "txs", OP_NONE, 1, 0x35, 3, 3, CHG_NONE, cpu6811 },	1561 { "tstw", OP_IDX_1\| OP_PAGE2, 3, 0xe7, 3, 3, CLR_VC_CHG_NZ, cpu9s 12x, 0 },

1048 { "tys", OP_NONE \| OP_PAGE2,2, 0x35, 4, 4, CHG_NONE, cpu6811 },	1562 { "tstw", OP_IDX_2\| OP_PAGE2, 4, 0xe7, 4, 4, CLR_VC_CHG_NZ, cpu9s 12x, 0 },

1049	1563 { "tstw", OP_D_IDX\| OP_PAGE2, 2, 0xe7, 6, 6, CLR_VC_CHG_NZ, cpu9s 12x, 0 },

1050 { "wai", OP_NONE, 1, 0x3e, 5, _M, CHG_NONE, cpu6811\|cpu6812 },	1564 { "tstw", OP_D_IDX_2\| OP_PAGE2, 4, 0xe7, 6, 6, CLR_VC_CHG_NZ, cpu9s 12x, 0 },

1051	1565

1052 { "wav", OP_NONE \| OP_PAGE2, 2, 0x3c, 8, _M, SET_Z_CHG_HNVC, cpu6812 },	1566 { "tstx", OP_NONE\| OP_PAGE2, 1, 0x97, 1, 1, CLR_VC_CHG_NZ, cpu9s1 2x, 0 },

1053	1567 { "tsty", OP_NONE\| OP_PAGE2, 1, 0xd7, 1, 1, CLR_VC_CHG_NZ, cpu9s1 2x, 0 },

1054 { "xgdx", OP_NONE, 1, 0x8f, 3, 3, CHG_NONE, cpu6811 },	1568

1055 { "xgdy", OP_NONE \| OP_PAGE2,2, 0x8f, 4, 4, CHG_NONE, cpu6811 }	1569 { "tsx", OP_NONE, 1, 0x30, 3, 3, CHG_NONE, cpu6811, 0 },

	1570 { "tsy", OP_NONE \| OP_PAGE2,2, 0x30, 4, 4, CHG_NONE, cpu6811, 0 },

	1571 { "txs", OP_NONE, 1, 0x35, 3, 3, CHG_NONE, cpu6811, 0 },

	1572 { "tys", OP_NONE \| OP_PAGE2,2, 0x35, 4, 4, CHG_NONE, cpu6811, 0 },

	1573

	1574 { "wai", OP_NONE, 1, 0x3e, 5, _M, CHG_NONE, cpu6811\|cpu6812\|cpu9s 12x, 0 },

	1575

	1576 { "wav", OP_NONE \| OP_PAGE2, 2, 0x3c, 8, _M, SET_Z_CHG_HNVC, cpu6812\|cpu9s1 2x, 0 },

	1577

	1578 { "xgdx", OP_NONE, 1, 0x8f, 3, 3, CHG_NONE, cpu6811, 0 },

	1579 { "xgdy", OP_NONE \| OP_PAGE2,2, 0x8f, 4, 4, CHG_NONE, cpu6811, 0 },

	1580

	1581 /* XGATE opcodes */

	1582 /* Return to Scheduler and Others*/

	1583 { "brk", M68XG_OP_NONE, 2, 0x0000, 0, 0, 0, 0, 0, cpuxgate, 0xffff },

	1584 { "nop", M68XG_OP_NONE, 2, 0x0100, 0, 0, 0, 0, 0, cpuxgate, 0xffff },

	1585 { "rts", M68XG_OP_NONE, 2, 0x0200, 0, 0, 0, 0, 0, cpuxgate, 0xffff },

	1586 { "sif", M68XG_OP_NONE, 2, 0x0300, 0, 0, 0, 0, 0, cpuxgate, 0xffff },

	1587 /* Semaphore Instructions */

	1588 { "csem", M68XG_OP_IMM3, 2, 0x00f0, 0, 0, 0, 0, 0, cpuxgate, 0xf8ff },

	1589 { "csem", M68XG_OP_R, 2, 0x00f1, 0, 0, 0, 0, 0, cpuxgate, 0xf8ff },

	1590 { "ssem", M68XG_OP_IMM3, 2, 0x00f2, 0, 0, 0, 0, 0, cpuxgate, 0xf8ff },

	1591 { "ssem", M68XG_OP_R, 2, 0x00f3, 0, 0, 0, 0, 0, cpuxgate, 0xf8ff },

	1592 /* Single Register Instructions */

	1593 { "sex", M68XG_OP_R, 2, 0x00f4, 0, 0, 0, 0, 0, cpuxgate, 0xf8ff },

	1594 { "par", M68XG_OP_R, 2, 0x00f5, 0, 0, 0, 0, 0, cpuxgate, 0xf8ff },

	1595 { "jal", M68XG_OP_R, 2, 0x00f6, 0, 0, 0, 0, 0, cpuxgate, 0xf8ff },

	1596 { "sif", M68XG_OP_R, 2, 0x00f7, 0, 0, 0, 0, 0, cpuxgate, 0xf8ff },

	1597 /* Special Move instructions */

	1598 { "tfr", M68XG_OP_R, 2, 0x00f8, 0, 0, 0, 0, 0, cpuxgate, 0xf8ff }, /* RD,CCR */

	1599 { "tfr", M68XG_OP_R, 2, 0x00f9, 0, 0, 0, 0, 0, cpuxgate, 0xf8ff }, /* CCR,RS */

	1600 { "tfr", M68XG_OP_R, 2, 0x00fa, 0, 0, 0, 0, 0, cpuxgate, 0xf8ff }, /* RD,PC */

	1601 /* Shift instructions Dyadic */

	1602 { "bffo", M68XG_OP_R_R, 2, 0x0810, 0, 0, 0, 0, 0, cpuxgate, 0xf81f },

	1603 { "asr", M68XG_OP_R_R, 2, 0x0811, 0, 0, 0, 0, 0, cpuxgate, 0xf81f },

	1604 { "csl", M68XG_OP_R_R, 2, 0x0812, 0, 0, 0, 0, 0, cpuxgate, 0xf81f },

	1605 { "csr", M68XG_OP_R_R, 2, 0x0813, 0, 0, 0, 0, 0, cpuxgate, 0xf81f },

	1606 { "lsl", M68XG_OP_R_R, 2, 0x0814, 0, 0, 0, 0, 0, cpuxgate, 0xf81f },

	1607 { "lsr", M68XG_OP_R_R, 2, 0x0815, 0, 0, 0, 0, 0, cpuxgate, 0xf81f },

	1608 { "rol", M68XG_OP_R_R, 2, 0x0816, 0, 0, 0, 0, 0, cpuxgate, 0xf81f },

	1609 { "ror", M68XG_OP_R_R, 2, 0x0817, 0, 0, 0, 0, 0, cpuxgate, 0xf81f },

	1610 /* Dyadic aliases */

	1611 { "cmp", M68XG_OP_R_R, 2, 0x1800, 0, 0, 0, 0, 0, cpuxgate, 0x0000 },

	1612 { "com", M68XG_OP_R_R, 2, 0x1003, 0, 0, 0, 0, 0, cpuxgate, 0x0000 },

	1613 { "cpc", M68XG_OP_R_R, 2, 0x1801, 0, 0, 0, 0, 0, cpuxgate, 0x0000 },

	1614 { "mov", M68XG_OP_R_R, 2, 0x1002, 0, 0, 0, 0, 0, cpuxgate, 0x0000 },

	1615 { "neg", M68XG_OP_R_R, 2, 0x1800, 0, 0, 0, 0, 0, cpuxgate, 0x0000 },

	1616 /* Monadic aliases */

	1617 { "com", M68XG_OP_R, 2, 0x1003, 0, 0, 0, 0, 0, cpuxgate, 0x0000 },

	1618 { "neg", M68XG_OP_R, 2, 0x1800, 0, 0, 0, 0, 0, cpuxgate, 0x0000 },

	1619 { "tst", M68XG_OP_R, 2, 0x1800, 0, 0, 0, 0, 0, cpuxgate, 0x0000 },

	1620 /* Shift instructions immediate */

	1621 { "asr", M68XG_OP_R_IMM4, 2, 0x0809, 0, 0, 0, 0, 0, cpuxgate, 0xf80f },

	1622 { "csl", M68XG_OP_R_IMM4, 2, 0x080a, 0, 0, 0, 0, 0, cpuxgate, 0xf80f },

	1623 { "csr", M68XG_OP_R_IMM4, 2, 0x080b, 0, 0, 0, 0, 0, cpuxgate, 0xf80f },

	1624 { "lsl", M68XG_OP_R_IMM4, 2, 0x080c, 0, 0, 0, 0, 0, cpuxgate, 0xf80f },

	1625 { "lsr", M68XG_OP_R_IMM4, 2, 0x080d, 0, 0, 0, 0, 0, cpuxgate, 0xf80f },

	1626 { "rol", M68XG_OP_R_IMM4, 2, 0x080e, 0, 0, 0, 0, 0, cpuxgate, 0xf80f },

	1627 { "ror", M68XG_OP_R_IMM4, 2, 0x080f, 0, 0, 0, 0, 0, cpuxgate, 0xf80f },

	1628 /* Logical Triadic */

	1629 { "and", M68XG_OP_R_R_R, 2, 0x1000, 0, 0, 0, 0, 0, cpuxgate, 0xf803 },

	1630 { "or", M68XG_OP_R_R_R, 2, 0x1002, 0, 0, 0, 0, 0, cpuxgate, 0xf803 },

	1631 { "xnor", M68XG_OP_R_R_R, 2, 0x1003, 0, 0, 0, 0, 0, cpuxgate, 0xf803 },

	1632 /* Arithmetic Triadic */

	1633 { "sub", M68XG_OP_R_R_R, 2, 0x1800, 0, 0, 0, 0, 0, cpuxgate, 0xf803 },

	1634 { "sbc", M68XG_OP_R_R_R, 2, 0x1801, 0, 0, 0, 0, 0, cpuxgate, 0xf803 },

	1635 { "add", M68XG_OP_R_R_R, 2, 0x1802, 0, 0, 0, 0, 0, cpuxgate, 0xf803 },

	1636 { "adc", M68XG_OP_R_R_R, 2, 0x1803, 0, 0, 0, 0, 0, cpuxgate, 0xf803 },

	1637 /* Branches */

	1638 { "bcc", M68XG_OP_REL9, 2, 0x2000, 0, 0, 0, 0, 0, cpuxgate, 0xfe00 },

	1639 { "bhs", M68XG_OP_REL9, 2, 0x2000, 0, 0, 0, 0, 0, cpuxgate, 0x0000 }, /* Synonym. */

	1640 { "bcs", M68XG_OP_REL9, 2, 0x2200, 0, 0, 0, 0, 0, cpuxgate, 0xfe00 },

	1641 { "blo", M68XG_OP_REL9, 2, 0x2200, 0, 0, 0, 0, 0, cpuxgate, 0xfe00 }, /* Synonym. */

	1642 { "bne", M68XG_OP_REL9, 2, 0x2400, 0, 0, 0, 0, 0, cpuxgate, 0xfe00 },

	1643 { "beq", M68XG_OP_REL9, 2, 0x2600, 0, 0, 0, 0, 0, cpuxgate, 0xfe00 },

	1644 { "bpl", M68XG_OP_REL9, 2, 0x2800, 0, 0, 0, 0, 0, cpuxgate, 0xfe00 },

	1645 { "bmi", M68XG_OP_REL9, 2, 0x2a00, 0, 0, 0, 0, 0, cpuxgate, 0xfe00 },

	1646 { "bvc", M68XG_OP_REL9, 2, 0x2c00, 0, 0, 0, 0, 0, cpuxgate, 0xfe00 },

	1647 { "bvs", M68XG_OP_REL9, 2, 0x2e00, 0, 0, 0, 0, 0, cpuxgate, 0xfe00 },

	1648 { "bhi", M68XG_OP_REL9, 2, 0x3000, 0, 0, 0, 0, 0, cpuxgate, 0xfe00 },

	1649 { "bls", M68XG_OP_REL9, 2, 0x3200, 0, 0, 0, 0, 0, cpuxgate, 0xfe00 },

	1650 { "bge", M68XG_OP_REL9, 2, 0x3400, 0, 0, 0, 0, 0, cpuxgate, 0xfe00 },

	1651 { "blt", M68XG_OP_REL9, 2, 0x3600, 0, 0, 0, 0, 0, cpuxgate, 0xfe00 },

	1652 { "bgt", M68XG_OP_REL9, 2, 0x3800, 0, 0, 0, 0, 0, cpuxgate, 0xfe00 },

	1653 { "ble", M68XG_OP_REL9, 2, 0x3a00, 0, 0, 0, 0, 0, cpuxgate, 0xfe00 },

	1654 { "bra", M68XG_OP_REL10, 2, 0x3c00, 0, 0, 0, 0, 0, cpuxgate, 0xfc00 },

	1655 /* Load and Store Instructions */

	1656 { "ldb", M68XG_OP_R_R_OFFS5, 2, 0x4000, 0, 0, 0, 0, 0, cpuxgate, 0xf800 },

	1657 { "ldw", M68XG_OP_R_R_OFFS5, 2, 0x4800, 0, 0, 0, 0, 0, cpuxgate, 0xf800 },

	1658 { "stb", M68XG_OP_R_R_OFFS5, 2, 0x5000, 0, 0, 0, 0, 0, cpuxgate, 0xf800 },

	1659 { "stw", M68XG_OP_R_R_OFFS5, 2, 0x5800, 0, 0, 0, 0, 0, cpuxgate, 0xf800 },

	1660

	1661 { "ldb", M68XG_OP_RD_RB_RI, 2, 0x6000, 0, 0, 0, 0, 0, cpuxgate, 0xf803 },

	1662 { "ldw", M68XG_OP_RD_RB_RI, 2, 0x6800, 0, 0, 0, 0, 0, cpuxgate, 0xf803 },

	1663 { "stb", M68XG_OP_RD_RB_RI, 2, 0x7000, 0, 0, 0, 0, 0, cpuxgate, 0xf803 },

	1664 { "stw", M68XG_OP_RD_RB_RI, 2, 0x7800, 0, 0, 0, 0, 0, cpuxgate, 0xf803 },

	1665

	1666 { "ldb", M68XG_OP_RD_RB_RIp, 2, 0x6001, 0, 0, 0, 0, 0, cpuxgate, 0xf803 },

	1667 { "ldw", M68XG_OP_RD_RB_RIp, 2, 0x6801, 0, 0, 0, 0, 0, cpuxgate, 0xf803 },

	1668 { "stb", M68XG_OP_RD_RB_RIp, 2, 0x7001, 0, 0, 0, 0, 0, cpuxgate, 0xf803 },

	1669 { "stw", M68XG_OP_RD_RB_RIp, 2, 0x7801, 0, 0, 0, 0, 0, cpuxgate, 0xf803 },

	1670

	1671 { "ldb", M68XG_OP_RD_RB_mRI, 2, 0x6002, 0, 0, 0, 0, 0, cpuxgate, 0xf803 },

	1672 { "ldw", M68XG_OP_RD_RB_mRI, 2, 0x6802, 0, 0, 0, 0, 0, cpuxgate, 0xf803 },

	1673 { "stb", M68XG_OP_RD_RB_mRI, 2, 0x7002, 0, 0, 0, 0, 0, cpuxgate, 0xf803 },

	1674 { "stw", M68XG_OP_RD_RB_mRI, 2, 0x7802, 0, 0, 0, 0, 0, cpuxgate, 0xf803 },

	1675 /* Bit Field Instructions */

	1676 { "bfext", M68XG_OP_R_R_R, 2, 0x6003, 0, 0, 0, 0, 0, cpuxgate, 0xf803 },

	1677 { "bfins", M68XG_OP_R_R_R, 2, 0x6803, 0, 0, 0, 0, 0, cpuxgate, 0xf803 },

	1678 { "bfinsi",M68XG_OP_R_R_R, 2, 0x7003, 0, 0, 0, 0, 0, cpuxgate, 0xf803 },

	1679 { "bfinsx",M68XG_OP_R_R_R, 2, 0x7803, 0, 0, 0, 0, 0, cpuxgate, 0xf803 },

	1680 /* Logic Immediate Instructions */

	1681 { "andl", M68XG_OP_R_IMM8, 2, 0x8000, 0, 0, 0, 0, 0, cpuxgate, 0xf800 },

	1682 { "andh", M68XG_OP_R_IMM8, 2, 0x8800, 0, 0, 0, 0, 0, cpuxgate, 0xf800 },

	1683 { "bitl", M68XG_OP_R_IMM8, 2, 0x9000, 0, 0, 0, 0, 0, cpuxgate, 0xf800 },

	1684 { "bith", M68XG_OP_R_IMM8, 2, 0x9800, 0, 0, 0, 0, 0, cpuxgate, 0xf800 },

	1685 { "orl", M68XG_OP_R_IMM8, 2, 0xa000, 0, 0, 0, 0, 0, cpuxgate, 0xf800 },

	1686 { "orh", M68XG_OP_R_IMM8, 2, 0xa800, 0, 0, 0, 0, 0, cpuxgate, 0xf800 },

	1687 { "xnorl", M68XG_OP_R_IMM8, 2, 0xb000, 0, 0, 0, 0, 0, cpuxgate, 0xf800 },

	1688 { "xnorh", M68XG_OP_R_IMM8, 2, 0xb800, 0, 0, 0, 0, 0, cpuxgate, 0xf800 },

	1689 /* Arithmetic Immediate Instructions */

	1690 { "subl", M68XG_OP_R_IMM8, 2, 0xc000, 0, 0, 0, 0, 0, cpuxgate, 0xf800 },

	1691 { "subh", M68XG_OP_R_IMM8, 2, 0xc800, 0, 0, 0, 0, 0, cpuxgate, 0xf800 },

	1692 { "cmpl", M68XG_OP_R_IMM8, 2, 0xd000, 0, 0, 0, 0, 0, cpuxgate, 0xf800 },

	1693 { "cpch", M68XG_OP_R_IMM8, 2, 0xd800, 0, 0, 0, 0, 0, cpuxgate, 0xf800 },

	1694 { "addl", M68XG_OP_R_IMM8, 2, 0xe000, 0, 0, 0, 0, 0, cpuxgate, 0xf800 },

	1695 { "addh", M68XG_OP_R_IMM8, 2, 0xe800, 0, 0, 0, 0, 0, cpuxgate, 0xf800 },

	1696 { "ldl", M68XG_OP_R_IMM8, 2, 0xf000, 0, 0, 0, 0, 0, cpuxgate, 0xf800 },

	1697 { "ldh", M68XG_OP_R_IMM8, 2, 0xf800, 0, 0, 0, 0, 0, cpuxgate, 0xf800 },

	1698 /* 16 bit versions.

	1699 * These are pseudo opcodes to allow 16 bit addresses to be passed.

	1700 * The mask ensures that we will never disassemble to these instructions.

	1701 */

	1702 /* Logic Immediate Instructions */

	1703 { "and", M68XG_OP_R_IMM16, 2, 0x8000, 0, 0, 0, 0, 0, cpuxgate, 0x0000 },

	1704 { "bit", M68XG_OP_R_IMM16, 2, 0x9000, 0, 0, 0, 0, 0, cpuxgate, 0x0000 },

	1705 { "or", M68XG_OP_R_IMM16, 2, 0xa000, 0, 0, 0, 0, 0, cpuxgate, 0x0000 },

	1706 { "xnor", M68XG_OP_R_IMM16, 2, 0xb000, 0, 0, 0, 0, 0, cpuxgate, 0x0000 },

	1707 /* Arithmetic Immediate Instructions */

	1708 { "sub", M68XG_OP_R_IMM16, 2, 0xc000, 0, 0, 0, 0, 0, cpuxgate, 0x0000 },

	1709 { "cmp", M68XG_OP_R_IMM16, 2, 0xd000, 0, 0, 0, 0, 0, cpuxgate, 0x0000 },

	1710 { "add", M68XG_OP_R_IMM16, 2, 0xe000, 0, 0, 0, 0, 0, cpuxgate, 0x0000 },

	1711 /* ld is for backwards compatability only, the correct opcode is ldw */

	1712 { "ld", M68XG_OP_R_IMM16, 2, 0xf000, 0, 0, 0, 0, 0, cpuxgate, 0x0000 },

	1713 { "ldw", M68XG_OP_R_IMM16, 2, 0xf000, 0, 0, 0, 0, 0, cpuxgate, 0x0000 }

1056 };	1714 };

1057	1715

1058 const int m68hc11_num_opcodes = TABLE_SIZE (m68hc11_opcodes);	1716 const int m68hc11_num_opcodes = TABLE_SIZE (m68hc11_opcodes);

1059	1717

1060 /* The following alias table provides source compatibility to	1718 /* The following alias table provides source compatibility to

1061 move from 68HC11 assembly to 68HC12. */	1719 move from 68HC11 assembly to 68HC12. */

1062 const struct m68hc12_opcode_alias m68hc12_alias[] = {	1720 const struct m68hc12_opcode_alias m68hc12_alias[] = {

1063 { "abx", "leax b,x", 2, 0x1a, 0xe5 },	1721 { "abx", "leax b,x", 2, 0x1a, 0xe5 },

1064 { "aby", "leay b,y", 2, 0x19, 0xed },	1722 { "aby", "leay b,y", 2, 0x19, 0xed },

1065 { "clc", "andcc #$fe", 2, 0x10, 0xfe },	1723 { "clc", "andcc #$fe", 2, 0x10, 0xfe },

1066 { "cli", "andcc #$ef", 2, 0x10, 0xef },	1724 { "cli", "andcc #$ef", 2, 0x10, 0xef },

1067 { "clv", "andcc #$fd", 2, 0x10, 0xfd },	1725 { "clv", "andcc #$fd", 2, 0x10, 0xfd },

1068 { "des", "leas -1,sp", 2, 0x1b, 0x9f },	1726 { "des", "leas -1,sp", 2, 0x1b, 0x9f },

1069 { "ins", "leas 1,sp", 2, 0x1b, 0x81 },	1727 { "ins", "leas 1,sp", 2, 0x1b, 0x81 },

1070 { "sec", "orcc #$01", 2, 0x14, 0x01 },	1728 { "sec", "orcc #$01", 2, 0x14, 0x01 },

1071 { "sei", "orcc #$10", 2, 0x14, 0x10 },	1729 { "sei", "orcc #$10", 2, 0x14, 0x10 },

1072 { "sev", "orcc #$02", 2, 0x14, 0x02 },	1730 { "sev", "orcc #$02", 2, 0x14, 0x02 },

1073 { "tap", "tfr a,ccr", 2, 0xb7, 0x02 },	1731 { "tap", "tfr a,ccr", 2, 0xb7, 0x02 },

1074 { "tpa", "tfr ccr,a", 2, 0xb7, 0x20 },	1732 { "tpa", "tfr ccr,a", 2, 0xb7, 0x20 },

1075 { "tsx", "tfr sp,x", 2, 0xb7, 0x75 },	1733 { "tsx", "tfr sp,x", 2, 0xb7, 0x75 },

1076 { "tsy", "tfr sp,y", 2, 0xb7, 0x76 },	1734 { "tsy", "tfr sp,y", 2, 0xb7, 0x76 },

1077 { "txs", "tfr x,sp", 2, 0xb7, 0x57 },	1735 { "txs", "tfr x,sp", 2, 0xb7, 0x57 },

1078 { "tys", "tfr y,sp", 2, 0xb7, 0x67 },	1736 { "tys", "tfr y,sp", 2, 0xb7, 0x67 },

1079 { "xgdx","exg d,x", 2, 0xb7, 0xc5 },	1737 { "xgdx","exg d,x", 2, 0xb7, 0xc5 },

1080 { "xgdy","exg d,y", 2, 0xb7, 0xc6 }	1738 { "xgdy","exg d,y", 2, 0xb7, 0xc6 }

1081 };	1739 };

1082 const int m68hc12_num_alias = TABLE_SIZE (m68hc12_alias);	1740 const int m68hc12_num_alias = TABLE_SIZE (m68hc12_alias);

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