opcodes/i386-opc.tbl - Issue 11969036: Merge GDB 7.5.1 - Code Review

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Issue 11969036: Merge GDB 7.5.1 (Closed) Base URL: http://git.chromium.org/native_client/nacl-gdb.git@master

Patch Set: Created 7 years, 11 months ago

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1 // i386 opcode table.	1 // i386 opcode table.

2 // Copyright 2007, 2008, 2009, 2010	2 // Copyright 2007, 2008, 2009, 2010, 2012

3 // Free Software Foundation, Inc.	3 // Free Software Foundation, Inc.

4 //	4 //

5 // This file is part of the GNU opcodes library.	5 // This file is part of the GNU opcodes library.

6 //	6 //

7 // This library is free software; you can redistribute it and/or modify	7 // This library is free software; you can redistribute it and/or modify

8 // it under the terms of the GNU General Public License as published by	8 // it under the terms of the GNU General Public License as published by

9 // the Free Software Foundation; either version 3, or (at your option)	9 // the Free Software Foundation; either version 3, or (at your option)

10 // any later version.	10 // any later version.

11 //	11 //

12 // It is distributed in the hope that it will be useful, but WITHOUT	12 // It is distributed in the hope that it will be useful, but WITHOUT

13 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY	13 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY

14 // or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public	14 // or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public

15 // License for more details.	15 // License for more details.

16 //	16 //

17 // You should have received a copy of the GNU General Public License	17 // You should have received a copy of the GNU General Public License

18 // along with GAS; see the file COPYING. If not, write to the Free	18 // along with GAS; see the file COPYING. If not, write to the Free

19 // Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA	19 // Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA

20 // 02110-1301, USA.	20 // 02110-1301, USA.

21	21

22 // Move instructions.	22 // Move instructions.

23 // We put the 64bit displacement first and we only mark constants	23 // We put the 64bit displacement first and we only mark constants

24 // larger than 32bit as Disp64.	24 // larger than 32bit as Disp64.

25 mov, 2, 0xa0, None, 1, Cpu64, D\|W\|CheckRegSize\|No_sSuf\|No_ldSuf, { Disp64\|Unspec ified\|Byte\|Word\|Dword\|Qword, Acc\|Byte\|Word\|Dword\|Qword }	25 mov, 2, 0xa0, None, 1, Cpu64, D\|W\|CheckRegSize\|No_sSuf\|No_ldSuf, { Disp64\|Unspec ified\|Byte\|Word\|Dword\|Qword, Acc\|Byte\|Word\|Dword\|Qword }

26 mov, 2, 0xa0, None, 1, CpuNo64, D\|W\|CheckRegSize\|No_sSuf\|No_qSuf\|No_ldSuf, { Dis p16\|Disp32\|Unspecified\|Byte\|Word\|Dword, Acc\|Byte\|Word\|Dword }	26 mov, 2, 0xa0, None, 1, CpuNo64, D\|W\|CheckRegSize\|No_sSuf\|No_qSuf\|No_ldSuf, { Dis p16\|Disp32\|Unspecified\|Byte\|Word\|Dword, Acc\|Byte\|Word\|Dword }

27 mov, 2, 0x88, None, 1, 0, D\|W\|CheckRegSize\|Modrm\|No_sSuf\|No_ldSuf, { Reg8\|Reg16\| Reg32\|Reg64, Reg8\|Reg16\|Reg32\|Reg64\|Byte\|Word\|Dword\|Qword\|Unspecified\|BaseIndex\| Disp8\|Disp16\|Disp32\|Disp32S }	27 mov, 2, 0x88, None, 1, 0, D\|W\|CheckRegSize\|Modrm\|No_sSuf\|No_ldSuf\|HLEPrefixOk=3, { Reg8\|Reg16\|Reg32\|Reg64, Reg8\|Reg16\|Reg32\|Reg64\|Byte\|Word\|Dword\|Qword\|Unspecif ied\|BaseIndex\|Disp8\|Disp16\|Disp32\|Disp32S }

28 // In the 64bit mode the short form mov immediate is redefined to have	28 // In the 64bit mode the short form mov immediate is redefined to have

29 // 64bit value.	29 // 64bit value.

30 mov, 2, 0xb0, None, 1, 0, W\|CheckRegSize\|ShortForm\|No_sSuf\|No_qSuf\|No_ldSuf, { I mm8\|Imm16\|Imm32\|Imm32S, Reg8\|Reg16\|Reg32 }	30 mov, 2, 0xb0, None, 1, 0, W\|CheckRegSize\|ShortForm\|No_sSuf\|No_qSuf\|No_ldSuf, { I mm8\|Imm16\|Imm32\|Imm32S, Reg8\|Reg16\|Reg32 }

31 mov, 2, 0xc6, 0x0, 1, 0, W\|CheckRegSize\|Modrm\|No_sSuf\|No_ldSuf, { Imm8\|Imm16\|Imm 32\|Imm32S, Reg8\|Reg16\|Reg32\|Reg64\|Byte\|Word\|Dword\|Qword\|Unspecified\|BaseIndex\|Di sp8\|Disp16\|Disp32\|Disp32S }	31 mov, 2, 0xc6, 0x0, 1, 0, W\|CheckRegSize\|Modrm\|No_sSuf\|No_ldSuf\|HLEPrefixOk=3, { Imm8\|Imm16\|Imm32\|Imm32S, Reg8\|Reg16\|Reg32\|Reg64\|Byte\|Word\|Dword\|Qword\|Unspecifie d\|BaseIndex\|Disp8\|Disp16\|Disp32\|Disp32S }

32 mov, 2, 0xb0, None, 1, Cpu64, W\|ShortForm\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_ldS uf, { Imm64, Reg64 }	32 mov, 2, 0xb0, None, 1, Cpu64, W\|ShortForm\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_ldS uf, { Imm64, Reg64 }

33 // The segment register moves accept WordReg so that a segment register	33 // The segment register moves accept WordReg so that a segment register

34 // can be copied to a 32 bit register, and vice versa, without using a	34 // can be copied to a 32 bit register, and vice versa, without using a

35 // size prefix. When moving to a 32 bit register, the upper 16 bits	35 // size prefix. When moving to a 32 bit register, the upper 16 bits

36 // are set to an implementation defined value (on the Pentium Pro, the	36 // are set to an implementation defined value (on the Pentium Pro, the

37 // implementation defined value is zero).	37 // implementation defined value is zero).

38 mov, 2, 0x8c, None, 1, 0, Modrm\|No_bSuf\|No_sSuf\|No_qSuf\|No_ldSuf, { SReg2, Reg16 \|Reg32\|Reg64\|RegMem }	38 mov, 2, 0x8c, None, 1, 0, Modrm\|No_bSuf\|No_sSuf\|No_qSuf\|No_ldSuf, { SReg2, Reg16 \|Reg32\|Reg64\|RegMem }

39 mov, 2, 0x8c, None, 1, 0, Modrm\|IgnoreSize\|No_bSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ld Suf, { SReg2, Word\|Unspecified\|BaseIndex\|Disp8\|Disp16\|Disp32\|Disp32S }	39 mov, 2, 0x8c, None, 1, 0, Modrm\|IgnoreSize\|No_bSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ld Suf, { SReg2, Word\|Unspecified\|BaseIndex\|Disp8\|Disp16\|Disp32\|Disp32S }

40 mov, 2, 0x8c, None, 1, Cpu386, Modrm\|No_bSuf\|No_sSuf\|No_qSuf\|No_ldSuf, { SReg3, Reg16\|Reg32\|Reg64\|RegMem }	40 mov, 2, 0x8c, None, 1, Cpu386, Modrm\|No_bSuf\|No_sSuf\|No_qSuf\|No_ldSuf, { SReg3, Reg16\|Reg32\|Reg64\|RegMem }

41 mov, 2, 0x8c, None, 1, Cpu386, Modrm\|IgnoreSize\|No_bSuf\|No_lSuf\|No_sSuf\|No_qSuf\| No_ldSuf, { SReg3, Word\|Unspecified\|BaseIndex\|Disp8\|Disp16\|Disp32\|Disp32S }	41 mov, 2, 0x8c, None, 1, Cpu386, Modrm\|IgnoreSize\|No_bSuf\|No_lSuf\|No_sSuf\|No_qSuf\| No_ldSuf, { SReg3, Word\|Unspecified\|BaseIndex\|Disp8\|Disp16\|Disp32\|Disp32S }

(...skipping 79 matching lines...) Expand 10 before \| Expand all \| Expand 10 after Loading...
121 pop, 1, 0xfa1, None, 2, Cpu64, ShortForm\|DefaultSize\|No_bSuf\|No_lSuf\|No_sSuf\|No_ ldSuf\|NoRex64, { SReg3 }	121 pop, 1, 0xfa1, None, 2, Cpu64, ShortForm\|DefaultSize\|No_bSuf\|No_lSuf\|No_sSuf\|No_ ldSuf\|NoRex64, { SReg3 }

122	122

123 popa, 0, 0x61, None, 1, Cpu186\|CpuNo64, DefaultSize\|No_bSuf\|No_sSuf\|No_qSuf\|No_l dSuf, { 0 }	123 popa, 0, 0x61, None, 1, Cpu186\|CpuNo64, DefaultSize\|No_bSuf\|No_sSuf\|No_qSuf\|No_l dSuf, { 0 }

124	124

125 // Exchange instructions.	125 // Exchange instructions.

126 // xchg commutes: we allow both operand orders.	126 // xchg commutes: we allow both operand orders.

127	127

128 // In the 64bit code, xchg rax, rax is reused for new nop instruction.	128 // In the 64bit code, xchg rax, rax is reused for new nop instruction.

129 xchg, 2, 0x90, None, 1, 0, ShortForm\|CheckRegSize\|No_bSuf\|No_sSuf\|No_ldSuf, { Re g16\|Reg32\|Reg64, Acc\|Word\|Dword\|Qword }	129 xchg, 2, 0x90, None, 1, 0, ShortForm\|CheckRegSize\|No_bSuf\|No_sSuf\|No_ldSuf, { Re g16\|Reg32\|Reg64, Acc\|Word\|Dword\|Qword }

130 xchg, 2, 0x90, None, 1, 0, ShortForm\|CheckRegSize\|No_bSuf\|No_sSuf\|No_ldSuf, { Ac c\|Word\|Dword\|Qword, Reg16\|Reg32\|Reg64 }	130 xchg, 2, 0x90, None, 1, 0, ShortForm\|CheckRegSize\|No_bSuf\|No_sSuf\|No_ldSuf, { Ac c\|Word\|Dword\|Qword, Reg16\|Reg32\|Reg64 }

131 xchg, 2, 0x86, None, 1, 0, W\|CheckRegSize\|Modrm\|No_sSuf\|No_ldSuf\|IsLockable, { R eg8\|Reg16\|Reg32\|Reg64, Reg8\|Reg16\|Reg32\|Reg64\|Byte\|Word\|Dword\|Qword\|Unspecified\| BaseIndex\|Disp8\|Disp16\|Disp32\|Disp32S }	131 xchg, 2, 0x86, None, 1, 0, W\|CheckRegSize\|Modrm\|No_sSuf\|No_ldSuf\|IsLockable\|HLEP refixOk=2, { Reg8\|Reg16\|Reg32\|Reg64, Reg8\|Reg16\|Reg32\|Reg64\|Byte\|Word\|Dword\|Qwor d\|Unspecified\|BaseIndex\|Disp8\|Disp16\|Disp32\|Disp32S }

132 xchg, 2, 0x86, None, 1, 0, W\|CheckRegSize\|Modrm\|No_sSuf\|No_ldSuf\|IsLockable, { R eg8\|Reg16\|Reg32\|Reg64\|Byte\|Word\|Dword\|Qword\|Unspecified\|BaseIndex\|Disp8\|Disp16\|D isp32\|Disp32S, Reg8\|Reg16\|Reg32\|Reg64 }	132 xchg, 2, 0x86, None, 1, 0, W\|CheckRegSize\|Modrm\|No_sSuf\|No_ldSuf\|IsLockable\|HLEP refixOk=2, { Reg8\|Reg16\|Reg32\|Reg64\|Byte\|Word\|Dword\|Qword\|Unspecified\|BaseIndex\| Disp8\|Disp16\|Disp32\|Disp32S, Reg8\|Reg16\|Reg32\|Reg64 }

133	133

134 // In/out from ports.	134 // In/out from ports.

135 in, 2, 0xe4, None, 1, 0, W\|CheckRegSize\|No_sSuf\|No_qSuf\|No_ldSuf, { Imm8, Acc\|By te\|Word\|Dword }	135 in, 2, 0xe4, None, 1, 0, W\|CheckRegSize\|No_sSuf\|No_qSuf\|No_ldSuf, { Imm8, Acc\|By te\|Word\|Dword }

136 in, 2, 0xec, None, 1, 0, W\|CheckRegSize\|No_sSuf\|No_qSuf\|No_ldSuf, { InOutPortReg , Acc\|Byte\|Word\|Dword }	136 in, 2, 0xec, None, 1, 0, W\|CheckRegSize\|No_sSuf\|No_qSuf\|No_ldSuf, { InOutPortReg , Acc\|Byte\|Word\|Dword }

137 in, 1, 0xe4, None, 1, 0, W\|No_sSuf\|No_qSuf\|No_ldSuf, { Imm8 }	137 in, 1, 0xe4, None, 1, 0, W\|No_sSuf\|No_qSuf\|No_ldSuf, { Imm8 }

138 in, 1, 0xec, None, 1, 0, W\|No_sSuf\|No_qSuf\|No_ldSuf, { InOutPortReg }	138 in, 1, 0xec, None, 1, 0, W\|No_sSuf\|No_qSuf\|No_ldSuf, { InOutPortReg }

139 out, 2, 0xe6, None, 1, 0, W\|CheckRegSize\|No_sSuf\|No_qSuf\|No_ldSuf, { Acc\|Byte\|Wo rd\|Dword, Imm8 }	139 out, 2, 0xe6, None, 1, 0, W\|CheckRegSize\|No_sSuf\|No_qSuf\|No_ldSuf, { Acc\|Byte\|Wo rd\|Dword, Imm8 }

140 out, 2, 0xee, None, 1, 0, W\|CheckRegSize\|No_sSuf\|No_qSuf\|No_ldSuf, { Acc\|Byte\|Wo rd\|Dword, InOutPortReg }	140 out, 2, 0xee, None, 1, 0, W\|CheckRegSize\|No_sSuf\|No_qSuf\|No_ldSuf, { Acc\|Byte\|Wo rd\|Dword, InOutPortReg }

141 out, 1, 0xe6, None, 1, 0, W\|No_sSuf\|No_qSuf\|No_ldSuf, { Imm8 }	141 out, 1, 0xe6, None, 1, 0, W\|No_sSuf\|No_qSuf\|No_ldSuf, { Imm8 }

142 out, 1, 0xee, None, 1, 0, W\|No_sSuf\|No_qSuf\|No_ldSuf, { InOutPortReg }	142 out, 1, 0xee, None, 1, 0, W\|No_sSuf\|No_qSuf\|No_ldSuf, { InOutPortReg }

(...skipping 18 matching lines...) Expand all Loading...
161 sahf, 0, 0x9e, None, 1, 0, No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf, { 0 }	161 sahf, 0, 0x9e, None, 1, 0, No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf, { 0 }

162 pushf, 0, 0x9c, None, 1, CpuNo64, DefaultSize\|No_bSuf\|No_sSuf\|No_qSuf\|No_ldSuf, { 0 }	162 pushf, 0, 0x9c, None, 1, CpuNo64, DefaultSize\|No_bSuf\|No_sSuf\|No_qSuf\|No_ldSuf, { 0 }

163 pushf, 0, 0x9c, None, 1, Cpu64, DefaultSize\|No_bSuf\|No_lSuf\|No_sSuf\|No_ldSuf\|NoR ex64, { 0 }	163 pushf, 0, 0x9c, None, 1, Cpu64, DefaultSize\|No_bSuf\|No_lSuf\|No_sSuf\|No_ldSuf\|NoR ex64, { 0 }

164 popf, 0, 0x9d, None, 1, CpuNo64, DefaultSize\|No_bSuf\|No_sSuf\|No_qSuf\|No_ldSuf, { 0 }	164 popf, 0, 0x9d, None, 1, CpuNo64, DefaultSize\|No_bSuf\|No_sSuf\|No_qSuf\|No_ldSuf, { 0 }

165 popf, 0, 0x9d, None, 1, Cpu64, DefaultSize\|No_bSuf\|No_lSuf\|No_sSuf\|No_ldSuf\|NoRe x64, { 0 }	165 popf, 0, 0x9d, None, 1, Cpu64, DefaultSize\|No_bSuf\|No_lSuf\|No_sSuf\|No_ldSuf\|NoRe x64, { 0 }

166 stc, 0, 0xf9, None, 1, 0, No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf, { 0 }	166 stc, 0, 0xf9, None, 1, 0, No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf, { 0 }

167 std, 0, 0xfd, None, 1, 0, No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf, { 0 }	167 std, 0, 0xfd, None, 1, 0, No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf, { 0 }

168 sti, 0, 0xfb, None, 1, 0, No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf, { 0 }	168 sti, 0, 0xfb, None, 1, 0, No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf, { 0 }

169	169

170 // Arithmetic.	170 // Arithmetic.

171 add, 2, 0x0, None, 1, 0, D\|W\|CheckRegSize\|Modrm\|No_sSuf\|No_ldSuf\|IsLockable, { R eg8\|Reg16\|Reg32\|Reg64, Reg8\|Reg16\|Reg32\|Reg64\|Byte\|Word\|Dword\|Qword\|Unspecified\| BaseIndex\|Disp8\|Disp16\|Disp32\|Disp32S }	171 add, 2, 0x0, None, 1, 0, D\|W\|CheckRegSize\|Modrm\|No_sSuf\|No_ldSuf\|IsLockable\|HLEP refixOk, { Reg8\|Reg16\|Reg32\|Reg64, Reg8\|Reg16\|Reg32\|Reg64\|Byte\|Word\|Dword\|Qword\| Unspecified\|BaseIndex\|Disp8\|Disp16\|Disp32\|Disp32S }

172 add, 2, 0x83, 0x0, 1, 0, Modrm\|No_bSuf\|No_sSuf\|No_ldSuf\|IsLockable, { Imm8S, Reg 16\|Reg32\|Reg64\|Word\|Dword\|Qword\|Unspecified\|BaseIndex\|Disp8\|Disp16\|Disp32\|Disp32 S }	172 add, 2, 0x83, 0x0, 1, 0, Modrm\|No_bSuf\|No_sSuf\|No_ldSuf\|IsLockable\|HLEPrefixOk, { Imm8S, Reg16\|Reg32\|Reg64\|Word\|Dword\|Qword\|Unspecified\|BaseIndex\|Disp8\|Disp16\|D isp32\|Disp32S }

173 add, 2, 0x4, None, 1, 0, W\|CheckRegSize\|No_sSuf\|No_ldSuf, { Imm8\|Imm16\|Imm32\|Imm 32S, Acc\|Byte\|Word\|Dword\|Qword }	173 add, 2, 0x4, None, 1, 0, W\|CheckRegSize\|No_sSuf\|No_ldSuf, { Imm8\|Imm16\|Imm32\|Imm 32S, Acc\|Byte\|Word\|Dword\|Qword }

174 add, 2, 0x80, 0x0, 1, 0, W\|CheckRegSize\|Modrm\|No_sSuf\|No_ldSuf\|IsLockable, { Imm 8\|Imm16\|Imm32\|Imm32S, Reg8\|Reg16\|Reg32\|Reg64\|Byte\|Word\|Dword\|Qword\|Unspecified\|B aseIndex\|Disp8\|Disp16\|Disp32\|Disp32S }	174 add, 2, 0x80, 0x0, 1, 0, W\|CheckRegSize\|Modrm\|No_sSuf\|No_ldSuf\|IsLockable\|HLEPre fixOk, { Imm8\|Imm16\|Imm32\|Imm32S, Reg8\|Reg16\|Reg32\|Reg64\|Byte\|Word\|Dword\|Qword\|U nspecified\|BaseIndex\|Disp8\|Disp16\|Disp32\|Disp32S }

175	175

176 inc, 1, 0x40, None, 1, CpuNo64, ShortForm\|No_bSuf\|No_sSuf\|No_qSuf\|No_ldSuf, { Re g16\|Reg32 }	176 inc, 1, 0x40, None, 1, CpuNo64, ShortForm\|No_bSuf\|No_sSuf\|No_qSuf\|No_ldSuf, { Re g16\|Reg32 }

177 inc, 1, 0xfe, 0x0, 1, 0, W\|Modrm\|No_sSuf\|No_ldSuf\|IsLockable, { Reg8\|Reg16\|Reg32 \|Reg64\|Byte\|Word\|Dword\|Qword\|Unspecified\|BaseIndex\|Disp8\|Disp16\|Disp32\|Disp32S }	177 inc, 1, 0xfe, 0x0, 1, 0, W\|Modrm\|No_sSuf\|No_ldSuf\|IsLockable\|HLEPrefixOk, { Reg8 \|Reg16\|Reg32\|Reg64\|Byte\|Word\|Dword\|Qword\|Unspecified\|BaseIndex\|Disp8\|Disp16\|Disp 32\|Disp32S }

178	178

179 sub, 2, 0x28, None, 1, 0, D\|W\|CheckRegSize\|Modrm\|No_sSuf\|No_ldSuf\|IsLockable, { Reg8\|Reg16\|Reg32\|Reg64, Reg8\|Reg16\|Reg32\|Reg64\|Byte\|Word\|Dword\|Qword\|Unspecified \|BaseIndex\|Disp8\|Disp16\|Disp32\|Disp32S }	179 sub, 2, 0x28, None, 1, 0, D\|W\|CheckRegSize\|Modrm\|No_sSuf\|No_ldSuf\|IsLockable\|HLE PrefixOk, { Reg8\|Reg16\|Reg32\|Reg64, Reg8\|Reg16\|Reg32\|Reg64\|Byte\|Word\|Dword\|Qword \|Unspecified\|BaseIndex\|Disp8\|Disp16\|Disp32\|Disp32S }

180 sub, 2, 0x83, 0x5, 1, 0, Modrm\|No_bSuf\|No_sSuf\|No_ldSuf\|IsLockable, { Imm8S, Reg 16\|Reg32\|Reg64\|Word\|Dword\|Qword\|Unspecified\|BaseIndex\|Disp8\|Disp16\|Disp32\|Disp32 S }	180 sub, 2, 0x83, 0x5, 1, 0, Modrm\|No_bSuf\|No_sSuf\|No_ldSuf\|IsLockable\|HLEPrefixOk, { Imm8S, Reg16\|Reg32\|Reg64\|Word\|Dword\|Qword\|Unspecified\|BaseIndex\|Disp8\|Disp16\|D isp32\|Disp32S }

181 sub, 2, 0x2c, None, 1, 0, W\|CheckRegSize\|No_sSuf\|No_ldSuf, { Imm8\|Imm16\|Imm32\|Im m32S, Acc\|Byte\|Word\|Dword\|Qword }	181 sub, 2, 0x2c, None, 1, 0, W\|CheckRegSize\|No_sSuf\|No_ldSuf, { Imm8\|Imm16\|Imm32\|Im m32S, Acc\|Byte\|Word\|Dword\|Qword }

182 sub, 2, 0x80, 0x5, 1, 0, W\|CheckRegSize\|Modrm\|No_sSuf\|No_ldSuf\|IsLockable, { Imm 8\|Imm16\|Imm32\|Imm32S, Reg8\|Reg16\|Reg32\|Reg64\|Byte\|Word\|Dword\|Qword\|Unspecified\|B aseIndex\|Disp8\|Disp16\|Disp32\|Disp32S }	182 sub, 2, 0x80, 0x5, 1, 0, W\|CheckRegSize\|Modrm\|No_sSuf\|No_ldSuf\|IsLockable\|HLEPre fixOk, { Imm8\|Imm16\|Imm32\|Imm32S, Reg8\|Reg16\|Reg32\|Reg64\|Byte\|Word\|Dword\|Qword\|U nspecified\|BaseIndex\|Disp8\|Disp16\|Disp32\|Disp32S }

183	183

184 dec, 1, 0x48, None, 1, CpuNo64, ShortForm\|No_bSuf\|No_sSuf\|No_qSuf\|No_ldSuf, { Re g16\|Reg32 }	184 dec, 1, 0x48, None, 1, CpuNo64, ShortForm\|No_bSuf\|No_sSuf\|No_qSuf\|No_ldSuf, { Re g16\|Reg32 }

185 dec, 1, 0xfe, 0x1, 1, 0, W\|Modrm\|No_sSuf\|No_ldSuf\|IsLockable, { Reg8\|Reg16\|Reg32 \|Reg64\|Byte\|Word\|Dword\|Qword\|Unspecified\|BaseIndex\|Disp8\|Disp16\|Disp32\|Disp32S }	185 dec, 1, 0xfe, 0x1, 1, 0, W\|Modrm\|No_sSuf\|No_ldSuf\|IsLockable\|HLEPrefixOk, { Reg8 \|Reg16\|Reg32\|Reg64\|Byte\|Word\|Dword\|Qword\|Unspecified\|BaseIndex\|Disp8\|Disp16\|Disp 32\|Disp32S }

186	186

187 sbb, 2, 0x18, None, 1, 0, D\|W\|CheckRegSize\|Modrm\|No_sSuf\|No_ldSuf\|IsLockable, { Reg8\|Reg16\|Reg32\|Reg64, Reg8\|Reg16\|Reg32\|Reg64\|Byte\|Word\|Dword\|Qword\|Unspecified \|BaseIndex\|Disp8\|Disp16\|Disp32\|Disp32S }	187 sbb, 2, 0x18, None, 1, 0, D\|W\|CheckRegSize\|Modrm\|No_sSuf\|No_ldSuf\|IsLockable\|HLE PrefixOk, { Reg8\|Reg16\|Reg32\|Reg64, Reg8\|Reg16\|Reg32\|Reg64\|Byte\|Word\|Dword\|Qword \|Unspecified\|BaseIndex\|Disp8\|Disp16\|Disp32\|Disp32S }

188 sbb, 2, 0x83, 0x3, 1, 0, Modrm\|No_bSuf\|No_sSuf\|No_ldSuf\|IsLockable, { Imm8S, Reg 16\|Reg32\|Reg64\|Word\|Dword\|Qword\|Unspecified\|BaseIndex\|Disp8\|Disp16\|Disp32\|Disp32 S }	188 sbb, 2, 0x83, 0x3, 1, 0, Modrm\|No_bSuf\|No_sSuf\|No_ldSuf\|IsLockable\|HLEPrefixOk, { Imm8S, Reg16\|Reg32\|Reg64\|Word\|Dword\|Qword\|Unspecified\|BaseIndex\|Disp8\|Disp16\|D isp32\|Disp32S }

189 sbb, 2, 0x1c, None, 1, 0, W\|CheckRegSize\|No_sSuf\|No_ldSuf, { Imm8\|Imm16\|Imm32\|Im m32S, Acc\|Byte\|Word\|Dword\|Qword }	189 sbb, 2, 0x1c, None, 1, 0, W\|CheckRegSize\|No_sSuf\|No_ldSuf, { Imm8\|Imm16\|Imm32\|Im m32S, Acc\|Byte\|Word\|Dword\|Qword }

190 sbb, 2, 0x80, 0x3, 1, 0, W\|CheckRegSize\|Modrm\|No_sSuf\|No_ldSuf\|IsLockable, { Imm 8\|Imm16\|Imm32\|Imm32S, Reg8\|Reg16\|Reg32\|Reg64\|Byte\|Word\|Dword\|Qword\|Unspecified\|B aseIndex\|Disp8\|Disp16\|Disp32\|Disp32S }	190 sbb, 2, 0x80, 0x3, 1, 0, W\|CheckRegSize\|Modrm\|No_sSuf\|No_ldSuf\|IsLockable\|HLEPre fixOk, { Imm8\|Imm16\|Imm32\|Imm32S, Reg8\|Reg16\|Reg32\|Reg64\|Byte\|Word\|Dword\|Qword\|U nspecified\|BaseIndex\|Disp8\|Disp16\|Disp32\|Disp32S }

191	191

192 cmp, 2, 0x38, None, 1, 0, D\|W\|CheckRegSize\|Modrm\|No_sSuf\|No_ldSuf, { Reg8\|Reg16\| Reg32\|Reg64, Reg8\|Reg16\|Reg32\|Reg64\|Byte\|Word\|Dword\|Qword\|Unspecified\|BaseIndex\| Disp8\|Disp16\|Disp32\|Disp32S }	192 cmp, 2, 0x38, None, 1, 0, D\|W\|CheckRegSize\|Modrm\|No_sSuf\|No_ldSuf, { Reg8\|Reg16\| Reg32\|Reg64, Reg8\|Reg16\|Reg32\|Reg64\|Byte\|Word\|Dword\|Qword\|Unspecified\|BaseIndex\| Disp8\|Disp16\|Disp32\|Disp32S }

193 cmp, 2, 0x83, 0x7, 1, 0, Modrm\|No_bSuf\|No_sSuf\|No_ldSuf, { Imm8S, Reg16\|Reg32\|Re g64\|Word\|Dword\|Qword\|Unspecified\|BaseIndex\|Disp8\|Disp16\|Disp32\|Disp32S }	193 cmp, 2, 0x83, 0x7, 1, 0, Modrm\|No_bSuf\|No_sSuf\|No_ldSuf, { Imm8S, Reg16\|Reg32\|Re g64\|Word\|Dword\|Qword\|Unspecified\|BaseIndex\|Disp8\|Disp16\|Disp32\|Disp32S }

194 cmp, 2, 0x3c, None, 1, 0, W\|CheckRegSize\|No_sSuf\|No_ldSuf, { Imm8\|Imm16\|Imm32\|Im m32S, Acc\|Byte\|Word\|Dword\|Qword }	194 cmp, 2, 0x3c, None, 1, 0, W\|CheckRegSize\|No_sSuf\|No_ldSuf, { Imm8\|Imm16\|Imm32\|Im m32S, Acc\|Byte\|Word\|Dword\|Qword }

195 cmp, 2, 0x80, 0x7, 1, 0, W\|CheckRegSize\|Modrm\|No_sSuf\|No_ldSuf, { Imm8\|Imm16\|Imm 32\|Imm32S, Reg8\|Reg16\|Reg32\|Reg64\|Byte\|Word\|Dword\|Qword\|Unspecified\|BaseIndex\|Di sp8\|Disp16\|Disp32\|Disp32S }	195 cmp, 2, 0x80, 0x7, 1, 0, W\|CheckRegSize\|Modrm\|No_sSuf\|No_ldSuf, { Imm8\|Imm16\|Imm 32\|Imm32S, Reg8\|Reg16\|Reg32\|Reg64\|Byte\|Word\|Dword\|Qword\|Unspecified\|BaseIndex\|Di sp8\|Disp16\|Disp32\|Disp32S }

196	196

197 test, 2, 0x84, None, 1, 0, W\|CheckRegSize\|Modrm\|No_sSuf\|No_ldSuf, { Reg8\|Reg16\|R eg32\|Reg64, Reg8\|Reg16\|Reg32\|Reg64\|Unspecified\|Byte\|Word\|Dword\|Qword\|BaseIndex\|D isp8\|Disp16\|Disp32\|Disp32S }	197 test, 2, 0x84, None, 1, 0, W\|CheckRegSize\|Modrm\|No_sSuf\|No_ldSuf, { Reg8\|Reg16\|R eg32\|Reg64, Reg8\|Reg16\|Reg32\|Reg64\|Unspecified\|Byte\|Word\|Dword\|Qword\|BaseIndex\|D isp8\|Disp16\|Disp32\|Disp32S }

198 test, 2, 0x84, None, 1, 0, W\|CheckRegSize\|Modrm\|No_sSuf\|No_ldSuf, { Byte\|Word\|Dw ord\|Qword\|Unspecified\|BaseIndex\|Disp8\|Disp16\|Disp32\|Disp32S, Reg8\|Reg16\|Reg32\|Re g64 }	198 test, 2, 0x84, None, 1, 0, W\|CheckRegSize\|Modrm\|No_sSuf\|No_ldSuf, { Byte\|Word\|Dw ord\|Qword\|Unspecified\|BaseIndex\|Disp8\|Disp16\|Disp32\|Disp32S, Reg8\|Reg16\|Reg32\|Re g64 }

199 test, 2, 0xa8, None, 1, 0, W\|CheckRegSize\|No_sSuf\|No_ldSuf, { Imm8\|Imm16\|Imm32\|I mm32S, Acc\|Byte\|Word\|Dword\|Qword }	199 test, 2, 0xa8, None, 1, 0, W\|CheckRegSize\|No_sSuf\|No_ldSuf, { Imm8\|Imm16\|Imm32\|I mm32S, Acc\|Byte\|Word\|Dword\|Qword }

200 test, 2, 0xf6, 0x0, 1, 0, W\|CheckRegSize\|Modrm\|No_sSuf\|No_ldSuf, { Imm8\|Imm16\|Im m32\|Imm32S, Reg8\|Reg16\|Reg32\|Reg64\|Byte\|Word\|Dword\|Qword\|Unspecified\|BaseIndex\|D isp8\|Disp16\|Disp32\|Disp32S }	200 test, 2, 0xf6, 0x0, 1, 0, W\|CheckRegSize\|Modrm\|No_sSuf\|No_ldSuf, { Imm8\|Imm16\|Im m32\|Imm32S, Reg8\|Reg16\|Reg32\|Reg64\|Byte\|Word\|Dword\|Qword\|Unspecified\|BaseIndex\|D isp8\|Disp16\|Disp32\|Disp32S }

201	201

202 and, 2, 0x20, None, 1, 0, D\|W\|CheckRegSize\|Modrm\|No_sSuf\|No_ldSuf\|IsLockable, { Reg8\|Reg16\|Reg32\|Reg64, Reg8\|Reg16\|Reg32\|Reg64\|Byte\|Word\|Dword\|Qword\|Unspecified \|BaseIndex\|Disp8\|Disp16\|Disp32\|Disp32S }	202 and, 2, 0x20, None, 1, 0, D\|W\|CheckRegSize\|Modrm\|No_sSuf\|No_ldSuf\|IsLockable\|HLE PrefixOk, { Reg8\|Reg16\|Reg32\|Reg64, Reg8\|Reg16\|Reg32\|Reg64\|Byte\|Word\|Dword\|Qword \|Unspecified\|BaseIndex\|Disp8\|Disp16\|Disp32\|Disp32S }

203 and, 2, 0x83, 0x4, 1, 0, Modrm\|No_bSuf\|No_sSuf\|No_ldSuf\|IsLockable, { Imm8S, Reg 16\|Reg32\|Reg64\|Word\|Dword\|Qword\|Unspecified\|BaseIndex\|Disp8\|Disp16\|Disp32\|Disp32 S }	203 and, 2, 0x83, 0x4, 1, 0, Modrm\|No_bSuf\|No_sSuf\|No_ldSuf\|IsLockable\|HLEPrefixOk, { Imm8S, Reg16\|Reg32\|Reg64\|Word\|Dword\|Qword\|Unspecified\|BaseIndex\|Disp8\|Disp16\|D isp32\|Disp32S }

204 and, 2, 0x24, None, 1, 0, W\|CheckRegSize\|No_sSuf\|No_ldSuf, { Imm8\|Imm16\|Imm32\|Im m32S, Acc\|Byte\|Word\|Dword\|Qword }	204 and, 2, 0x24, None, 1, 0, W\|CheckRegSize\|No_sSuf\|No_ldSuf, { Imm8\|Imm16\|Imm32\|Im m32S, Acc\|Byte\|Word\|Dword\|Qword }

205 and, 2, 0x80, 0x4, 1, 0, W\|CheckRegSize\|Modrm\|No_sSuf\|No_ldSuf\|IsLockable, { Imm 8\|Imm16\|Imm32\|Imm32S, Reg8\|Reg16\|Reg32\|Reg64\|Byte\|Word\|Dword\|Qword\|Unspecified\|B aseIndex\|Disp8\|Disp16\|Disp32\|Disp32S }	205 and, 2, 0x80, 0x4, 1, 0, W\|CheckRegSize\|Modrm\|No_sSuf\|No_ldSuf\|IsLockable\|HLEPre fixOk, { Imm8\|Imm16\|Imm32\|Imm32S, Reg8\|Reg16\|Reg32\|Reg64\|Byte\|Word\|Dword\|Qword\|U nspecified\|BaseIndex\|Disp8\|Disp16\|Disp32\|Disp32S }

206	206

207 or, 2, 0x8, None, 1, 0, D\|W\|CheckRegSize\|Modrm\|No_sSuf\|No_ldSuf\|IsLockable, { Re g8\|Reg16\|Reg32\|Reg64, Reg8\|Reg16\|Reg32\|Reg64\|Byte\|Word\|Dword\|Qword\|Unspecified\|B aseIndex\|Disp8\|Disp16\|Disp32\|Disp32S }	207 or, 2, 0x8, None, 1, 0, D\|W\|CheckRegSize\|Modrm\|No_sSuf\|No_ldSuf\|IsLockable\|HLEPr efixOk, { Reg8\|Reg16\|Reg32\|Reg64, Reg8\|Reg16\|Reg32\|Reg64\|Byte\|Word\|Dword\|Qword\|U nspecified\|BaseIndex\|Disp8\|Disp16\|Disp32\|Disp32S }

208 or, 2, 0x83, 0x1, 1, 0, Modrm\|No_bSuf\|No_sSuf\|No_ldSuf\|IsLockable, { Imm8S, Reg1 6\|Reg32\|Reg64\|Word\|Dword\|Qword\|Unspecified\|BaseIndex\|Disp8\|Disp16\|Disp32\|Disp32S }	208 or, 2, 0x83, 0x1, 1, 0, Modrm\|No_bSuf\|No_sSuf\|No_ldSuf\|IsLockable\|HLEPrefixOk, { Imm8S, Reg16\|Reg32\|Reg64\|Word\|Dword\|Qword\|Unspecified\|BaseIndex\|Disp8\|Disp16\|Di sp32\|Disp32S }

209 or, 2, 0xc, None, 1, 0, W\|CheckRegSize\|No_sSuf\|No_ldSuf, { Imm8\|Imm16\|Imm32\|Imm3 2S, Acc\|Byte\|Word\|Dword\|Qword }	209 or, 2, 0xc, None, 1, 0, W\|CheckRegSize\|No_sSuf\|No_ldSuf, { Imm8\|Imm16\|Imm32\|Imm3 2S, Acc\|Byte\|Word\|Dword\|Qword }

210 or, 2, 0x80, 0x1, 1, 0, W\|CheckRegSize\|Modrm\|No_sSuf\|No_ldSuf\|IsLockable, { Imm8 \|Imm16\|Imm32\|Imm32S, Reg8\|Reg16\|Reg32\|Reg64\|Byte\|Word\|Dword\|Qword\|Unspecified\|Ba seIndex\|Disp8\|Disp16\|Disp32\|Disp32S }	210 or, 2, 0x80, 0x1, 1, 0, W\|CheckRegSize\|Modrm\|No_sSuf\|No_ldSuf\|IsLockable\|HLEPref ixOk, { Imm8\|Imm16\|Imm32\|Imm32S, Reg8\|Reg16\|Reg32\|Reg64\|Byte\|Word\|Dword\|Qword\|Un specified\|BaseIndex\|Disp8\|Disp16\|Disp32\|Disp32S }

211	211

212 xor, 2, 0x30, None, 1, 0, D\|W\|CheckRegSize\|Modrm\|No_sSuf\|No_ldSuf\|IsLockable, { Reg8\|Reg16\|Reg32\|Reg64, Reg8\|Reg16\|Reg32\|Reg64\|Byte\|Word\|Dword\|Qword\|Unspecified \|BaseIndex\|Disp8\|Disp16\|Disp32\|Disp32S }	212 xor, 2, 0x30, None, 1, 0, D\|W\|CheckRegSize\|Modrm\|No_sSuf\|No_ldSuf\|IsLockable\|HLE PrefixOk, { Reg8\|Reg16\|Reg32\|Reg64, Reg8\|Reg16\|Reg32\|Reg64\|Byte\|Word\|Dword\|Qword \|Unspecified\|BaseIndex\|Disp8\|Disp16\|Disp32\|Disp32S }

213 xor, 2, 0x83, 0x6, 1, 0, Modrm\|No_bSuf\|No_sSuf\|No_ldSuf\|IsLockable, { Imm8S, Reg 16\|Reg32\|Reg64\|Word\|Dword\|Qword\|Unspecified\|BaseIndex\|Disp8\|Disp16\|Disp32\|Disp32 S }	213 xor, 2, 0x83, 0x6, 1, 0, Modrm\|No_bSuf\|No_sSuf\|No_ldSuf\|IsLockable\|HLEPrefixOk, { Imm8S, Reg16\|Reg32\|Reg64\|Word\|Dword\|Qword\|Unspecified\|BaseIndex\|Disp8\|Disp16\|D isp32\|Disp32S }

214 xor, 2, 0x34, None, 1, 0, W\|CheckRegSize\|No_sSuf\|No_ldSuf, { Imm8\|Imm16\|Imm32\|Im m32S, Acc\|Byte\|Word\|Dword\|Qword }	214 xor, 2, 0x34, None, 1, 0, W\|CheckRegSize\|No_sSuf\|No_ldSuf, { Imm8\|Imm16\|Imm32\|Im m32S, Acc\|Byte\|Word\|Dword\|Qword }

215 xor, 2, 0x80, 0x6, 1, 0, W\|CheckRegSize\|Modrm\|No_sSuf\|No_ldSuf\|IsLockable, { Imm 8\|Imm16\|Imm32\|Imm32S, Reg8\|Reg16\|Reg32\|Reg64\|Byte\|Word\|Dword\|Qword\|Unspecified\|B aseIndex\|Disp8\|Disp16\|Disp32\|Disp32S }	215 xor, 2, 0x80, 0x6, 1, 0, W\|CheckRegSize\|Modrm\|No_sSuf\|No_ldSuf\|IsLockable\|HLEPre fixOk, { Imm8\|Imm16\|Imm32\|Imm32S, Reg8\|Reg16\|Reg32\|Reg64\|Byte\|Word\|Dword\|Qword\|U nspecified\|BaseIndex\|Disp8\|Disp16\|Disp32\|Disp32S }

216	216

217 // clr with 1 operand is really xor with 2 operands.	217 // clr with 1 operand is really xor with 2 operands.

218 clr, 1, 0x30, None, 1, 0, W\|Modrm\|No_sSuf\|No_ldSuf\|RegKludge, { Reg8\|Reg16\|Reg32 \|Reg64 }	218 clr, 1, 0x30, None, 1, 0, W\|Modrm\|No_sSuf\|No_ldSuf\|RegKludge, { Reg8\|Reg16\|Reg32 \|Reg64 }

219	219

220 adc, 2, 0x10, None, 1, 0, D\|W\|CheckRegSize\|Modrm\|No_sSuf\|No_ldSuf\|IsLockable, { Reg8\|Reg16\|Reg32\|Reg64, Reg8\|Reg16\|Reg32\|Reg64\|Byte\|Word\|Dword\|Qword\|Unspecified \|BaseIndex\|Disp8\|Disp16\|Disp32\|Disp32S }	220 adc, 2, 0x10, None, 1, 0, D\|W\|CheckRegSize\|Modrm\|No_sSuf\|No_ldSuf\|IsLockable\|HLE PrefixOk, { Reg8\|Reg16\|Reg32\|Reg64, Reg8\|Reg16\|Reg32\|Reg64\|Byte\|Word\|Dword\|Qword \|Unspecified\|BaseIndex\|Disp8\|Disp16\|Disp32\|Disp32S }

221 adc, 2, 0x83, 0x2, 1, 0, Modrm\|No_bSuf\|No_sSuf\|No_ldSuf\|IsLockable, { Imm8S, Reg 16\|Reg32\|Reg64\|Word\|Dword\|Qword\|Unspecified\|BaseIndex\|Disp8\|Disp16\|Disp32\|Disp32 S }	221 adc, 2, 0x83, 0x2, 1, 0, Modrm\|No_bSuf\|No_sSuf\|No_ldSuf\|IsLockable\|HLEPrefixOk, { Imm8S, Reg16\|Reg32\|Reg64\|Word\|Dword\|Qword\|Unspecified\|BaseIndex\|Disp8\|Disp16\|D isp32\|Disp32S }

222 adc, 2, 0x14, None, 1, 0, W\|CheckRegSize\|No_sSuf\|No_ldSuf, { Imm8\|Imm16\|Imm32\|Im m32S, Acc\|Byte\|Word\|Dword\|Qword }	222 adc, 2, 0x14, None, 1, 0, W\|CheckRegSize\|No_sSuf\|No_ldSuf, { Imm8\|Imm16\|Imm32\|Im m32S, Acc\|Byte\|Word\|Dword\|Qword }

223 adc, 2, 0x80, 0x2, 1, 0, W\|CheckRegSize\|Modrm\|No_sSuf\|No_ldSuf\|IsLockable, { Imm 8\|Imm16\|Imm32\|Imm32S, Reg8\|Reg16\|Reg32\|Reg64\|Byte\|Word\|Dword\|Qword\|Unspecified\|B aseIndex\|Disp8\|Disp16\|Disp32\|Disp32S }	223 adc, 2, 0x80, 0x2, 1, 0, W\|CheckRegSize\|Modrm\|No_sSuf\|No_ldSuf\|IsLockable\|HLEPre fixOk, { Imm8\|Imm16\|Imm32\|Imm32S, Reg8\|Reg16\|Reg32\|Reg64\|Byte\|Word\|Dword\|Qword\|U nspecified\|BaseIndex\|Disp8\|Disp16\|Disp32\|Disp32S }

224	224

225 neg, 1, 0xf6, 0x3, 1, 0, W\|Modrm\|No_sSuf\|No_ldSuf\|IsLockable, { Reg8\|Reg16\|Reg32 \|Reg64\|Byte\|Word\|Dword\|Qword\|Unspecified\|BaseIndex\|Disp8\|Disp16\|Disp32\|Disp32S }	225 neg, 1, 0xf6, 0x3, 1, 0, W\|Modrm\|No_sSuf\|No_ldSuf\|IsLockable\|HLEPrefixOk, { Reg8 \|Reg16\|Reg32\|Reg64\|Byte\|Word\|Dword\|Qword\|Unspecified\|BaseIndex\|Disp8\|Disp16\|Disp 32\|Disp32S }

226 not, 1, 0xf6, 0x2, 1, 0, W\|Modrm\|No_sSuf\|No_ldSuf\|IsLockable, { Reg8\|Reg16\|Reg32 \|Reg64\|Byte\|Word\|Dword\|Qword\|Unspecified\|BaseIndex\|Disp8\|Disp16\|Disp32\|Disp32S }	226 not, 1, 0xf6, 0x2, 1, 0, W\|Modrm\|No_sSuf\|No_ldSuf\|IsLockable\|HLEPrefixOk, { Reg8 \|Reg16\|Reg32\|Reg64\|Byte\|Word\|Dword\|Qword\|Unspecified\|BaseIndex\|Disp8\|Disp16\|Disp 32\|Disp32S }

227	227

228 aaa, 0, 0x37, None, 1, CpuNo64, No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf , { 0 }	228 aaa, 0, 0x37, None, 1, CpuNo64, No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf , { 0 }

229 aas, 0, 0x3f, None, 1, CpuNo64, No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf , { 0 }	229 aas, 0, 0x3f, None, 1, CpuNo64, No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf , { 0 }

230 daa, 0, 0x27, None, 1, CpuNo64, No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf , { 0 }	230 daa, 0, 0x27, None, 1, CpuNo64, No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf , { 0 }

231 das, 0, 0x2f, None, 1, CpuNo64, No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf , { 0 }	231 das, 0, 0x2f, None, 1, CpuNo64, No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf , { 0 }

232 aad, 0, 0xd50a, None, 2, CpuNo64, No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldS uf, { 0 }	232 aad, 0, 0xd50a, None, 2, CpuNo64, No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldS uf, { 0 }

233 aad, 1, 0xd5, None, 1, CpuNo64, No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf , { Imm8 }	233 aad, 1, 0xd5, None, 1, CpuNo64, No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf , { Imm8 }

234 aam, 0, 0xd40a, None, 2, CpuNo64, No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldS uf, { 0 }	234 aam, 0, 0xd40a, None, 2, CpuNo64, No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldS uf, { 0 }

235 aam, 1, 0xd4, None, 1, CpuNo64, No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf , { Imm8 }	235 aam, 1, 0xd4, None, 1, CpuNo64, No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf , { Imm8 }

236	236

(...skipping 96 matching lines...) Expand 10 before \| Expand all \| Expand 10 after Loading...
333 jmp, 1, 0xeb, None, 1, 0, Jump\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf, { Disp8\|Disp16\|Disp32\|Disp32S }	333 jmp, 1, 0xeb, None, 1, 0, Jump\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf, { Disp8\|Disp16\|Disp32\|Disp32S }

334 jmp, 1, 0xff, 0x4, 1, CpuNo64, Modrm\|No_bSuf\|No_sSuf\|No_qSuf\|No_ldSuf, { Reg16\|R eg32\|Word\|Dword\|Unspecified\|BaseIndex\|Disp8\|Disp16\|Disp32\|JumpAbsolute }	334 jmp, 1, 0xff, 0x4, 1, CpuNo64, Modrm\|No_bSuf\|No_sSuf\|No_qSuf\|No_ldSuf, { Reg16\|R eg32\|Word\|Dword\|Unspecified\|BaseIndex\|Disp8\|Disp16\|Disp32\|JumpAbsolute }

335 jmp, 1, 0xff, 0x4, 1, Cpu64, Modrm\|No_bSuf\|No_lSuf\|No_sSuf\|No_ldSuf\|NoRex64, { R eg16\|Reg64\|Word\|Qword\|Unspecified\|BaseIndex\|Disp8\|Disp32\|Disp32S\|JumpAbsolute }	335 jmp, 1, 0xff, 0x4, 1, Cpu64, Modrm\|No_bSuf\|No_lSuf\|No_sSuf\|No_ldSuf\|NoRex64, { R eg16\|Reg64\|Word\|Qword\|Unspecified\|BaseIndex\|Disp8\|Disp32\|Disp32S\|JumpAbsolute }

336 // Intel Syntax.	336 // Intel Syntax.

337 jmp, 2, 0xea, None, 1, CpuNo64, JumpInterSegment\|No_bSuf\|No_sSuf\|No_qSuf\|No_ldSu f, { Imm16, Imm16\|Imm32 }	337 jmp, 2, 0xea, None, 1, CpuNo64, JumpInterSegment\|No_bSuf\|No_sSuf\|No_qSuf\|No_ldSu f, { Imm16, Imm16\|Imm32 }

338 // Intel Syntax.	338 // Intel Syntax.

339 jmp, 1, 0xff, 0x5, 1, 0, Modrm\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf, { Dword\| Fword\|Unspecified\|BaseIndex\|Disp8\|Disp16\|Disp32\|Disp32S\|JumpAbsolute }	339 jmp, 1, 0xff, 0x5, 1, 0, Modrm\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf, { Dword\| Fword\|Unspecified\|BaseIndex\|Disp8\|Disp16\|Disp32\|Disp32S\|JumpAbsolute }

340 ljmp, 2, 0xea, None, 1, CpuNo64, JumpInterSegment\|No_bSuf\|No_sSuf\|No_qSuf\|No_ldS uf, { Imm16, Imm16\|Imm32 }	340 ljmp, 2, 0xea, None, 1, CpuNo64, JumpInterSegment\|No_bSuf\|No_sSuf\|No_qSuf\|No_ldS uf, { Imm16, Imm16\|Imm32 }

341 ljmp, 1, 0xff, 0x5, 1, 0, Modrm\|No_bSuf\|No_sSuf\|No_qSuf\|No_ldSuf, { Unspecified\| BaseIndex\|Disp8\|Disp16\|Disp32\|Disp32S\|JumpAbsolute }	341 ljmp, 1, 0xff, 0x5, 1, 0, Modrm\|No_bSuf\|No_sSuf\|No_qSuf\|No_ldSuf, { Unspecified\| BaseIndex\|Disp8\|Disp16\|Disp32\|Disp32S\|JumpAbsolute }

342	342

343 ret, 0, 0xc3, None, 1, CpuNo64, DefaultSize\|No_bSuf\|No_sSuf\|No_qSuf\|No_ldSuf, { 0 }	343 ret, 0, 0xc3, None, 1, CpuNo64, DefaultSize\|No_bSuf\|No_sSuf\|No_qSuf\|No_ldSuf\|Rep PrefixOk, { 0 }

344 ret, 1, 0xc2, None, 1, CpuNo64, DefaultSize\|No_bSuf\|No_sSuf\|No_qSuf\|No_ldSuf, { Imm16 }	344 ret, 1, 0xc2, None, 1, CpuNo64, DefaultSize\|No_bSuf\|No_sSuf\|No_qSuf\|No_ldSuf\|Rep PrefixOk, { Imm16 }

345 ret, 0, 0xc3, None, 1, Cpu64, DefaultSize\|No_bSuf\|No_lSuf\|No_sSuf\|No_ldSuf\|NoRex 64, { 0 }	345 ret, 0, 0xc3, None, 1, Cpu64, DefaultSize\|No_bSuf\|No_lSuf\|No_sSuf\|No_ldSuf\|NoRex 64\|RepPrefixOk, { 0 }

346 ret, 1, 0xc2, None, 1, Cpu64, DefaultSize\|No_bSuf\|No_lSuf\|No_sSuf\|No_ldSuf\|NoRex 64, { Imm16 }	346 ret, 1, 0xc2, None, 1, Cpu64, DefaultSize\|No_bSuf\|No_lSuf\|No_sSuf\|No_ldSuf\|NoRex 64\|RepPrefixOk, { Imm16 }

347 lret, 0, 0xcb, None, 1, 0, DefaultSize\|No_bSuf\|No_sSuf\|No_ldSuf, { 0 }	347 lret, 0, 0xcb, None, 1, 0, DefaultSize\|No_bSuf\|No_sSuf\|No_ldSuf, { 0 }

348 lret, 1, 0xca, None, 1, 0, DefaultSize\|No_bSuf\|No_sSuf\|No_ldSuf, { Imm16 }	348 lret, 1, 0xca, None, 1, 0, DefaultSize\|No_bSuf\|No_sSuf\|No_ldSuf, { Imm16 }

349 // Intel Syntax.	349 // Intel Syntax.

350 retf, 0, 0xcb, None, 1, 0, DefaultSize\|No_bSuf\|No_sSuf\|No_ldSuf, { 0 }	350 retf, 0, 0xcb, None, 1, 0, DefaultSize\|No_bSuf\|No_sSuf\|No_ldSuf, { 0 }

351 retf, 1, 0xca, None, 1, 0, DefaultSize\|No_bSuf\|No_sSuf\|No_ldSuf, { Imm16 }	351 retf, 1, 0xca, None, 1, 0, DefaultSize\|No_bSuf\|No_sSuf\|No_ldSuf, { Imm16 }

352	352

353 enter, 2, 0xc8, None, 1, Cpu186\|CpuNo64, DefaultSize\|No_bSuf\|No_sSuf\|No_qSuf\|No_ ldSuf, { Imm16, Imm8 }	353 enter, 2, 0xc8, None, 1, Cpu186\|CpuNo64, DefaultSize\|No_bSuf\|No_sSuf\|No_qSuf\|No_ ldSuf, { Imm16, Imm8 }

354 enter, 2, 0xc8, None, 1, Cpu64, DefaultSize\|No_bSuf\|No_lSuf\|No_sSuf\|No_ldSuf\|NoR ex64, { Imm16, Imm8 }	354 enter, 2, 0xc8, None, 1, Cpu64, DefaultSize\|No_bSuf\|No_lSuf\|No_sSuf\|No_ldSuf\|NoR ex64, { Imm16, Imm8 }

355 leave, 0, 0xc9, None, 1, Cpu186\|CpuNo64, DefaultSize\|No_bSuf\|No_sSuf\|No_qSuf\|No_ ldSuf, { 0 }	355 leave, 0, 0xc9, None, 1, Cpu186\|CpuNo64, DefaultSize\|No_bSuf\|No_sSuf\|No_qSuf\|No_ ldSuf, { 0 }

356 leave, 0, 0xc9, None, 1, Cpu64, DefaultSize\|No_bSuf\|No_lSuf\|No_sSuf\|No_ldSuf\|NoR ex64, { 0 }	356 leave, 0, 0xc9, None, 1, Cpu64, DefaultSize\|No_bSuf\|No_lSuf\|No_sSuf\|No_ldSuf\|NoR ex64, { 0 }

(...skipping 77 matching lines...) Expand 10 before \| Expand all \| Expand 10 after Loading...
434 setl, 1, 0xf9c, 0x0, 2, Cpu386, Modrm\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf, { Reg8\|Byte\|Unspecified\|BaseIndex\|Disp8\|Disp16\|Disp32\|Disp32S }	434 setl, 1, 0xf9c, 0x0, 2, Cpu386, Modrm\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf, { Reg8\|Byte\|Unspecified\|BaseIndex\|Disp8\|Disp16\|Disp32\|Disp32S }

435 setnge, 1, 0xf9c, 0x0, 2, Cpu386, Modrm\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf , { Reg8\|Byte\|Unspecified\|BaseIndex\|Disp8\|Disp16\|Disp32\|Disp32S }	435 setnge, 1, 0xf9c, 0x0, 2, Cpu386, Modrm\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf , { Reg8\|Byte\|Unspecified\|BaseIndex\|Disp8\|Disp16\|Disp32\|Disp32S }

436 setnl, 1, 0xf9d, 0x0, 2, Cpu386, Modrm\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf, { Reg8\|Byte\|Unspecified\|BaseIndex\|Disp8\|Disp16\|Disp32\|Disp32S }	436 setnl, 1, 0xf9d, 0x0, 2, Cpu386, Modrm\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf, { Reg8\|Byte\|Unspecified\|BaseIndex\|Disp8\|Disp16\|Disp32\|Disp32S }

437 setge, 1, 0xf9d, 0x0, 2, Cpu386, Modrm\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf, { Reg8\|Byte\|Unspecified\|BaseIndex\|Disp8\|Disp16\|Disp32\|Disp32S }	437 setge, 1, 0xf9d, 0x0, 2, Cpu386, Modrm\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf, { Reg8\|Byte\|Unspecified\|BaseIndex\|Disp8\|Disp16\|Disp32\|Disp32S }

438 setle, 1, 0xf9e, 0x0, 2, Cpu386, Modrm\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf, { Reg8\|Byte\|Unspecified\|BaseIndex\|Disp8\|Disp16\|Disp32\|Disp32S }	438 setle, 1, 0xf9e, 0x0, 2, Cpu386, Modrm\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf, { Reg8\|Byte\|Unspecified\|BaseIndex\|Disp8\|Disp16\|Disp32\|Disp32S }

439 setng, 1, 0xf9e, 0x0, 2, Cpu386, Modrm\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf, { Reg8\|Byte\|Unspecified\|BaseIndex\|Disp8\|Disp16\|Disp32\|Disp32S }	439 setng, 1, 0xf9e, 0x0, 2, Cpu386, Modrm\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf, { Reg8\|Byte\|Unspecified\|BaseIndex\|Disp8\|Disp16\|Disp32\|Disp32S }

440 setnle, 1, 0xf9f, 0x0, 2, Cpu386, Modrm\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf , { Reg8\|Byte\|Unspecified\|BaseIndex\|Disp8\|Disp16\|Disp32\|Disp32S }	440 setnle, 1, 0xf9f, 0x0, 2, Cpu386, Modrm\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf , { Reg8\|Byte\|Unspecified\|BaseIndex\|Disp8\|Disp16\|Disp32\|Disp32S }

441 setg, 1, 0xf9f, 0x0, 2, Cpu386, Modrm\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf, { Reg8\|Byte\|Unspecified\|BaseIndex\|Disp8\|Disp16\|Disp32\|Disp32S }	441 setg, 1, 0xf9f, 0x0, 2, Cpu386, Modrm\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf, { Reg8\|Byte\|Unspecified\|BaseIndex\|Disp8\|Disp16\|Disp32\|Disp32S }

442	442

443 // String manipulation.	443 // String manipulation.

444 cmps, 0, 0xa6, None, 1, 0, W\|No_sSuf\|No_ldSuf\|IsString, { 0 }	444 cmps, 0, 0xa6, None, 1, 0, W\|No_sSuf\|No_ldSuf\|IsString\|RepPrefixOk, { 0 }

445 cmps, 2, 0xa6, None, 1, 0, W\|CheckRegSize\|No_sSuf\|No_ldSuf\|IsString, { Byte\|Word \|Dword\|Qword\|Unspecified\|BaseIndex\|Disp8\|Disp16\|Disp32\|Disp32S\|EsSeg, Byte\|Word\| Dword\|Qword\|Unspecified\|BaseIndex\|Disp8\|Disp16\|Disp32\|Disp32S }	445 cmps, 2, 0xa6, None, 1, 0, W\|CheckRegSize\|No_sSuf\|No_ldSuf\|IsString\|RepPrefixOk, { Byte\|Word\|Dword\|Qword\|Unspecified\|BaseIndex\|Disp8\|Disp16\|Disp32\|Disp32S\|EsSeg , Byte\|Word\|Dword\|Qword\|Unspecified\|BaseIndex\|Disp8\|Disp16\|Disp32\|Disp32S }

446 scmp, 0, 0xa6, None, 1, 0, W\|No_sSuf\|No_ldSuf\|IsString, { 0 }	446 scmp, 0, 0xa6, None, 1, 0, W\|No_sSuf\|No_ldSuf\|IsString\|RepPrefixOk, { 0 }

447 scmp, 2, 0xa6, None, 1, 0, W\|CheckRegSize\|No_sSuf\|No_ldSuf\|IsString, { Byte\|Word \|Dword\|Qword\|Unspecified\|BaseIndex\|Disp8\|Disp16\|Disp32\|Disp32S\|EsSeg, Byte\|Word\| Dword\|Qword\|Unspecified\|BaseIndex\|Disp8\|Disp16\|Disp32\|Disp32S }	447 scmp, 2, 0xa6, None, 1, 0, W\|CheckRegSize\|No_sSuf\|No_ldSuf\|IsString\|RepPrefixOk, { Byte\|Word\|Dword\|Qword\|Unspecified\|BaseIndex\|Disp8\|Disp16\|Disp32\|Disp32S\|EsSeg , Byte\|Word\|Dword\|Qword\|Unspecified\|BaseIndex\|Disp8\|Disp16\|Disp32\|Disp32S }

448 ins, 0, 0x6c, None, 1, Cpu186, W\|No_sSuf\|No_qSuf\|No_ldSuf\|IsString, { 0 }	448 ins, 0, 0x6c, None, 1, Cpu186, W\|No_sSuf\|No_qSuf\|No_ldSuf\|IsString\|RepPrefixOk, { 0 }

449 ins, 2, 0x6c, None, 1, Cpu186, W\|CheckRegSize\|No_sSuf\|No_qSuf\|No_ldSuf\|IsString, { InOutPortReg, Byte\|Word\|Dword\|Unspecified\|BaseIndex\|Disp8\|Disp16\|Disp32\|Disp3 2S\|EsSeg }	449 ins, 2, 0x6c, None, 1, Cpu186, W\|CheckRegSize\|No_sSuf\|No_qSuf\|No_ldSuf\|IsString\| RepPrefixOk, { InOutPortReg, Byte\|Word\|Dword\|Unspecified\|BaseIndex\|Disp8\|Disp16\| Disp32\|Disp32S\|EsSeg }

450 outs, 0, 0x6e, None, 1, Cpu186, W\|No_sSuf\|No_qSuf\|No_ldSuf\|IsString, { 0 }	450 outs, 0, 0x6e, None, 1, Cpu186, W\|No_sSuf\|No_qSuf\|No_ldSuf\|IsString\|RepPrefixOk, { 0 }

451 outs, 2, 0x6e, None, 1, Cpu186, W\|CheckRegSize\|No_sSuf\|No_qSuf\|No_ldSuf\|IsString , { Byte\|Word\|Dword\|Unspecified\|BaseIndex\|Disp8\|Disp16\|Disp32\|Disp32S, InOutPort Reg }	451 outs, 2, 0x6e, None, 1, Cpu186, W\|CheckRegSize\|No_sSuf\|No_qSuf\|No_ldSuf\|IsString \|RepPrefixOk, { Byte\|Word\|Dword\|Unspecified\|BaseIndex\|Disp8\|Disp16\|Disp32\|Disp32 S, InOutPortReg }

452 lods, 0, 0xac, None, 1, 0, W\|No_sSuf\|No_ldSuf\|IsString, { 0 }	452 lods, 0, 0xac, None, 1, 0, W\|No_sSuf\|No_ldSuf\|IsString\|RepPrefixOk, { 0 }

453 lods, 1, 0xac, None, 1, 0, W\|No_sSuf\|No_ldSuf\|IsString, { Byte\|Word\|Dword\|Qword\| Unspecified\|BaseIndex\|Disp8\|Disp16\|Disp32\|Disp32S }	453 lods, 1, 0xac, None, 1, 0, W\|No_sSuf\|No_ldSuf\|IsString\|RepPrefixOk, { Byte\|Word\| Dword\|Qword\|Unspecified\|BaseIndex\|Disp8\|Disp16\|Disp32\|Disp32S }

454 lods, 2, 0xac, None, 1, 0, W\|CheckRegSize\|No_sSuf\|No_ldSuf\|IsString, { Byte\|Word \|Dword\|Qword\|Unspecified\|BaseIndex\|Disp8\|Disp16\|Disp32\|Disp32S, Acc\|Byte\|Word\|Dw ord\|Qword }	454 lods, 2, 0xac, None, 1, 0, W\|CheckRegSize\|No_sSuf\|No_ldSuf\|IsString\|RepPrefixOk, { Byte\|Word\|Dword\|Qword\|Unspecified\|BaseIndex\|Disp8\|Disp16\|Disp32\|Disp32S, Acc\| Byte\|Word\|Dword\|Qword }

455 slod, 0, 0xac, None, 1, 0, W\|No_sSuf\|No_ldSuf\|IsString, { 0 }	455 slod, 0, 0xac, None, 1, 0, W\|No_sSuf\|No_ldSuf\|IsString\|RepPrefixOk, { 0 }

456 slod, 1, 0xac, None, 1, 0, W\|No_sSuf\|No_ldSuf\|IsString, { Byte\|Word\|Dword\|Qword\| Unspecified\|BaseIndex\|Disp8\|Disp16\|Disp32\|Disp32S }	456 slod, 1, 0xac, None, 1, 0, W\|No_sSuf\|No_ldSuf\|IsString\|RepPrefixOk, { Byte\|Word\| Dword\|Qword\|Unspecified\|BaseIndex\|Disp8\|Disp16\|Disp32\|Disp32S }

457 slod, 2, 0xac, None, 1, 0, W\|CheckRegSize\|No_sSuf\|No_ldSuf\|IsString, { Byte\|Word \|Dword\|Qword\|Unspecified\|BaseIndex\|Disp8\|Disp16\|Disp32\|Disp32S, Acc\|Byte\|Word\|Dw ord\|Qword }	457 slod, 2, 0xac, None, 1, 0, W\|CheckRegSize\|No_sSuf\|No_ldSuf\|IsString\|RepPrefixOk, { Byte\|Word\|Dword\|Qword\|Unspecified\|BaseIndex\|Disp8\|Disp16\|Disp32\|Disp32S, Acc\| Byte\|Word\|Dword\|Qword }

458 movs, 0, 0xa4, None, 1, 0, W\|No_sSuf\|No_ldSuf\|IsString, { 0 }	458 movs, 0, 0xa4, None, 1, 0, W\|No_sSuf\|No_ldSuf\|IsString\|RepPrefixOk, { 0 }

459 movs, 2, 0xa4, None, 1, 0, W\|CheckRegSize\|No_sSuf\|No_ldSuf\|IsString, { Byte\|Word \|Dword\|Qword\|Unspecified\|BaseIndex\|Disp8\|Disp16\|Disp32\|Disp32S, Byte\|Word\|Dword\| Qword\|Unspecified\|BaseIndex\|Disp8\|Disp16\|Disp32\|Disp32S\|EsSeg }	459 movs, 2, 0xa4, None, 1, 0, W\|CheckRegSize\|No_sSuf\|No_ldSuf\|IsString\|RepPrefixOk, { Byte\|Word\|Dword\|Qword\|Unspecified\|BaseIndex\|Disp8\|Disp16\|Disp32\|Disp32S, Byte \|Word\|Dword\|Qword\|Unspecified\|BaseIndex\|Disp8\|Disp16\|Disp32\|Disp32S\|EsSeg }

460 smov, 0, 0xa4, None, 1, 0, W\|No_sSuf\|No_ldSuf\|IsString, { 0 }	460 smov, 0, 0xa4, None, 1, 0, W\|No_sSuf\|No_ldSuf\|IsString\|RepPrefixOk, { 0 }

461 smov, 2, 0xa4, None, 1, 0, W\|CheckRegSize\|No_sSuf\|No_ldSuf\|IsString, { Byte\|Word \|Dword\|Qword\|Unspecified\|BaseIndex\|Disp8\|Disp16\|Disp32\|Disp32S, Byte\|Word\|Dword\| Qword\|Unspecified\|BaseIndex\|Disp8\|Disp16\|Disp32\|Disp32S\|EsSeg }	461 smov, 2, 0xa4, None, 1, 0, W\|CheckRegSize\|No_sSuf\|No_ldSuf\|IsString\|RepPrefixOk, { Byte\|Word\|Dword\|Qword\|Unspecified\|BaseIndex\|Disp8\|Disp16\|Disp32\|Disp32S, Byte \|Word\|Dword\|Qword\|Unspecified\|BaseIndex\|Disp8\|Disp16\|Disp32\|Disp32S\|EsSeg }

462 scas, 0, 0xae, None, 1, 0, W\|No_sSuf\|No_ldSuf\|IsString, { 0 }	462 scas, 0, 0xae, None, 1, 0, W\|No_sSuf\|No_ldSuf\|IsString\|RepPrefixOk, { 0 }

463 scas, 1, 0xae, None, 1, 0, W\|No_sSuf\|No_ldSuf\|IsString, { Byte\|Word\|Dword\|Qword\| Unspecified\|BaseIndex\|Disp8\|Disp16\|Disp32\|Disp32S\|EsSeg }	463 scas, 1, 0xae, None, 1, 0, W\|No_sSuf\|No_ldSuf\|IsString\|RepPrefixOk, { Byte\|Word\| Dword\|Qword\|Unspecified\|BaseIndex\|Disp8\|Disp16\|Disp32\|Disp32S\|EsSeg }

464 scas, 2, 0xae, None, 1, 0, W\|CheckRegSize\|No_sSuf\|No_ldSuf\|IsString, { Byte\|Word \|Dword\|Qword\|Unspecified\|BaseIndex\|Disp8\|Disp16\|Disp32\|Disp32S\|EsSeg, Acc\|Byte\|W ord\|Dword\|Qword }	464 scas, 2, 0xae, None, 1, 0, W\|CheckRegSize\|No_sSuf\|No_ldSuf\|IsString\|RepPrefixOk, { Byte\|Word\|Dword\|Qword\|Unspecified\|BaseIndex\|Disp8\|Disp16\|Disp32\|Disp32S\|EsSeg , Acc\|Byte\|Word\|Dword\|Qword }

465 ssca, 0, 0xae, None, 1, 0, W\|No_sSuf\|No_ldSuf\|IsString, { 0 }	465 ssca, 0, 0xae, None, 1, 0, W\|No_sSuf\|No_ldSuf\|IsString\|RepPrefixOk, { 0 }

466 ssca, 1, 0xae, None, 1, 0, W\|No_sSuf\|No_ldSuf\|IsString, { Byte\|Word\|Dword\|Qword\| Unspecified\|BaseIndex\|Disp8\|Disp16\|Disp32\|Disp32S\|EsSeg }	466 ssca, 1, 0xae, None, 1, 0, W\|No_sSuf\|No_ldSuf\|IsString\|RepPrefixOk, { Byte\|Word\| Dword\|Qword\|Unspecified\|BaseIndex\|Disp8\|Disp16\|Disp32\|Disp32S\|EsSeg }

467 ssca, 2, 0xae, None, 1, 0, W\|CheckRegSize\|No_sSuf\|No_ldSuf\|IsString, { Byte\|Word \|Dword\|Qword\|Unspecified\|BaseIndex\|Disp8\|Disp16\|Disp32\|Disp32S\|EsSeg, Acc\|Byte\|W ord\|Dword\|Qword }	467 ssca, 2, 0xae, None, 1, 0, W\|CheckRegSize\|No_sSuf\|No_ldSuf\|IsString\|RepPrefixOk, { Byte\|Word\|Dword\|Qword\|Unspecified\|BaseIndex\|Disp8\|Disp16\|Disp32\|Disp32S\|EsSeg , Acc\|Byte\|Word\|Dword\|Qword }

468 stos, 0, 0xaa, None, 1, 0, W\|No_sSuf\|No_ldSuf\|IsString, { 0 }	468 stos, 0, 0xaa, None, 1, 0, W\|No_sSuf\|No_ldSuf\|IsString\|RepPrefixOk, { 0 }

469 stos, 1, 0xaa, None, 1, 0, W\|No_sSuf\|No_ldSuf\|IsString, { Byte\|Word\|Dword\|Qword\| Unspecified\|BaseIndex\|Disp8\|Disp16\|Disp32\|Disp32S\|EsSeg }	469 stos, 1, 0xaa, None, 1, 0, W\|No_sSuf\|No_ldSuf\|IsString\|RepPrefixOk, { Byte\|Word\| Dword\|Qword\|Unspecified\|BaseIndex\|Disp8\|Disp16\|Disp32\|Disp32S\|EsSeg }

470 stos, 2, 0xaa, None, 1, 0, W\|CheckRegSize\|No_sSuf\|No_ldSuf\|IsString, { Acc\|Byte\| Word\|Dword\|Qword, Byte\|Word\|Dword\|Qword\|Unspecified\|BaseIndex\|Disp8\|Disp16\|Disp3 2\|Disp32S\|EsSeg }	470 stos, 2, 0xaa, None, 1, 0, W\|CheckRegSize\|No_sSuf\|No_ldSuf\|IsString\|RepPrefixOk, { Acc\|Byte\|Word\|Dword\|Qword, Byte\|Word\|Dword\|Qword\|Unspecified\|BaseIndex\|Disp8\| Disp16\|Disp32\|Disp32S\|EsSeg }

471 ssto, 0, 0xaa, None, 1, 0, W\|No_sSuf\|No_ldSuf\|IsString, { 0 }	471 ssto, 0, 0xaa, None, 1, 0, W\|No_sSuf\|No_ldSuf\|IsString\|RepPrefixOk, { 0 }

472 ssto, 1, 0xaa, None, 1, 0, W\|No_sSuf\|No_ldSuf\|IsString, { Byte\|Word\|Dword\|Qword\| Unspecified\|BaseIndex\|Disp8\|Disp16\|Disp32\|Disp32S\|EsSeg }	472 ssto, 1, 0xaa, None, 1, 0, W\|No_sSuf\|No_ldSuf\|IsString\|RepPrefixOk, { Byte\|Word\| Dword\|Qword\|Unspecified\|BaseIndex\|Disp8\|Disp16\|Disp32\|Disp32S\|EsSeg }

473 ssto, 2, 0xaa, None, 1, 0, W\|CheckRegSize\|No_sSuf\|No_ldSuf\|IsString, { Acc\|Byte\| Word\|Dword\|Qword, Byte\|Word\|Dword\|Qword\|Unspecified\|BaseIndex\|Disp8\|Disp16\|Disp3 2\|Disp32S\|EsSeg }	473 ssto, 2, 0xaa, None, 1, 0, W\|CheckRegSize\|No_sSuf\|No_ldSuf\|IsString\|RepPrefixOk, { Acc\|Byte\|Word\|Dword\|Qword, Byte\|Word\|Dword\|Qword\|Unspecified\|BaseIndex\|Disp8\| Disp16\|Disp32\|Disp32S\|EsSeg }

474 xlat, 0, 0xd7, None, 1, 0, No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf\|IsString, { 0 }	474 xlat, 0, 0xd7, None, 1, 0, No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf\|IsString\|Rep PrefixOk, { 0 }

475 xlat, 1, 0xd7, None, 1, 0, No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf\|IsString, { Byte\|Unspecified\|BaseIndex\|Disp8\|Disp16\|Disp32\|Disp32S }	475 xlat, 1, 0xd7, None, 1, 0, No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf\|IsString\|Rep PrefixOk, { Byte\|Unspecified\|BaseIndex\|Disp8\|Disp16\|Disp32\|Disp32S }

476	476

477 // Bit manipulation.	477 // Bit manipulation.

478 bsf, 2, 0xfbc, None, 2, Cpu386, Modrm\|CheckRegSize\|No_bSuf\|No_sSuf\|No_ldSuf, { R eg16\|Reg32\|Reg64\|Word\|Dword\|Qword\|Unspecified\|BaseIndex\|Disp8\|Disp16\|Disp32\|Disp 32S, Reg16\|Reg32\|Reg64 }	478 bsf, 2, 0xfbc, None, 2, Cpu386, Modrm\|CheckRegSize\|No_bSuf\|No_sSuf\|No_ldSuf\|RepP refixOk, { Reg16\|Reg32\|Reg64\|Word\|Dword\|Qword\|Unspecified\|BaseIndex\|Disp8\|Disp16 \|Disp32\|Disp32S, Reg16\|Reg32\|Reg64 }

479 bsr, 2, 0xfbd, None, 2, Cpu386, Modrm\|CheckRegSize\|No_bSuf\|No_sSuf\|No_ldSuf, { R eg16\|Reg32\|Reg64\|Word\|Dword\|Qword\|Unspecified\|BaseIndex\|Disp8\|Disp16\|Disp32\|Disp 32S, Reg16\|Reg32\|Reg64 }	479 bsr, 2, 0xfbd, None, 2, Cpu386, Modrm\|CheckRegSize\|No_bSuf\|No_sSuf\|No_ldSuf\|RepP refixOk, { Reg16\|Reg32\|Reg64\|Word\|Dword\|Qword\|Unspecified\|BaseIndex\|Disp8\|Disp16 \|Disp32\|Disp32S, Reg16\|Reg32\|Reg64 }

480 bt, 2, 0xfa3, None, 2, Cpu386, Modrm\|CheckRegSize\|No_bSuf\|No_sSuf\|No_ldSuf, { Re g16\|Reg32\|Reg64, Reg16\|Reg32\|Reg64\|Word\|Dword\|Qword\|Unspecified\|BaseIndex\|Disp8\| Disp16\|Disp32\|Disp32S }	480 bt, 2, 0xfa3, None, 2, Cpu386, Modrm\|CheckRegSize\|No_bSuf\|No_sSuf\|No_ldSuf, { Re g16\|Reg32\|Reg64, Reg16\|Reg32\|Reg64\|Word\|Dword\|Qword\|Unspecified\|BaseIndex\|Disp8\| Disp16\|Disp32\|Disp32S }

481 bt, 2, 0xfba, 0x4, 2, Cpu386, Modrm\|No_bSuf\|No_sSuf\|No_ldSuf, { Imm8, Reg16\|Reg3 2\|Reg64\|Word\|Dword\|Qword\|Unspecified\|BaseIndex\|Disp8\|Disp16\|Disp32\|Disp32S }	481 bt, 2, 0xfba, 0x4, 2, Cpu386, Modrm\|No_bSuf\|No_sSuf\|No_ldSuf, { Imm8, Reg16\|Reg3 2\|Reg64\|Word\|Dword\|Qword\|Unspecified\|BaseIndex\|Disp8\|Disp16\|Disp32\|Disp32S }

482 btc, 2, 0xfbb, None, 2, Cpu386, Modrm\|CheckRegSize\|No_bSuf\|No_sSuf\|No_ldSuf\|IsLo ckable, { Reg16\|Reg32\|Reg64, Reg16\|Reg32\|Reg64\|Word\|Dword\|Qword\|Unspecified\|Base Index\|Disp8\|Disp16\|Disp32\|Disp32S }	482 btc, 2, 0xfbb, None, 2, Cpu386, Modrm\|CheckRegSize\|No_bSuf\|No_sSuf\|No_ldSuf\|IsLo ckable\|HLEPrefixOk, { Reg16\|Reg32\|Reg64, Reg16\|Reg32\|Reg64\|Word\|Dword\|Qword\|Unsp ecified\|BaseIndex\|Disp8\|Disp16\|Disp32\|Disp32S }

483 btc, 2, 0xfba, 0x7, 2, Cpu386, Modrm\|No_bSuf\|No_sSuf\|No_ldSuf\|IsLockable, { Imm8 , Reg16\|Reg32\|Reg64\|Word\|Dword\|Qword\|Unspecified\|BaseIndex\|Disp8\|Disp16\|Disp32\|D isp32S }	483 btc, 2, 0xfba, 0x7, 2, Cpu386, Modrm\|No_bSuf\|No_sSuf\|No_ldSuf\|IsLockable\|HLEPref ixOk, { Imm8, Reg16\|Reg32\|Reg64\|Word\|Dword\|Qword\|Unspecified\|BaseIndex\|Disp8\|Dis p16\|Disp32\|Disp32S }

484 btr, 2, 0xfb3, None, 2, Cpu386, Modrm\|CheckRegSize\|No_bSuf\|No_sSuf\|No_ldSuf\|IsLo ckable, { Reg16\|Reg32\|Reg64, Reg16\|Reg32\|Reg64\|Word\|Dword\|Qword\|Unspecified\|Base Index\|Disp8\|Disp16\|Disp32\|Disp32S }	484 btr, 2, 0xfb3, None, 2, Cpu386, Modrm\|CheckRegSize\|No_bSuf\|No_sSuf\|No_ldSuf\|IsLo ckable\|HLEPrefixOk, { Reg16\|Reg32\|Reg64, Reg16\|Reg32\|Reg64\|Word\|Dword\|Qword\|Unsp ecified\|BaseIndex\|Disp8\|Disp16\|Disp32\|Disp32S }

485 btr, 2, 0xfba, 0x6, 2, Cpu386, Modrm\|No_bSuf\|No_sSuf\|No_ldSuf\|IsLockable, { Imm8 , Reg16\|Reg32\|Reg64\|Word\|Dword\|Qword\|Unspecified\|BaseIndex\|Disp8\|Disp16\|Disp32\|D isp32S }	485 btr, 2, 0xfba, 0x6, 2, Cpu386, Modrm\|No_bSuf\|No_sSuf\|No_ldSuf\|IsLockable\|HLEPref ixOk, { Imm8, Reg16\|Reg32\|Reg64\|Word\|Dword\|Qword\|Unspecified\|BaseIndex\|Disp8\|Dis p16\|Disp32\|Disp32S }

486 bts, 2, 0xfab, None, 2, Cpu386, Modrm\|CheckRegSize\|No_bSuf\|No_sSuf\|No_ldSuf\|IsLo ckable, { Reg16\|Reg32\|Reg64, Reg16\|Reg32\|Reg64\|Word\|Dword\|Qword\|Unspecified\|Base Index\|Disp8\|Disp16\|Disp32\|Disp32S }	486 bts, 2, 0xfab, None, 2, Cpu386, Modrm\|CheckRegSize\|No_bSuf\|No_sSuf\|No_ldSuf\|IsLo ckable\|HLEPrefixOk, { Reg16\|Reg32\|Reg64, Reg16\|Reg32\|Reg64\|Word\|Dword\|Qword\|Unsp ecified\|BaseIndex\|Disp8\|Disp16\|Disp32\|Disp32S }

487 bts, 2, 0xfba, 0x5, 2, Cpu386, Modrm\|No_bSuf\|No_sSuf\|No_ldSuf\|IsLockable, { Imm8 , Reg16\|Reg32\|Reg64\|Word\|Dword\|Qword\|Unspecified\|BaseIndex\|Disp8\|Disp16\|Disp32\|D isp32S }	487 bts, 2, 0xfba, 0x5, 2, Cpu386, Modrm\|No_bSuf\|No_sSuf\|No_ldSuf\|IsLockable\|HLEPref ixOk, { Imm8, Reg16\|Reg32\|Reg64\|Word\|Dword\|Qword\|Unspecified\|BaseIndex\|Disp8\|Dis p16\|Disp32\|Disp32S }

488	488

489 // Interrupts & op. sys insns.	489 // Interrupts & op. sys insns.

490 // See gas/config/tc-i386.c for conversion of 'int $3' into the special	490 // See gas/config/tc-i386.c for conversion of 'int $3' into the special

491 // int 3 insn.	491 // int 3 insn.

492 int, 1, 0xcd, None, 1, 0, No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf, { Im m8 }	492 int, 1, 0xcd, None, 1, 0, No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf, { Im m8 }

493 int3, 0, 0xcc, None, 1, 0, No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf, { 0 }	493 int3, 0, 0xcc, None, 1, 0, No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf, { 0 }

494 into, 0, 0xce, None, 1, CpuNo64, No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSu f, { 0 }	494 into, 0, 0xce, None, 1, CpuNo64, No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSu f, { 0 }

495 iret, 0, 0xcf, None, 1, 0, DefaultSize\|No_bSuf\|No_sSuf\|No_ldSuf, { 0 }	495 iret, 0, 0xcf, None, 1, 0, DefaultSize\|No_bSuf\|No_sSuf\|No_ldSuf, { 0 }

496 // i386sl, i486sl, later 486, and Pentium.	496 // i386sl, i486sl, later 486, and Pentium.

497 rsm, 0, 0xfaa, None, 2, Cpu386, No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf , { 0 }	497 rsm, 0, 0xfaa, None, 2, Cpu386, No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf , { 0 }

498	498

499 bound, 2, 0x62, None, 1, Cpu186\|CpuNo64, Modrm\|No_bSuf\|No_sSuf\|No_qSuf\|No_ldSuf, { Reg16\|Reg32, Dword\|Qword\|Unspecified\|BaseIndex\|Disp8\|Disp16\|Disp32 }	499 bound, 2, 0x62, None, 1, Cpu186\|CpuNo64, Modrm\|No_bSuf\|No_sSuf\|No_qSuf\|No_ldSuf, { Reg16\|Reg32, Dword\|Qword\|Unspecified\|BaseIndex\|Disp8\|Disp16\|Disp32 }

500	500

501 hlt, 0, 0xf4, None, 1, 0, No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf, { 0 }	501 hlt, 0, 0xf4, None, 1, 0, No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf, { 0 }

502	502

503 nop, 1, 0xf1f, 0x0, 2, CpuNop, Modrm\|No_bSuf\|No_sSuf\|No_ldSuf, { Reg16\|Reg32\|Reg 64\|Word\|Dword\|Qword\|Unspecified\|BaseIndex\|Disp8\|Disp16\|Disp32\|Disp32S }	503 nop, 1, 0xf1f, 0x0, 2, CpuNop, Modrm\|No_bSuf\|No_sSuf\|No_ldSuf, { Reg16\|Reg32\|Reg 64\|Word\|Dword\|Qword\|Unspecified\|BaseIndex\|Disp8\|Disp16\|Disp32\|Disp32S }

504	504

505 // nop is actually "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in	505 // nop is actually "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in

506 // 32bit mode and "xchg %rax,%rax" in 64bit mode.	506 // 32bit mode and "xchg %rax,%rax" in 64bit mode.

507 nop, 0, 0x90, None, 1, 0, No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf, { 0 }	507 nop, 0, 0x90, None, 1, 0, No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf\|RepPr efixOk, { 0 }

508	508

509 // Protection control.	509 // Protection control.

510 arpl, 2, 0x63, None, 1, Cpu286\|CpuNo64, Modrm\|IgnoreSize\|No_bSuf\|No_lSuf\|No_sSuf \|No_qSuf\|No_ldSuf, { Reg16, Reg16\|Word\|Unspecified\|BaseIndex\|Disp8\|Disp16\|Disp32 }	510 arpl, 2, 0x63, None, 1, Cpu286\|CpuNo64, Modrm\|IgnoreSize\|No_bSuf\|No_lSuf\|No_sSuf \|No_qSuf\|No_ldSuf, { Reg16, Reg16\|Word\|Unspecified\|BaseIndex\|Disp8\|Disp16\|Disp32 }

511 lar, 2, 0xf02, None, 2, Cpu286, Modrm\|No_bSuf\|No_sSuf\|No_ldSuf, { Reg16\|Reg32\|Re g64\|Word\|Dword\|Qword\|Unspecified\|BaseIndex\|Disp8\|Disp16\|Disp32\|Disp32S, Reg16\|Re g32\|Reg64 }	511 lar, 2, 0xf02, None, 2, Cpu286, Modrm\|No_bSuf\|No_sSuf\|No_ldSuf, { Reg16\|Reg32\|Re g64\|Word\|Dword\|Qword\|Unspecified\|BaseIndex\|Disp8\|Disp16\|Disp32\|Disp32S, Reg16\|Re g32\|Reg64 }

512 lgdt, 1, 0xf01, 0x2, 2, Cpu286\|CpuNo64, Modrm\|No_bSuf\|No_sSuf\|No_qSuf\|No_ldSuf, { Tbyte\|Fword\|Unspecified\|BaseIndex\|Disp8\|Disp16\|Disp32 }	512 lgdt, 1, 0xf01, 0x2, 2, Cpu286\|CpuNo64, Modrm\|No_bSuf\|No_sSuf\|No_qSuf\|No_ldSuf, { Tbyte\|Fword\|Unspecified\|BaseIndex\|Disp8\|Disp16\|Disp32 }

513 lgdt, 1, 0xf01, 0x2, 2, Cpu64, Modrm\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_ldSuf\|No Rex64, { Tbyte\|Unspecified\|BaseIndex\|Disp8\|Disp32\|Disp32S }	513 lgdt, 1, 0xf01, 0x2, 2, Cpu64, Modrm\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_ldSuf\|No Rex64, { Tbyte\|Unspecified\|BaseIndex\|Disp8\|Disp32\|Disp32S }

514 lidt, 1, 0xf01, 0x3, 2, Cpu286\|CpuNo64, Modrm\|No_bSuf\|No_sSuf\|No_qSuf\|No_ldSuf, { Fword\|Unspecified\|BaseIndex\|Disp8\|Disp16\|Disp32 }	514 lidt, 1, 0xf01, 0x3, 2, Cpu286\|CpuNo64, Modrm\|No_bSuf\|No_sSuf\|No_qSuf\|No_ldSuf, { Fword\|Unspecified\|BaseIndex\|Disp8\|Disp16\|Disp32 }

515 lidt, 1, 0xf01, 0x3, 2, Cpu64, Modrm\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_ldSuf\|No Rex64, { Tbyte\|Unspecified\|BaseIndex\|Disp8\|Disp32\|Disp32S }	515 lidt, 1, 0xf01, 0x3, 2, Cpu64, Modrm\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_ldSuf\|No Rex64, { Tbyte\|Unspecified\|BaseIndex\|Disp8\|Disp32\|Disp32S }

516 lldt, 1, 0xf00, 0x2, 2, Cpu286, Modrm\|IgnoreSize\|No_bSuf\|No_lSuf\|No_sSuf\|No_qSuf \|No_ldSuf, { Reg16\|Word\|Unspecified\|BaseIndex\|Disp8\|Disp16\|Disp32\|Disp32S }	516 lldt, 1, 0xf00, 0x2, 2, Cpu286, Modrm\|IgnoreSize\|No_bSuf\|No_lSuf\|No_sSuf\|No_qSuf \|No_ldSuf, { Reg16\|Word\|Unspecified\|BaseIndex\|Disp8\|Disp16\|Disp32\|Disp32S }

517 lmsw, 1, 0xf01, 0x6, 2, Cpu286, Modrm\|IgnoreSize\|No_bSuf\|No_lSuf\|No_sSuf\|No_qSuf \|No_ldSuf, { Reg16\|Word\|Unspecified\|BaseIndex\|Disp8\|Disp16\|Disp32\|Disp32S }	517 lmsw, 1, 0xf01, 0x6, 2, Cpu286, Modrm\|IgnoreSize\|No_bSuf\|No_lSuf\|No_sSuf\|No_qSuf \|No_ldSuf, { Reg16\|Word\|Unspecified\|BaseIndex\|Disp8\|Disp16\|Disp32\|Disp32S }

(...skipping 304 matching lines...) Expand 10 before \| Expand all \| Expand 10 after Loading...
822 rex.wx, 0, 0x4a, None, 1, Cpu64, No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSu f\|IsPrefix, { 0 }	822 rex.wx, 0, 0x4a, None, 1, Cpu64, No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSu f\|IsPrefix, { 0 }

823 rex.wxb, 0, 0x4b, None, 1, Cpu64, No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldS uf\|IsPrefix, { 0 }	823 rex.wxb, 0, 0x4b, None, 1, Cpu64, No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldS uf\|IsPrefix, { 0 }

824 rex.wr, 0, 0x4c, None, 1, Cpu64, No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSu f\|IsPrefix, { 0 }	824 rex.wr, 0, 0x4c, None, 1, Cpu64, No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSu f\|IsPrefix, { 0 }

825 rex.wrb, 0, 0x4d, None, 1, Cpu64, No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldS uf\|IsPrefix, { 0 }	825 rex.wrb, 0, 0x4d, None, 1, Cpu64, No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldS uf\|IsPrefix, { 0 }

826 rex.wrx, 0, 0x4e, None, 1, Cpu64, No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldS uf\|IsPrefix, { 0 }	826 rex.wrx, 0, 0x4e, None, 1, Cpu64, No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldS uf\|IsPrefix, { 0 }

827 rex.wrxb, 0, 0x4f, None, 1, Cpu64, No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ld Suf\|IsPrefix, { 0 }	827 rex.wrxb, 0, 0x4f, None, 1, Cpu64, No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ld Suf\|IsPrefix, { 0 }

828	828

829 // 486 extensions.	829 // 486 extensions.

830	830

831 bswap, 1, 0xfc8, None, 2, Cpu486, ShortForm\|No_bSuf\|No_wSuf\|No_sSuf\|No_ldSuf, { Reg32\|Reg64 }	831 bswap, 1, 0xfc8, None, 2, Cpu486, ShortForm\|No_bSuf\|No_wSuf\|No_sSuf\|No_ldSuf, { Reg32\|Reg64 }

832 xadd, 2, 0xfc0, None, 2, Cpu486, W\|CheckRegSize\|Modrm\|No_sSuf\|No_ldSuf\|IsLockabl e, { Reg8\|Reg16\|Reg32\|Reg64, Reg8\|Reg16\|Reg32\|Reg64\|Byte\|Word\|Dword\|Qword\|Unspec ified\|BaseIndex\|Disp8\|Disp16\|Disp32\|Disp32S }	832 xadd, 2, 0xfc0, None, 2, Cpu486, W\|CheckRegSize\|Modrm\|No_sSuf\|No_ldSuf\|IsLockabl e\|HLEPrefixOk, { Reg8\|Reg16\|Reg32\|Reg64, Reg8\|Reg16\|Reg32\|Reg64\|Byte\|Word\|Dword\| Qword\|Unspecified\|BaseIndex\|Disp8\|Disp16\|Disp32\|Disp32S }

833 cmpxchg, 2, 0xfb0, None, 2, Cpu486, W\|CheckRegSize\|Modrm\|No_sSuf\|No_ldSuf\|IsLock able, { Reg8\|Reg16\|Reg32\|Reg64, Reg8\|Reg16\|Reg32\|Reg64\|Byte\|Word\|Dword\|Qword\|Uns pecified\|BaseIndex\|Disp8\|Disp16\|Disp32\|Disp32S }	833 cmpxchg, 2, 0xfb0, None, 2, Cpu486, W\|CheckRegSize\|Modrm\|No_sSuf\|No_ldSuf\|IsLock able\|HLEPrefixOk, { Reg8\|Reg16\|Reg32\|Reg64, Reg8\|Reg16\|Reg32\|Reg64\|Byte\|Word\|Dwo rd\|Qword\|Unspecified\|BaseIndex\|Disp8\|Disp16\|Disp32\|Disp32S }

834 invd, 0, 0xf08, None, 2, Cpu486, No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSu f, { 0 }	834 invd, 0, 0xf08, None, 2, Cpu486, No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSu f, { 0 }

835 wbinvd, 0, 0xf09, None, 2, Cpu486, No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ld Suf, { 0 }	835 wbinvd, 0, 0xf09, None, 2, Cpu486, No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ld Suf, { 0 }

836 invlpg, 1, 0xf01, 0x7, 2, Cpu486, Modrm\|IgnoreSize\|No_bSuf\|No_wSuf\|No_lSuf\|No_sS uf\|No_qSuf\|No_ldSuf, { Unspecified\|BaseIndex\|Disp8\|Disp16\|Disp32\|Disp32S }	836 invlpg, 1, 0xf01, 0x7, 2, Cpu486, Modrm\|IgnoreSize\|No_bSuf\|No_wSuf\|No_lSuf\|No_sS uf\|No_qSuf\|No_ldSuf, { Unspecified\|BaseIndex\|Disp8\|Disp16\|Disp32\|Disp32S }

837	837

838 // 586 and late 486 extensions.	838 // 586 and late 486 extensions.

839 cpuid, 0, 0xfa2, None, 2, Cpu486, No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldS uf, { 0 }	839 cpuid, 0, 0xfa2, None, 2, Cpu486, No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldS uf, { 0 }

840	840

841 // Pentium extensions.	841 // Pentium extensions.

842 wrmsr, 0, 0xf30, None, 2, Cpu586, No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldS uf, { 0 }	842 wrmsr, 0, 0xf30, None, 2, Cpu586, No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldS uf, { 0 }

843 rdtsc, 0, 0xf31, None, 2, Cpu586, No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldS uf, { 0 }	843 rdtsc, 0, 0xf31, None, 2, Cpu586, No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldS uf, { 0 }

844 rdmsr, 0, 0xf32, None, 2, Cpu586, No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldS uf, { 0 }	844 rdmsr, 0, 0xf32, None, 2, Cpu586, No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldS uf, { 0 }

845 cmpxchg8b, 1, 0xfc7, 0x1, 2, Cpu586, Modrm\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_ld Suf\|IsLockable, { Qword\|Unspecified\|BaseIndex\|Disp8\|Disp16\|Disp32\|Disp32S }	845 cmpxchg8b, 1, 0xfc7, 0x1, 2, Cpu586, Modrm\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_ld Suf\|IsLockable\|HLEPrefixOk, { Qword\|Unspecified\|BaseIndex\|Disp8\|Disp16\|Disp32\|Di sp32S }

846	846

847 // Pentium II/Pentium Pro extensions.	847 // Pentium II/Pentium Pro extensions.

848 sysenter, 0, 0xf34, None, 2, Cpu686, No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ ldSuf, { 0 }	848 sysenter, 0, 0xf34, None, 2, Cpu686, No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ ldSuf, { 0 }

849 sysexit, 0, 0xf35, None, 2, Cpu686, No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_l dSuf, { 0 }	849 sysexit, 0, 0xf35, None, 2, Cpu686, No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_l dSuf, { 0 }

850 fxsave, 1, 0xfae, 0x0, 2, Cpu686, Modrm\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_ldSuf , { Unspecified\|BaseIndex\|Disp8\|Disp16\|Disp32\|Disp32S }	850 fxsave, 1, 0xfae, 0x0, 2, Cpu686, Modrm\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_ldSuf , { Unspecified\|BaseIndex\|Disp8\|Disp16\|Disp32\|Disp32S }

851 fxsave64, 1, 0xfae, 0x0, 2, Cpu64, Modrm\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_ldSu f\|Rex64, { Unspecified\|BaseIndex\|Disp8\|Disp16\|Disp32\|Disp32S }	851 fxsave64, 1, 0xfae, 0x0, 2, Cpu64, Modrm\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_ldSu f\|Rex64, { Unspecified\|BaseIndex\|Disp8\|Disp16\|Disp32\|Disp32S }

852 fxrstor, 1, 0xfae, 0x1, 2, Cpu686, Modrm\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_ldSu f, { Unspecified\|BaseIndex\|Disp8\|Disp16\|Disp32\|Disp32S }	852 fxrstor, 1, 0xfae, 0x1, 2, Cpu686, Modrm\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_ldSu f, { Unspecified\|BaseIndex\|Disp8\|Disp16\|Disp32\|Disp32S }

853 fxrstor64, 1, 0xfae, 0x1, 2, Cpu64, Modrm\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_ldS uf\|Rex64, { Unspecified\|BaseIndex\|Disp8\|Disp16\|Disp32\|Disp32S }	853 fxrstor64, 1, 0xfae, 0x1, 2, Cpu64, Modrm\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_ldS uf\|Rex64, { Unspecified\|BaseIndex\|Disp8\|Disp16\|Disp32\|Disp32S }

854 rdpmc, 0, 0xf33, None, 2, Cpu686, No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldS uf, { 0 }	854 rdpmc, 0, 0xf33, None, 2, Cpu686, No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldS uf, { 0 }

855 // official undefined instr.	855 // official undefined instr.

(...skipping 93 matching lines...) Expand 10 before \| Expand all \| Expand 10 after Loading...
949 movd, 2, 0x660f7e, None, 2, CpuSSE2, Modrm\|IgnoreSize\|No_bSuf\|No_wSuf\|No_lSuf\|No _sSuf\|No_qSuf\|No_ldSuf, { RegXMM, Reg32\|Dword\|Unspecified\|BaseIndex\|Disp8\|Disp16 \|Disp32\|Disp32S\|Disp32S }	949 movd, 2, 0x660f7e, None, 2, CpuSSE2, Modrm\|IgnoreSize\|No_bSuf\|No_wSuf\|No_lSuf\|No _sSuf\|No_qSuf\|No_ldSuf, { RegXMM, Reg32\|Dword\|Unspecified\|BaseIndex\|Disp8\|Disp16 \|Disp32\|Disp32S\|Disp32S }

950 movd, 2, 0x660f7e, None, 2, CpuSSE2\|Cpu64, Modrm\|IgnoreSize\|No_bSuf\|No_wSuf\|No_l Suf\|No_sSuf\|No_qSuf\|No_ldSuf\|Rex64, { RegXMM, Reg64\|Qword\|BaseIndex\|Disp8\|Disp32 \|Disp32S\|Disp32S }	950 movd, 2, 0x660f7e, None, 2, CpuSSE2\|Cpu64, Modrm\|IgnoreSize\|No_bSuf\|No_wSuf\|No_l Suf\|No_sSuf\|No_qSuf\|No_ldSuf\|Rex64, { RegXMM, Reg64\|Qword\|BaseIndex\|Disp8\|Disp32 \|Disp32S\|Disp32S }

951 movd, 2, 0xf6e, None, 2, CpuMMX, Modrm\|IgnoreSize\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSu f\|No_qSuf\|No_ldSuf, { Reg32\|Dword\|Unspecified\|BaseIndex\|Disp8\|Disp16\|Disp32\|Disp 32S, RegMMX }	951 movd, 2, 0xf6e, None, 2, CpuMMX, Modrm\|IgnoreSize\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSu f\|No_qSuf\|No_ldSuf, { Reg32\|Dword\|Unspecified\|BaseIndex\|Disp8\|Disp16\|Disp32\|Disp 32S, RegMMX }

952 movd, 2, 0xf6e, None, 2, CpuMMX\|Cpu64, Modrm\|IgnoreSize\|No_bSuf\|No_wSuf\|No_lSuf\| No_sSuf\|No_qSuf\|No_ldSuf\|Rex64, { Reg64\|Qword\|BaseIndex\|Disp8\|Disp32\|Disp32S, Re gMMX }	952 movd, 2, 0xf6e, None, 2, CpuMMX\|Cpu64, Modrm\|IgnoreSize\|No_bSuf\|No_wSuf\|No_lSuf\| No_sSuf\|No_qSuf\|No_ldSuf\|Rex64, { Reg64\|Qword\|BaseIndex\|Disp8\|Disp32\|Disp32S, Re gMMX }

953 movd, 2, 0xf7e, None, 2, CpuMMX, Modrm\|IgnoreSize\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSu f\|No_qSuf\|No_ldSuf, { RegMMX, Reg32\|Dword\|Unspecified\|BaseIndex\|Disp8\|Disp16\|Dis p32\|Disp32S\|Disp32S }	953 movd, 2, 0xf7e, None, 2, CpuMMX, Modrm\|IgnoreSize\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSu f\|No_qSuf\|No_ldSuf, { RegMMX, Reg32\|Dword\|Unspecified\|BaseIndex\|Disp8\|Disp16\|Dis p32\|Disp32S\|Disp32S }

954 movd, 2, 0xf7e, None, 2, CpuMMX\|Cpu64, Modrm\|IgnoreSize\|No_bSuf\|No_wSuf\|No_lSuf\| No_sSuf\|No_qSuf\|No_ldSuf\|Rex64, { RegMMX, Reg64\|Qword\|BaseIndex\|Disp8\|Disp32\|Dis p32S\|Disp32S }	954 movd, 2, 0xf7e, None, 2, CpuMMX\|Cpu64, Modrm\|IgnoreSize\|No_bSuf\|No_wSuf\|No_lSuf\| No_sSuf\|No_qSuf\|No_ldSuf\|Rex64, { RegMMX, Reg64\|Qword\|BaseIndex\|Disp8\|Disp32\|Dis p32S\|Disp32S }

955 // In the 64bit mode the short form mov immediate is redefined to have	955 // In the 64bit mode the short form mov immediate is redefined to have

956 // 64bit displacement value. We put the 64bit displacement first and	956 // 64bit displacement value. We put the 64bit displacement first and

957 // we only mark constants larger than 32bit as Disp64.	957 // we only mark constants larger than 32bit as Disp64.

958 movq, 2, 0xa0, None, 1, Cpu64, D\|W\|CheckRegSize\|Size64\|No_bSuf\|No_wSuf\|No_lSuf\|N o_sSuf\|No_qSuf\|No_ldSuf, { Disp64\|Unspecified\|Qword, Acc\|Qword }	958 movq, 2, 0xa0, None, 1, Cpu64, D\|W\|CheckRegSize\|Size64\|No_bSuf\|No_wSuf\|No_lSuf\|N o_sSuf\|No_qSuf\|No_ldSuf, { Disp64\|Unspecified\|Qword, Acc\|Qword }

959 movq, 2, 0x88, None, 1, Cpu64, D\|W\|Modrm\|Size64\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\| No_qSuf\|No_ldSuf, { Reg64, Reg64\|Unspecified\|Qword\|BaseIndex\|Disp8\|Disp32\|Disp32 S }	959 movq, 2, 0x88, None, 1, Cpu64, D\|W\|Modrm\|Size64\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\| No_qSuf\|No_ldSuf\|HLEPrefixOk=3, { Reg64, Reg64\|Unspecified\|Qword\|BaseIndex\|Disp8 \|Disp32\|Disp32S }

960 movq, 2, 0xc6, 0x0, 1, Cpu64, W\|Modrm\|Size64\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_ qSuf\|No_ldSuf, { Imm32S, Reg64\|Qword\|Unspecified\|BaseIndex\|Disp8\|Disp32\|Disp32S }	960 movq, 2, 0xc6, 0x0, 1, Cpu64, W\|Modrm\|Size64\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_ qSuf\|No_ldSuf\|HLEPrefixOk=3, { Imm32S, Reg64\|Qword\|Unspecified\|BaseIndex\|Disp8\|D isp32\|Disp32S }

961 movq, 2, 0xb0, None, 1, Cpu64, W\|ShortForm\|Size64\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSu f\|No_qSuf\|No_ldSuf, { Imm64, Reg64 }	961 movq, 2, 0xb0, None, 1, Cpu64, W\|ShortForm\|Size64\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSu f\|No_qSuf\|No_ldSuf, { Imm64, Reg64 }

962 movq, 2, 0xf37e, None, 1, CpuAVX, S\|Modrm\|Vex=3\|VexOpcode=0\|VexW=1\|IgnoreSize\|No _bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf\|NoRex64\|SSE2AVX, { Qword\|Unspecif ied\|BaseIndex\|Disp8\|Disp16\|Disp32\|Disp32S\|RegXMM, RegXMM }	962 movq, 2, 0xf37e, None, 1, CpuAVX, S\|Modrm\|Vex=3\|VexOpcode=0\|VexW=1\|IgnoreSize\|No _bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf\|NoRex64\|SSE2AVX, { Qword\|Unspecif ied\|BaseIndex\|Disp8\|Disp16\|Disp32\|Disp32S\|RegXMM, RegXMM }

963 movq, 2, 0x66d6, None, 1, CpuAVX, Modrm\|Vex=3\|VexOpcode=0\|VexW=1\|IgnoreSize\|No_b Suf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf\|NoRex64\|SSE2AVX, { RegXMM, Qword\|Un specified\|BaseIndex\|Disp8\|Disp16\|Disp32\|Disp32S\|RegXMM }	963 movq, 2, 0x66d6, None, 1, CpuAVX, Modrm\|Vex=3\|VexOpcode=0\|VexW=1\|IgnoreSize\|No_b Suf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf\|NoRex64\|SSE2AVX, { RegXMM, Qword\|Un specified\|BaseIndex\|Disp8\|Disp16\|Disp32\|Disp32S\|RegXMM }

964 movq, 2, 0x666e, None, 1, CpuAVX\|Cpu64, Modrm\|Vex=3\|VexOpcode=0\|IgnoreSize\|No_bS uf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf\|SSE2AVX, { Reg64\|Qword\|Unspecified\|B aseIndex\|Disp8\|Disp32\|Disp32S, RegXMM }	964 movq, 2, 0x666e, None, 1, CpuAVX\|Cpu64, Modrm\|Vex=3\|VexOpcode=0\|IgnoreSize\|No_bS uf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf\|SSE2AVX, { Reg64\|Qword\|Unspecified\|B aseIndex\|Disp8\|Disp32\|Disp32S, RegXMM }

965 movq, 2, 0x667e, None, 1, CpuAVX\|Cpu64, Modrm\|Vex=3\|VexOpcode=0\|IgnoreSize\|No_bS uf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf\|SSE2AVX, { RegXMM, Reg64\|Qword\|Unspe cified\|BaseIndex\|Disp8\|Disp32\|Disp32S }	965 movq, 2, 0x667e, None, 1, CpuAVX\|Cpu64, Modrm\|Vex=3\|VexOpcode=0\|IgnoreSize\|No_bS uf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf\|SSE2AVX, { RegXMM, Reg64\|Qword\|Unspe cified\|BaseIndex\|Disp8\|Disp32\|Disp32S }

966 movq, 2, 0xf30f7e, None, 2, CpuSSE2, S\|Modrm\|IgnoreSize\|No_bSuf\|No_wSuf\|No_lSuf\| No_sSuf\|No_qSuf\|No_ldSuf\|NoRex64, { Unspecified\|Qword\|BaseIndex\|Disp8\|Disp16\|Dis p32\|Disp32S\|RegXMM, RegXMM }	966 movq, 2, 0xf30f7e, None, 2, CpuSSE2, S\|Modrm\|IgnoreSize\|No_bSuf\|No_wSuf\|No_lSuf\| No_sSuf\|No_qSuf\|No_ldSuf\|NoRex64, { Unspecified\|Qword\|BaseIndex\|Disp8\|Disp16\|Dis p32\|Disp32S\|RegXMM, RegXMM }

967 movq, 2, 0x660fd6, None, 2, CpuSSE2, Modrm\|IgnoreSize\|No_bSuf\|No_wSuf\|No_lSuf\|No _sSuf\|No_qSuf\|No_ldSuf\|NoRex64, { RegXMM, Unspecified\|Qword\|BaseIndex\|Disp8\|Disp 16\|Disp32\|Disp32S\|RegXMM }	967 movq, 2, 0x660fd6, None, 2, CpuSSE2, Modrm\|IgnoreSize\|No_bSuf\|No_wSuf\|No_lSuf\|No _sSuf\|No_qSuf\|No_ldSuf\|NoRex64, { RegXMM, Unspecified\|Qword\|BaseIndex\|Disp8\|Disp 16\|Disp32\|Disp32S\|RegXMM }

968 movq, 2, 0x660f6e, None, 2, Cpu64, Modrm\|IgnoreSize\|No_bSuf\|No_wSuf\|No_lSuf\|No_s Suf\|No_qSuf\|No_ldSuf, { Reg64\|Unspecified\|Qword\|BaseIndex\|Disp8\|Disp32\|Disp32S, RegXMM }	968 movq, 2, 0x660f6e, None, 2, Cpu64, Modrm\|IgnoreSize\|No_bSuf\|No_wSuf\|No_lSuf\|No_s Suf\|No_qSuf\|No_ldSuf, { Reg64\|Unspecified\|Qword\|BaseIndex\|Disp8\|Disp32\|Disp32S, RegXMM }

969 movq, 2, 0x660f7e, None, 2, Cpu64, Modrm\|IgnoreSize\|No_bSuf\|No_wSuf\|No_lSuf\|No_s Suf\|No_qSuf\|No_ldSuf, { RegXMM, Reg64\|Unspecified\|Qword\|BaseIndex\|Disp8\|Disp32\|D isp32S }	969 movq, 2, 0x660f7e, None, 2, Cpu64, Modrm\|IgnoreSize\|No_bSuf\|No_wSuf\|No_lSuf\|No_s Suf\|No_qSuf\|No_ldSuf, { RegXMM, Reg64\|Unspecified\|Qword\|BaseIndex\|Disp8\|Disp32\|D isp32S }

970 movq, 2, 0xf6f, None, 2, CpuMMX, S\|Modrm\|IgnoreSize\|No_bSuf\|No_wSuf\|No_lSuf\|No_s Suf\|No_qSuf\|No_ldSuf\|NoRex64, { Unspecified\|Qword\|BaseIndex\|Disp8\|Disp16\|Disp32\| Disp32S\|RegMMX, RegMMX }	970 movq, 2, 0xf6f, None, 2, CpuMMX, S\|Modrm\|IgnoreSize\|No_bSuf\|No_wSuf\|No_lSuf\|No_s Suf\|No_qSuf\|No_ldSuf\|NoRex64, { Unspecified\|Qword\|BaseIndex\|Disp8\|Disp16\|Disp32\| Disp32S\|RegMMX, RegMMX }

(...skipping 393 matching lines...) Expand 10 before \| Expand all \| Expand 10 after Loading...
1364 cmpordpd, 2, 0x660fc2, 0x7, 2, CpuSSE2, Modrm\|IgnoreSize\|No_bSuf\|No_wSuf\|No_lSuf \|No_sSuf\|No_qSuf\|No_ldSuf\|ImmExt, { Xmmword\|Unspecified\|BaseIndex\|Disp8\|Disp16\|D isp32\|Disp32S\|RegXMM, RegXMM }	1364 cmpordpd, 2, 0x660fc2, 0x7, 2, CpuSSE2, Modrm\|IgnoreSize\|No_bSuf\|No_wSuf\|No_lSuf \|No_sSuf\|No_qSuf\|No_ldSuf\|ImmExt, { Xmmword\|Unspecified\|BaseIndex\|Disp8\|Disp16\|D isp32\|Disp32S\|RegXMM, RegXMM }

1365 cmpordsd, 2, 0xf2c2, 0x7, 1, CpuAVX, Modrm\|Vex=3\|VexOpcode=0\|VexVVVV=1\|VexW=1\|Ig noreSize\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf\|ImmExt\|SSE2AVX, { Qwor d\|Unspecified\|BaseIndex\|Disp8\|Disp16\|Disp32\|Disp32S\|RegXMM, RegXMM }	1365 cmpordsd, 2, 0xf2c2, 0x7, 1, CpuAVX, Modrm\|Vex=3\|VexOpcode=0\|VexVVVV=1\|VexW=1\|Ig noreSize\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf\|ImmExt\|SSE2AVX, { Qwor d\|Unspecified\|BaseIndex\|Disp8\|Disp16\|Disp32\|Disp32S\|RegXMM, RegXMM }

1366 cmpordsd, 2, 0xf20fc2, 0x7, 2, CpuSSE2, Modrm\|IgnoreSize\|No_bSuf\|No_wSuf\|No_lSuf \|No_sSuf\|No_qSuf\|No_ldSuf\|ImmExt, { Qword\|Unspecified\|BaseIndex\|Disp8\|Disp16\|Dis p32\|Disp32S\|RegXMM, RegXMM }	1366 cmpordsd, 2, 0xf20fc2, 0x7, 2, CpuSSE2, Modrm\|IgnoreSize\|No_bSuf\|No_wSuf\|No_lSuf \|No_sSuf\|No_qSuf\|No_ldSuf\|ImmExt, { Qword\|Unspecified\|BaseIndex\|Disp8\|Disp16\|Dis p32\|Disp32S\|RegXMM, RegXMM }

1367 cmpunordpd, 2, 0x66c2, 0x3, 1, CpuAVX, Modrm\|Vex\|VexOpcode=0\|VexVVVV=1\|VexW=1\|Ig noreSize\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf\|ImmExt\|SSE2AVX, { Xmmw ord\|Unspecified\|BaseIndex\|Disp8\|Disp16\|Disp32\|Disp32S\|RegXMM, RegXMM }	1367 cmpunordpd, 2, 0x66c2, 0x3, 1, CpuAVX, Modrm\|Vex\|VexOpcode=0\|VexVVVV=1\|VexW=1\|Ig noreSize\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf\|ImmExt\|SSE2AVX, { Xmmw ord\|Unspecified\|BaseIndex\|Disp8\|Disp16\|Disp32\|Disp32S\|RegXMM, RegXMM }

1368 cmpunordpd, 2, 0x660fc2, 0x3, 2, CpuSSE2, Modrm\|IgnoreSize\|No_bSuf\|No_wSuf\|No_lS uf\|No_sSuf\|No_qSuf\|No_ldSuf\|ImmExt, { Xmmword\|Unspecified\|BaseIndex\|Disp8\|Disp16 \|Disp32\|Disp32S\|RegXMM, RegXMM }	1368 cmpunordpd, 2, 0x660fc2, 0x3, 2, CpuSSE2, Modrm\|IgnoreSize\|No_bSuf\|No_wSuf\|No_lS uf\|No_sSuf\|No_qSuf\|No_ldSuf\|ImmExt, { Xmmword\|Unspecified\|BaseIndex\|Disp8\|Disp16 \|Disp32\|Disp32S\|RegXMM, RegXMM }

1369 cmpunordsd, 2, 0xf2c2, 0x3, 1, CpuAVX, Modrm\|Vex=3\|VexOpcode=0\|VexVVVV=1\|VexW=1\| IgnoreSize\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf\|ImmExt\|SSE2AVX, { Qw ord\|Unspecified\|BaseIndex\|Disp8\|Disp16\|Disp32\|Disp32S\|RegXMM, RegXMM }	1369 cmpunordsd, 2, 0xf2c2, 0x3, 1, CpuAVX, Modrm\|Vex=3\|VexOpcode=0\|VexVVVV=1\|VexW=1\| IgnoreSize\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf\|ImmExt\|SSE2AVX, { Qw ord\|Unspecified\|BaseIndex\|Disp8\|Disp16\|Disp32\|Disp32S\|RegXMM, RegXMM }

1370 cmpunordsd, 2, 0xf20fc2, 0x3, 2, CpuSSE2, Modrm\|IgnoreSize\|No_bSuf\|No_wSuf\|No_lS uf\|No_sSuf\|No_qSuf\|No_ldSuf\|ImmExt, { Qword\|Unspecified\|BaseIndex\|Disp8\|Disp16\|D isp32\|Disp32S\|RegXMM, RegXMM }	1370 cmpunordsd, 2, 0xf20fc2, 0x3, 2, CpuSSE2, Modrm\|IgnoreSize\|No_bSuf\|No_wSuf\|No_lS uf\|No_sSuf\|No_qSuf\|No_ldSuf\|ImmExt, { Qword\|Unspecified\|BaseIndex\|Disp8\|Disp16\|D isp32\|Disp32S\|RegXMM, RegXMM }

1371 cmppd, 3, 0x66c2, None, 1, CpuAVX, Modrm\|Vex\|VexOpcode=0\|VexVVVV=1\|VexW=1\|Ignore Size\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf\|SSE2AVX, { Imm8, Xmmword\|U nspecified\|BaseIndex\|Disp8\|Disp16\|Disp32\|Disp32S\|RegXMM, RegXMM }	1371 cmppd, 3, 0x66c2, None, 1, CpuAVX, Modrm\|Vex\|VexOpcode=0\|VexVVVV=1\|VexW=1\|Ignore Size\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf\|SSE2AVX, { Imm8, Xmmword\|U nspecified\|BaseIndex\|Disp8\|Disp16\|Disp32\|Disp32S\|RegXMM, RegXMM }

1372 cmppd, 3, 0x660fc2, None, 2, CpuSSE2, Modrm\|IgnoreSize\|No_bSuf\|No_wSuf\|No_lSuf\|N o_sSuf\|No_qSuf\|No_ldSuf, { Imm8, Xmmword\|Unspecified\|BaseIndex\|Disp8\|Disp16\|Disp 32\|Disp32S\|RegXMM, RegXMM }	1372 cmppd, 3, 0x660fc2, None, 2, CpuSSE2, Modrm\|IgnoreSize\|No_bSuf\|No_wSuf\|No_lSuf\|N o_sSuf\|No_qSuf\|No_ldSuf, { Imm8, Xmmword\|Unspecified\|BaseIndex\|Disp8\|Disp16\|Disp 32\|Disp32S\|RegXMM, RegXMM }

1373 // Intel mode string compare.	1373 // Intel mode string compare.

1374 cmpsd, 0, 0xa7, None, 1, 0, Size32\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ld Suf\|IsString, { 0 }	1374 cmpsd, 0, 0xa7, None, 1, 0, Size32\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ld Suf\|IsString\|RepPrefixOk, { 0 }

1375 cmpsd, 2, 0xa7, None, 1, 0, Size32\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ld Suf\|IsString, { Unspecified\|BaseIndex\|Disp8\|Disp16\|Disp32\|Disp32S, Unspecified\|B aseIndex\|Disp8\|Disp16\|Disp32\|Disp32S\|EsSeg }	1375 cmpsd, 2, 0xa7, None, 1, 0, Size32\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ld Suf\|IsString\|RepPrefixOk, { Unspecified\|BaseIndex\|Disp8\|Disp16\|Disp32\|Disp32S, U nspecified\|BaseIndex\|Disp8\|Disp16\|Disp32\|Disp32S\|EsSeg }

1376 cmpsd, 3, 0xf2c2, None, 1, CpuAVX, Modrm\|Vex=3\|VexOpcode=0\|VexVVVV=1\|VexW=1\|Igno reSize\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf\|SSE2AVX, { Imm8, Qword\|U nspecified\|BaseIndex\|Disp8\|Disp16\|Disp32\|Disp32S\|RegXMM, RegXMM }	1376 cmpsd, 3, 0xf2c2, None, 1, CpuAVX, Modrm\|Vex=3\|VexOpcode=0\|VexVVVV=1\|VexW=1\|Igno reSize\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf\|SSE2AVX, { Imm8, Qword\|U nspecified\|BaseIndex\|Disp8\|Disp16\|Disp32\|Disp32S\|RegXMM, RegXMM }

1377 cmpsd, 3, 0xf20fc2, None, 2, CpuSSE2, Modrm\|IgnoreSize\|No_bSuf\|No_wSuf\|No_lSuf\|N o_sSuf\|No_qSuf\|No_ldSuf, { Imm8, Qword\|Unspecified\|BaseIndex\|Disp8\|Disp16\|Disp32 \|Disp32S\|RegXMM, RegXMM }	1377 cmpsd, 3, 0xf20fc2, None, 2, CpuSSE2, Modrm\|IgnoreSize\|No_bSuf\|No_wSuf\|No_lSuf\|N o_sSuf\|No_qSuf\|No_ldSuf, { Imm8, Qword\|Unspecified\|BaseIndex\|Disp8\|Disp16\|Disp32 \|Disp32S\|RegXMM, RegXMM }

1378 comisd, 2, 0x662f, None, 1, CpuAVX, Modrm\|Vex=3\|VexOpcode=0\|VexW=1\|IgnoreSize\|No _bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf\|SSE2AVX, { Qword\|Unspecified\|Base Index\|Disp8\|Disp16\|Disp32\|Disp32S\|RegXMM, RegXMM }	1378 comisd, 2, 0x662f, None, 1, CpuAVX, Modrm\|Vex=3\|VexOpcode=0\|VexW=1\|IgnoreSize\|No _bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf\|SSE2AVX, { Qword\|Unspecified\|Base Index\|Disp8\|Disp16\|Disp32\|Disp32S\|RegXMM, RegXMM }

1379 comisd, 2, 0x660f2f, None, 2, CpuSSE2, Modrm\|IgnoreSize\|No_bSuf\|No_wSuf\|No_lSuf\| No_sSuf\|No_qSuf\|No_ldSuf, { Qword\|Unspecified\|BaseIndex\|Disp8\|Disp16\|Disp32\|Disp 32S\|RegXMM, RegXMM }	1379 comisd, 2, 0x660f2f, None, 2, CpuSSE2, Modrm\|IgnoreSize\|No_bSuf\|No_wSuf\|No_lSuf\| No_sSuf\|No_qSuf\|No_ldSuf, { Qword\|Unspecified\|BaseIndex\|Disp8\|Disp16\|Disp32\|Disp 32S\|RegXMM, RegXMM }

1380 cvtpi2pd, 2, 0x660f2a, None, 2, CpuSSE2, Modrm\|IgnoreSize\|No_bSuf\|No_wSuf\|No_lSu f\|No_sSuf\|No_qSuf\|No_ldSuf\|NoAVX, { Qword\|Unspecified\|BaseIndex\|Disp8\|Disp16\|Dis p32\|Disp32S\|RegMMX, RegXMM }	1380 cvtpi2pd, 2, 0x660f2a, None, 2, CpuSSE2, Modrm\|IgnoreSize\|No_bSuf\|No_wSuf\|No_lSu f\|No_sSuf\|No_qSuf\|No_ldSuf\|NoAVX, { Qword\|Unspecified\|BaseIndex\|Disp8\|Disp16\|Dis p32\|Disp32S\|RegMMX, RegXMM }

1381 cvtsi2sd, 2, 0xf22a, None, 1, CpuAVX\|CpuNo64, Modrm\|Vex=3\|VexOpcode=0\|VexVVVV=1\| IgnoreSize\|No_bSuf\|No_wSuf\|No_sSuf\|No_qSuf\|No_ldSuf\|SSE2AVX, { Reg32\|Dword\|Unspe cified\|BaseIndex\|Disp8\|Disp16\|Disp32\|Disp32S, RegXMM }	1381 cvtsi2sd, 2, 0xf22a, None, 1, CpuAVX\|CpuNo64, Modrm\|Vex=3\|VexOpcode=0\|VexVVVV=1\| IgnoreSize\|No_bSuf\|No_wSuf\|No_sSuf\|No_qSuf\|No_ldSuf\|SSE2AVX, { Reg32\|Dword\|Unspe cified\|BaseIndex\|Disp8\|Disp16\|Disp32\|Disp32S, RegXMM }

1382 cvtsi2sd, 2, 0xf22a, None, 1, CpuAVX\|Cpu64, Modrm\|Vex=3\|VexOpcode=0\|VexVVVV=1\|No _bSuf\|No_wSuf\|No_sSuf\|No_ldSuf\|SSE2AVX, { Reg32\|Reg64\|Dword\|Qword\|Unspecified\|Ba seIndex\|Disp8\|Disp16\|Disp32\|Disp32S, RegXMM }	1382 cvtsi2sd, 2, 0xf22a, None, 1, CpuAVX\|Cpu64, Modrm\|Vex=3\|VexOpcode=0\|VexVVVV=1\|No _bSuf\|No_wSuf\|No_sSuf\|No_ldSuf\|SSE2AVX, { Reg32\|Reg64\|Dword\|Qword\|Unspecified\|Ba seIndex\|Disp8\|Disp16\|Disp32\|Disp32S, RegXMM }

1383 cvtsi2sd, 2, 0xf20f2a, None, 2, CpuSSE2\|CpuNo64, Modrm\|IgnoreSize\|No_bSuf\|No_wSu f\|No_sSuf\|No_qSuf\|No_ldSuf, { Reg32\|Dword\|Unspecified\|BaseIndex\|Disp8\|Disp16\|Dis p32\|Disp32S, RegXMM }	1383 cvtsi2sd, 2, 0xf20f2a, None, 2, CpuSSE2\|CpuNo64, Modrm\|IgnoreSize\|No_bSuf\|No_wSu f\|No_sSuf\|No_qSuf\|No_ldSuf, { Reg32\|Dword\|Unspecified\|BaseIndex\|Disp8\|Disp16\|Dis p32\|Disp32S, RegXMM }

1384 cvtsi2sd, 2, 0xf20f2a, None, 2, CpuSSE2\|Cpu64, Modrm\|No_bSuf\|No_wSuf\|No_sSuf\|No_ ldSuf, { Reg32\|Reg64\|Dword\|Qword\|Unspecified\|BaseIndex\|Disp8\|Disp16\|Disp32\|Disp3 2S, RegXMM }	1384 cvtsi2sd, 2, 0xf20f2a, None, 2, CpuSSE2\|Cpu64, Modrm\|No_bSuf\|No_wSuf\|No_sSuf\|No_ ldSuf, { Reg32\|Reg64\|Dword\|Qword\|Unspecified\|BaseIndex\|Disp8\|Disp16\|Disp32\|Disp3 2S, RegXMM }

1385 divpd, 2, 0x665e, None, 1, CpuAVX, Modrm\|Vex\|VexOpcode=0\|VexVVVV=1\|VexW=1\|Ignore Size\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf\|SSE2AVX, { Xmmword\|Unspeci fied\|BaseIndex\|Disp8\|Disp16\|Disp32\|Disp32S\|RegXMM, RegXMM }	1385 divpd, 2, 0x665e, None, 1, CpuAVX, Modrm\|Vex\|VexOpcode=0\|VexVVVV=1\|VexW=1\|Ignore Size\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf\|SSE2AVX, { Xmmword\|Unspeci fied\|BaseIndex\|Disp8\|Disp16\|Disp32\|Disp32S\|RegXMM, RegXMM }

(...skipping 18 matching lines...) Expand all Loading...
1404 movhpd, 2, 0x660f17, None, 2, CpuSSE2, Modrm\|IgnoreSize\|No_bSuf\|No_wSuf\|No_lSuf\| No_sSuf\|No_qSuf\|No_ldSuf, { RegXMM, Qword\|Unspecified\|BaseIndex\|Disp8\|Disp16\|Dis p32\|Disp32S }	1404 movhpd, 2, 0x660f17, None, 2, CpuSSE2, Modrm\|IgnoreSize\|No_bSuf\|No_wSuf\|No_lSuf\| No_sSuf\|No_qSuf\|No_ldSuf, { RegXMM, Qword\|Unspecified\|BaseIndex\|Disp8\|Disp16\|Dis p32\|Disp32S }

1405 movlpd, 2, 0x6612, None, 1, CpuAVX, Modrm\|Vex\|VexOpcode=0\|VexVVVV=1\|VexW=1\|Ignor eSize\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf\|SSE2AVX, { Qword\|Unspecif ied\|BaseIndex\|Disp8\|Disp16\|Disp32\|Disp32S, RegXMM }	1405 movlpd, 2, 0x6612, None, 1, CpuAVX, Modrm\|Vex\|VexOpcode=0\|VexVVVV=1\|VexW=1\|Ignor eSize\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf\|SSE2AVX, { Qword\|Unspecif ied\|BaseIndex\|Disp8\|Disp16\|Disp32\|Disp32S, RegXMM }

1406 movlpd, 2, 0x6613, None, 1, CpuAVX, Modrm\|Vex\|VexOpcode=0\|VexW=1\|IgnoreSize\|No_b Suf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf\|SSE2AVX, { RegXMM, Qword\|Unspecifie d\|BaseIndex\|Disp8\|Disp16\|Disp32\|Disp32S }	1406 movlpd, 2, 0x6613, None, 1, CpuAVX, Modrm\|Vex\|VexOpcode=0\|VexW=1\|IgnoreSize\|No_b Suf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf\|SSE2AVX, { RegXMM, Qword\|Unspecifie d\|BaseIndex\|Disp8\|Disp16\|Disp32\|Disp32S }

1407 movlpd, 2, 0x660f12, None, 2, CpuSSE2, Modrm\|IgnoreSize\|No_bSuf\|No_wSuf\|No_lSuf\| No_sSuf\|No_qSuf\|No_ldSuf, { Qword\|Unspecified\|BaseIndex\|Disp8\|Disp16\|Disp32\|Disp 32S, RegXMM }	1407 movlpd, 2, 0x660f12, None, 2, CpuSSE2, Modrm\|IgnoreSize\|No_bSuf\|No_wSuf\|No_lSuf\| No_sSuf\|No_qSuf\|No_ldSuf, { Qword\|Unspecified\|BaseIndex\|Disp8\|Disp16\|Disp32\|Disp 32S, RegXMM }

1408 movlpd, 2, 0x660f13, None, 2, CpuSSE2, Modrm\|IgnoreSize\|No_bSuf\|No_wSuf\|No_lSuf\| No_sSuf\|No_qSuf\|No_ldSuf, { RegXMM, Qword\|Unspecified\|BaseIndex\|Disp8\|Disp16\|Dis p32\|Disp32S }	1408 movlpd, 2, 0x660f13, None, 2, CpuSSE2, Modrm\|IgnoreSize\|No_bSuf\|No_wSuf\|No_lSuf\| No_sSuf\|No_qSuf\|No_ldSuf, { RegXMM, Qword\|Unspecified\|BaseIndex\|Disp8\|Disp16\|Dis p32\|Disp32S }

1409 movmskpd, 2, 0x6650, None, 1, CpuAVX, Modrm\|Vex\|VexOpcode=0\|VexW=1\|IgnoreSize\|No _bSuf\|No_wSuf\|No_sSuf\|No_ldSuf\|NoRex64\|SSE2AVX, { RegXMM, Reg32\|Reg64 }	1409 movmskpd, 2, 0x6650, None, 1, CpuAVX, Modrm\|Vex\|VexOpcode=0\|VexW=1\|IgnoreSize\|No _bSuf\|No_wSuf\|No_sSuf\|No_ldSuf\|NoRex64\|SSE2AVX, { RegXMM, Reg32\|Reg64 }

1410 movmskpd, 2, 0x660f50, None, 2, CpuSSE2, Modrm\|IgnoreSize\|No_bSuf\|No_wSuf\|No_sSu f\|No_ldSuf\|NoRex64, { RegXMM, Reg32\|Reg64 }	1410 movmskpd, 2, 0x660f50, None, 2, CpuSSE2, Modrm\|IgnoreSize\|No_bSuf\|No_wSuf\|No_sSu f\|No_ldSuf\|NoRex64, { RegXMM, Reg32\|Reg64 }

1411 movntpd, 2, 0x662b, None, 1, CpuAVX, Modrm\|Vex\|VexOpcode=0\|VexW=1\|IgnoreSize\|No_ bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf\|SSE2AVX, { RegXMM, Xmmword\|Unspeci fied\|BaseIndex\|Disp8\|Disp16\|Disp32\|Disp32S }	1411 movntpd, 2, 0x662b, None, 1, CpuAVX, Modrm\|Vex\|VexOpcode=0\|VexW=1\|IgnoreSize\|No_ bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf\|SSE2AVX, { RegXMM, Xmmword\|Unspeci fied\|BaseIndex\|Disp8\|Disp16\|Disp32\|Disp32S }

1412 movntpd, 2, 0x660f2b, None, 2, CpuSSE2, Modrm\|IgnoreSize\|No_bSuf\|No_wSuf\|No_lSuf \|No_sSuf\|No_qSuf\|No_ldSuf, { RegXMM, Xmmword\|Unspecified\|BaseIndex\|Disp8\|Disp16\| Disp32\|Disp32S }	1412 movntpd, 2, 0x660f2b, None, 2, CpuSSE2, Modrm\|IgnoreSize\|No_bSuf\|No_wSuf\|No_lSuf \|No_sSuf\|No_qSuf\|No_ldSuf, { RegXMM, Xmmword\|Unspecified\|BaseIndex\|Disp8\|Disp16\| Disp32\|Disp32S }

1413 // Intel mode string move.	1413 // Intel mode string move.

1414 movsd, 0, 0xa5, None, 1, 0, Size32\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ld Suf\|IsString, { 0 }	1414 movsd, 0, 0xa5, None, 1, 0, Size32\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ld Suf\|IsString\|RepPrefixOk, { 0 }

1415 movsd, 2, 0xa5, None, 1, 0, Size32\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ld Suf\|IsString, { Unspecified\|BaseIndex\|Disp8\|Disp16\|Disp32\|Disp32S, Unspecified\|B aseIndex\|Disp8\|Disp16\|Disp32\|Disp32S\|EsSeg }	1415 movsd, 2, 0xa5, None, 1, 0, Size32\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ld Suf\|IsString\|RepPrefixOk, { Unspecified\|BaseIndex\|Disp8\|Disp16\|Disp32\|Disp32S, U nspecified\|BaseIndex\|Disp8\|Disp16\|Disp32\|Disp32S\|EsSeg }

1416 movsd, 2, 0xf211, None, 1, CpuAVX, Modrm\|Vex=3\|VexOpcode=0\|VexW=1\|IgnoreSize\|No_ bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf\|SSE2AVX, { RegXMM, Qword\|Unspecifi ed\|BaseIndex\|Disp8\|Disp16\|Disp32\|Disp32S }	1416 movsd, 2, 0xf211, None, 1, CpuAVX, Modrm\|Vex=3\|VexOpcode=0\|VexW=1\|IgnoreSize\|No_ bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf\|SSE2AVX, { RegXMM, Qword\|Unspecifi ed\|BaseIndex\|Disp8\|Disp16\|Disp32\|Disp32S }

1417 movsd, 2, 0xf210, None, 1, CpuAVX, Modrm\|Vex=3\|VexOpcode=0\|VexW=1\|IgnoreSize\|No_ bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf\|SSE2AVX, { Qword\|Unspecified\|BaseI ndex\|Disp8\|Disp16\|Disp32\|Disp32S, RegXMM }	1417 movsd, 2, 0xf210, None, 1, CpuAVX, Modrm\|Vex=3\|VexOpcode=0\|VexW=1\|IgnoreSize\|No_ bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf\|SSE2AVX, { Qword\|Unspecified\|BaseI ndex\|Disp8\|Disp16\|Disp32\|Disp32S, RegXMM }

1418 movsd, 2, 0xf210, None, 1, CpuAVX, S\|Modrm\|Vex=3\|VexOpcode=0\|VexVVVV=1\|VexW=1\|Ig noreSize\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf\|SSE2AVX, { RegXMM, Reg XMM }	1418 movsd, 2, 0xf210, None, 1, CpuAVX, S\|Modrm\|Vex=3\|VexOpcode=0\|VexVVVV=1\|VexW=1\|Ig noreSize\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf\|SSE2AVX, { RegXMM, Reg XMM }

1419 movsd, 2, 0xf211, None, 1, CpuAVX, Modrm\|Vex=3\|VexOpcode=0\|VexVVVV=1\|VexW=1\|Igno reSize\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf\|SSE2AVX, { RegXMM, RegXM M\|Regmem }	1419 movsd, 2, 0xf211, None, 1, CpuAVX, Modrm\|Vex=3\|VexOpcode=0\|VexVVVV=1\|VexW=1\|Igno reSize\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf\|SSE2AVX, { RegXMM, RegXM M\|Regmem }

1420 movsd, 2, 0xf20f10, None, 2, CpuSSE2, S\|Modrm\|IgnoreSize\|No_bSuf\|No_wSuf\|No_lSuf \|No_sSuf\|No_qSuf\|No_ldSuf, { Qword\|Unspecified\|BaseIndex\|Disp8\|Disp16\|Disp32\|Dis p32S\|RegXMM, RegXMM }	1420 movsd, 2, 0xf20f10, None, 2, CpuSSE2, S\|Modrm\|IgnoreSize\|No_bSuf\|No_wSuf\|No_lSuf \|No_sSuf\|No_qSuf\|No_ldSuf, { Qword\|Unspecified\|BaseIndex\|Disp8\|Disp16\|Disp32\|Dis p32S\|RegXMM, RegXMM }

1421 movsd, 2, 0xf20f11, None, 2, CpuSSE2, Modrm\|IgnoreSize\|No_bSuf\|No_wSuf\|No_lSuf\|N o_sSuf\|No_qSuf\|No_ldSuf, { RegXMM, Qword\|Unspecified\|BaseIndex\|Disp8\|Disp16\|Disp 32\|Disp32S\|RegXMM }	1421 movsd, 2, 0xf20f11, None, 2, CpuSSE2, Modrm\|IgnoreSize\|No_bSuf\|No_wSuf\|No_lSuf\|N o_sSuf\|No_qSuf\|No_ldSuf, { RegXMM, Qword\|Unspecified\|BaseIndex\|Disp8\|Disp16\|Disp 32\|Disp32S\|RegXMM }

1422 movupd, 2, 0x6610, None, 1, CpuAVX, S\|Modrm\|Vex\|VexOpcode=0\|VexW=1\|IgnoreSize\|No _bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf\|SSE2AVX, { Xmmword\|Unspecified\|Ba seIndex\|Disp8\|Disp16\|Disp32\|Disp32S\|RegXMM, RegXMM }	1422 movupd, 2, 0x6610, None, 1, CpuAVX, S\|Modrm\|Vex\|VexOpcode=0\|VexW=1\|IgnoreSize\|No _bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf\|SSE2AVX, { Xmmword\|Unspecified\|Ba seIndex\|Disp8\|Disp16\|Disp32\|Disp32S\|RegXMM, RegXMM }

1423 movupd, 2, 0x6611, None, 1, CpuAVX, Modrm\|Vex\|VexOpcode=0\|VexW=1\|IgnoreSize\|No_b Suf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf\|SSE2AVX, { RegXMM, Xmmword\|Unspecif ied\|BaseIndex\|Disp8\|Disp16\|Disp32\|Disp32S\|RegXMM }	1423 movupd, 2, 0x6611, None, 1, CpuAVX, Modrm\|Vex\|VexOpcode=0\|VexW=1\|IgnoreSize\|No_b Suf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf\|SSE2AVX, { RegXMM, Xmmword\|Unspecif ied\|BaseIndex\|Disp8\|Disp16\|Disp32\|Disp32S\|RegXMM }

1424 movupd, 2, 0x660f10, None, 2, CpuSSE2, S\|Modrm\|IgnoreSize\|No_bSuf\|No_wSuf\|No_lSu f\|No_sSuf\|No_qSuf\|No_ldSuf, { Xmmword\|Unspecified\|BaseIndex\|Disp8\|Disp16\|Disp32\| Disp32S\|RegXMM, RegXMM }	1424 movupd, 2, 0x660f10, None, 2, CpuSSE2, S\|Modrm\|IgnoreSize\|No_bSuf\|No_wSuf\|No_lSu f\|No_sSuf\|No_qSuf\|No_ldSuf, { Xmmword\|Unspecified\|BaseIndex\|Disp8\|Disp16\|Disp32\| Disp32S\|RegXMM, RegXMM }

1425 movupd, 2, 0x660f11, None, 2, CpuSSE2, Modrm\|IgnoreSize\|No_bSuf\|No_wSuf\|No_lSuf\| No_sSuf\|No_qSuf\|No_ldSuf, { RegXMM, Xmmword\|Unspecified\|BaseIndex\|Disp8\|Disp16\|D isp32\|Disp32S\|RegXMM }	1425 movupd, 2, 0x660f11, None, 2, CpuSSE2, Modrm\|IgnoreSize\|No_bSuf\|No_wSuf\|No_lSuf\| No_sSuf\|No_qSuf\|No_ldSuf, { RegXMM, Xmmword\|Unspecified\|BaseIndex\|Disp8\|Disp16\|D isp32\|Disp32S\|RegXMM }

(...skipping 128 matching lines...) Expand 10 before \| Expand all \| Expand 10 after Loading...
1554 vmresume, 0, 0xf01, 0xc3, 2, CpuVMX, No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ ldSuf\|ImmExt, { 0 }	1554 vmresume, 0, 0xf01, 0xc3, 2, CpuVMX, No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ ldSuf\|ImmExt, { 0 }

1555 vmptrld, 1, 0xfc7, 0x6, 2, CpuVMX, Modrm\|IgnoreSize\|No_bSuf\|No_wSuf\|No_lSuf\|No_s Suf\|No_qSuf\|No_ldSuf\|NoRex64, { Qword\|Unspecified\|BaseIndex\|Disp8\|Disp16\|Disp32\| Disp32S }	1555 vmptrld, 1, 0xfc7, 0x6, 2, CpuVMX, Modrm\|IgnoreSize\|No_bSuf\|No_wSuf\|No_lSuf\|No_s Suf\|No_qSuf\|No_ldSuf\|NoRex64, { Qword\|Unspecified\|BaseIndex\|Disp8\|Disp16\|Disp32\| Disp32S }

1556 vmptrst, 1, 0xfc7, 0x7, 2, CpuVMX, Modrm\|IgnoreSize\|No_bSuf\|No_wSuf\|No_lSuf\|No_s Suf\|No_qSuf\|No_ldSuf\|NoRex64, { Qword\|Unspecified\|BaseIndex\|Disp8\|Disp16\|Disp32\| Disp32S }	1556 vmptrst, 1, 0xfc7, 0x7, 2, CpuVMX, Modrm\|IgnoreSize\|No_bSuf\|No_wSuf\|No_lSuf\|No_s Suf\|No_qSuf\|No_ldSuf\|NoRex64, { Qword\|Unspecified\|BaseIndex\|Disp8\|Disp16\|Disp32\| Disp32S }

1557 vmread, 2, 0xf78, None, 2, CpuVMX\|CpuNo64, Modrm\|No_bSuf\|No_wSuf\|No_sSuf\|No_qSuf \|No_ldSuf, { Reg32, Reg32\|Dword\|Unspecified\|BaseIndex\|Disp8\|Disp16\|Disp32 }	1557 vmread, 2, 0xf78, None, 2, CpuVMX\|CpuNo64, Modrm\|No_bSuf\|No_wSuf\|No_sSuf\|No_qSuf \|No_ldSuf, { Reg32, Reg32\|Dword\|Unspecified\|BaseIndex\|Disp8\|Disp16\|Disp32 }

1558 vmread, 2, 0xf78, None, 2, CpuVMX\|Cpu64, Modrm\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|N o_ldSuf\|NoRex64, { Reg64, Reg64\|Qword\|Unspecified\|BaseIndex\|Disp8\|Disp32\|Disp32S }	1558 vmread, 2, 0xf78, None, 2, CpuVMX\|Cpu64, Modrm\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|N o_ldSuf\|NoRex64, { Reg64, Reg64\|Qword\|Unspecified\|BaseIndex\|Disp8\|Disp32\|Disp32S }

1559 vmwrite, 2, 0xf79, None, 2, CpuVMX\|CpuNo64, Modrm\|No_bSuf\|No_wSuf\|No_sSuf\|No_qSu f\|No_ldSuf, { Reg32\|Dword\|Unspecified\|BaseIndex\|Disp8\|Disp16\|Disp32, Reg32 }	1559 vmwrite, 2, 0xf79, None, 2, CpuVMX\|CpuNo64, Modrm\|No_bSuf\|No_wSuf\|No_sSuf\|No_qSu f\|No_ldSuf, { Reg32\|Dword\|Unspecified\|BaseIndex\|Disp8\|Disp16\|Disp32, Reg32 }

1560 vmwrite, 2, 0xf79, None, 2, CpuVMX\|Cpu64, Modrm\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\| No_ldSuf\|NoRex64, { Reg64\|Qword\|Unspecified\|BaseIndex\|Disp8\|Disp32\|Disp32S, Reg6 4 }	1560 vmwrite, 2, 0xf79, None, 2, CpuVMX\|Cpu64, Modrm\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\| No_ldSuf\|NoRex64, { Reg64\|Qword\|Unspecified\|BaseIndex\|Disp8\|Disp32\|Disp32S, Reg6 4 }

1561 vmxoff, 0, 0xf01, 0xc4, 2, CpuVMX, No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ld Suf\|ImmExt, { 0 }	1561 vmxoff, 0, 0xf01, 0xc4, 2, CpuVMX, No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ld Suf\|ImmExt, { 0 }

1562 vmxon, 1, 0xf30fc7, 0x6, 2, CpuVMX, Modrm\|IgnoreSize\|No_bSuf\|No_wSuf\|No_lSuf\|No_ sSuf\|No_qSuf\|No_ldSuf\|NoRex64, { Qword\|Unspecified\|BaseIndex\|Disp8\|Disp16\|Disp32 \|Disp32S }	1562 vmxon, 1, 0xf30fc7, 0x6, 2, CpuVMX, Modrm\|IgnoreSize\|No_bSuf\|No_wSuf\|No_lSuf\|No_ sSuf\|No_qSuf\|No_ldSuf\|NoRex64, { Qword\|Unspecified\|BaseIndex\|Disp8\|Disp16\|Disp32 \|Disp32S }

1563	1563

	1564 // VMFUNC instruction

	1565

	1566 vmfunc, 0, 0xf01, 0xd4, 2, CpuVMFUNC, No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No _ldSuf\|ImmExt, { 0 }

	1567

1564 // SMX instructions.	1568 // SMX instructions.

1565	1569

1566 getsec, 0, 0xf37, None, 2, CpuSMX, No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ld Suf, { 0 }	1570 getsec, 0, 0xf37, None, 2, CpuSMX, No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ld Suf, { 0 }

1567	1571

1568 // EPT instructions.	1572 // EPT instructions.

1569	1573

1570 invept, 2, 0x660f3880, None, 3, CpuEPT\|CpuNo64, Modrm\|IgnoreSize\|No_bSuf\|No_wSuf \|No_lSuf\|No_qSuf\|No_sSuf\|No_ldSuf, { Oword\|Unspecified\|BaseIndex\|Disp8\|Disp16\|Di sp32\|Disp32S, Reg32 }	1574 invept, 2, 0x660f3880, None, 3, CpuEPT\|CpuNo64, Modrm\|IgnoreSize\|No_bSuf\|No_wSuf \|No_lSuf\|No_qSuf\|No_sSuf\|No_ldSuf, { Oword\|Unspecified\|BaseIndex\|Disp8\|Disp16\|Di sp32\|Disp32S, Reg32 }

1571 invept, 2, 0x660f3880, None, 3, CpuEPT\|Cpu64, Modrm\|IgnoreSize\|No_bSuf\|No_wSuf\|N o_lSuf\|No_qSuf\|No_sSuf\|No_ldSuf\|NoRex64, { Oword\|Unspecified\|BaseIndex\|Disp8\|Dis p16\|Disp32\|Disp32S, Reg64 }	1575 invept, 2, 0x660f3880, None, 3, CpuEPT\|Cpu64, Modrm\|IgnoreSize\|No_bSuf\|No_wSuf\|N o_lSuf\|No_qSuf\|No_sSuf\|No_ldSuf\|NoRex64, { Oword\|Unspecified\|BaseIndex\|Disp8\|Dis p16\|Disp32\|Disp32S, Reg64 }

1572 invvpid, 2, 0x660f3881, None, 3, CpuEPT\|CpuNo64, Modrm\|IgnoreSize\|No_bSuf\|No_wSu f\|No_lSuf\|No_qSuf\|No_sSuf\|No_ldSuf, { Oword\|Unspecified\|BaseIndex\|Disp8\|Disp16\|D isp32\|Disp32S, Reg32 }	1576 invvpid, 2, 0x660f3881, None, 3, CpuEPT\|CpuNo64, Modrm\|IgnoreSize\|No_bSuf\|No_wSu f\|No_lSuf\|No_qSuf\|No_sSuf\|No_ldSuf, { Oword\|Unspecified\|BaseIndex\|Disp8\|Disp16\|D isp32\|Disp32S, Reg32 }

1573 invvpid, 2, 0x660f3881, None, 3, CpuEPT\|Cpu64, Modrm\|IgnoreSize\|No_bSuf\|No_wSuf\| No_lSuf\|No_qSuf\|No_sSuf\|No_ldSuf\|NoRex64, { Oword\|Unspecified\|BaseIndex\|Disp8\|Di sp16\|Disp32\|Disp32S, Reg64 }	1577 invvpid, 2, 0x660f3881, None, 3, CpuEPT\|Cpu64, Modrm\|IgnoreSize\|No_bSuf\|No_wSuf\| No_lSuf\|No_qSuf\|No_sSuf\|No_ldSuf\|NoRex64, { Oword\|Unspecified\|BaseIndex\|Disp8\|Di sp16\|Disp32\|Disp32S, Reg64 }

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1754	1758

1755 // xsave/xrstor New Instructions.	1759 // xsave/xrstor New Instructions.

1756	1760

1757 xsave, 1, 0xfae, 0x4, 2, CpuXsave, Modrm\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_ldSu f, { Unspecified\|BaseIndex\|Disp8\|Disp16\|Disp32\|Disp32S }	1761 xsave, 1, 0xfae, 0x4, 2, CpuXsave, Modrm\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_ldSu f, { Unspecified\|BaseIndex\|Disp8\|Disp16\|Disp32\|Disp32S }

1758 xsave64, 1, 0xfae, 0x4, 2, CpuXsave\|Cpu64, Modrm\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf \|No_ldSuf\|Rex64, { Unspecified\|BaseIndex\|Disp8\|Disp16\|Disp32\|Disp32S }	1762 xsave64, 1, 0xfae, 0x4, 2, CpuXsave\|Cpu64, Modrm\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf \|No_ldSuf\|Rex64, { Unspecified\|BaseIndex\|Disp8\|Disp16\|Disp32\|Disp32S }

1759 xrstor, 1, 0xfae, 0x5, 2, CpuXsave, Modrm\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_ldS uf, { Unspecified\|BaseIndex\|Disp8\|Disp16\|Disp32\|Disp32S }	1763 xrstor, 1, 0xfae, 0x5, 2, CpuXsave, Modrm\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_ldS uf, { Unspecified\|BaseIndex\|Disp8\|Disp16\|Disp32\|Disp32S }

1760 xrstor64, 1, 0xfae, 0x5, 2, CpuXsave\|Cpu64, Modrm\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSu f\|No_ldSuf\|Rex64, { Unspecified\|BaseIndex\|Disp8\|Disp16\|Disp32\|Disp32S }	1764 xrstor64, 1, 0xfae, 0x5, 2, CpuXsave\|Cpu64, Modrm\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSu f\|No_ldSuf\|Rex64, { Unspecified\|BaseIndex\|Disp8\|Disp16\|Disp32\|Disp32S }

1761 xgetbv, 0, 0xf01, 0xd0, 2, CpuXsave, No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ ldSuf\|ImmExt, { 0 }	1765 xgetbv, 0, 0xf01, 0xd0, 2, CpuXsave, No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ ldSuf\|ImmExt, { 0 }

1762 xsetbv, 0, 0xf01, 0xd1, 2, CpuXsave, No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ ldSuf\|ImmExt, { 0 }	1766 xsetbv, 0, 0xf01, 0xd1, 2, CpuXsave, No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ ldSuf\|ImmExt, { 0 }

1763	1767

1764 // xsaveopt	1768 // xsaveopt

1765 xsaveopt, 1, 0xfae, 0x6, 2, CpuXsaveopt, Modrm\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|N o_ldSuf, { Unspecified\|BaseIndex\|Disp8\|Disp16\|Disp32\|Disp32S }	1769 xsaveopt, 1, 0xfae, 0x6, 2, CpuXsaveopt, Modrm\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|N o_ldSuf, { Unspecified\|BaseIndex\|Disp8\|Disp16\|Disp32\|Disp32S }

1766 xsaveopt64, 1, 0xfae, 0x6, 2, CpuXsaveopt\|Cpu64, Modrm\|No_bSuf\|No_wSuf\|No_lSuf\|N o_sSuf\|No_ldSuf\|Rex64, { Unspecified\|BaseIndex\|Disp8\|Disp16\|Disp32\|Disp32S }	1770 xsaveopt64, 1, 0xfae, 0x6, 2, CpuXsaveopt\|Cpu64, Modrm\|No_bSuf\|No_wSuf\|No_lSuf\|N o_sSuf\|No_ldSuf\|Rex64, { Unspecified\|BaseIndex\|Disp8\|Disp16\|Disp32\|Disp32S }

1767	1771

1768 // AES instructions.	1772 // AES instructions.

1769	1773

1770 aesdec, 2, 0x66de, None, 1, CpuAVX\|CpuAES, Modrm\|Vex\|VexOpcode=1\|VexVVVV=1\|VexW= 1\|IgnoreSize\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf\|SSE2AVX, { Xmmword \|Unspecified\|BaseIndex\|Disp8\|Disp16\|Disp32\|Disp32S\|RegXMM, RegXMM }	1774 aesdec, 2, 0x66de, None, 1, CpuAVX\|CpuAES, Modrm\|Vex\|VexOpcode=1\|VexVVVV=1\|VexW= 1\|IgnoreSize\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf\|SSE2AVX, { Xmmword \|Unspecified\|BaseIndex\|Disp8\|Disp16\|Disp32\|Disp32S\|RegXMM, RegXMM }

1771 aesdec, 2, 0x660f38de, None, 3, CpuAES, Modrm\|IgnoreSize\|No_bSuf\|No_wSuf\|No_lSuf \|No_sSuf\|No_qSuf\|No_ldSuf, { Xmmword\|Unspecified\|BaseIndex\|Disp8\|Disp16\|Disp32\|D isp32S\|RegXMM, RegXMM }	1775 aesdec, 2, 0x660f38de, None, 3, CpuAES, Modrm\|IgnoreSize\|No_bSuf\|No_wSuf\|No_lSuf \|No_sSuf\|No_qSuf\|No_ldSuf, { Xmmword\|Unspecified\|BaseIndex\|Disp8\|Disp16\|Disp32\|D isp32S\|RegXMM, RegXMM }

1772 aesdeclast, 2, 0x66df, None, 1, CpuAVX\|CpuAES, Modrm\|Vex\|VexOpcode=1\|VexVVVV=1\|V exW=1\|IgnoreSize\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf\|SSE2AVX, { Xmm word\|Unspecified\|BaseIndex\|Disp8\|Disp16\|Disp32\|Disp32S\|RegXMM, RegXMM }	1776 aesdeclast, 2, 0x66df, None, 1, CpuAVX\|CpuAES, Modrm\|Vex\|VexOpcode=1\|VexVVVV=1\|V exW=1\|IgnoreSize\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf\|SSE2AVX, { Xmm word\|Unspecified\|BaseIndex\|Disp8\|Disp16\|Disp32\|Disp32S\|RegXMM, RegXMM }

1773 aesdeclast, 2, 0x660f38df, None, 3, CpuAES, Modrm\|IgnoreSize\|No_bSuf\|No_wSuf\|No_ lSuf\|No_sSuf\|No_qSuf\|No_ldSuf, { Xmmword\|Unspecified\|BaseIndex\|Disp8\|Disp16\|Disp 32\|Disp32S\|RegXMM, RegXMM }	1777 aesdeclast, 2, 0x660f38df, None, 3, CpuAES, Modrm\|IgnoreSize\|No_bSuf\|No_wSuf\|No_ lSuf\|No_sSuf\|No_qSuf\|No_ldSuf, { Xmmword\|Unspecified\|BaseIndex\|Disp8\|Disp16\|Disp 32\|Disp32S\|RegXMM, RegXMM }

1774 aesenc, 2, 0x66dc, None, 1, CpuAVX\|CpuAES, Modrm\|Vex\|VexOpcode=1\|VexVVVV=1\|VexW= 1\|IgnoreSize\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf\|SSE2AVX, { Xmmword \|Unspecified\|BaseIndex\|Disp8\|Disp16\|Disp32\|Disp32S\|RegXMM, RegXMM }	1778 aesenc, 2, 0x66dc, None, 1, CpuAVX\|CpuAES, Modrm\|Vex\|VexOpcode=1\|VexVVVV=1\|VexW= 1\|IgnoreSize\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf\|SSE2AVX, { Xmmword \|Unspecified\|BaseIndex\|Disp8\|Disp16\|Disp32\|Disp32S\|RegXMM, RegXMM }

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2680 vfnmsub231pd, 3, 0x66be, None, 1, CpuFMA, Modrm\|Vex=2\|VexOpcode=1\|VexVVVV=1\|VexW =2\|IgnoreSize\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf, { Ymmword\|Unspec ified\|BaseIndex\|Disp8\|Disp16\|Disp32\|Disp32S\|RegYMM, RegYMM, RegYMM }	2684 vfnmsub231pd, 3, 0x66be, None, 1, CpuFMA, Modrm\|Vex=2\|VexOpcode=1\|VexVVVV=1\|VexW =2\|IgnoreSize\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf, { Ymmword\|Unspec ified\|BaseIndex\|Disp8\|Disp16\|Disp32\|Disp32S\|RegYMM, RegYMM, RegYMM }

2681 vfnmsub231ps, 3, 0x66be, None, 1, CpuFMA, Modrm\|Vex\|VexOpcode=1\|VexVVVV=1\|VexW=1 \|IgnoreSize\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf, { Xmmword\|Unspecif ied\|BaseIndex\|Disp8\|Disp16\|Disp32\|Disp32S\|RegXMM, RegXMM, RegXMM }	2685 vfnmsub231ps, 3, 0x66be, None, 1, CpuFMA, Modrm\|Vex\|VexOpcode=1\|VexVVVV=1\|VexW=1 \|IgnoreSize\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf, { Xmmword\|Unspecif ied\|BaseIndex\|Disp8\|Disp16\|Disp32\|Disp32S\|RegXMM, RegXMM, RegXMM }

2682 vfnmsub231ps, 3, 0x66be, None, 1, CpuFMA, Modrm\|Vex=2\|VexOpcode=1\|VexVVVV=1\|VexW =1\|IgnoreSize\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf, { Ymmword\|Unspec ified\|BaseIndex\|Disp8\|Disp16\|Disp32\|Disp32S\|RegYMM, RegYMM, RegYMM }	2686 vfnmsub231ps, 3, 0x66be, None, 1, CpuFMA, Modrm\|Vex=2\|VexOpcode=1\|VexVVVV=1\|VexW =1\|IgnoreSize\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf, { Ymmword\|Unspec ified\|BaseIndex\|Disp8\|Disp16\|Disp32\|Disp32S\|RegYMM, RegYMM, RegYMM }

2683 vfnmsub132sd, 3, 0x669f, None, 1, CpuFMA, Modrm\|Vex=3\|VexOpcode=1\|VexVVVV=1\|VexW =2\|IgnoreSize\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf, { Qword\|Unspecif ied\|BaseIndex\|Disp8\|Disp16\|Disp32\|Disp32S\|RegXMM, RegXMM, RegXMM }	2687 vfnmsub132sd, 3, 0x669f, None, 1, CpuFMA, Modrm\|Vex=3\|VexOpcode=1\|VexVVVV=1\|VexW =2\|IgnoreSize\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf, { Qword\|Unspecif ied\|BaseIndex\|Disp8\|Disp16\|Disp32\|Disp32S\|RegXMM, RegXMM, RegXMM }

2684 vfnmsub132ss, 3, 0x669f, None, 1, CpuFMA, Modrm\|Vex=3\|VexOpcode=1\|VexVVVV=1\|VexW =1\|IgnoreSize\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf, { Dword\|Unspecif ied\|BaseIndex\|Disp8\|Disp16\|Disp32\|Disp32S\|RegXMM, RegXMM, RegXMM }	2688 vfnmsub132ss, 3, 0x669f, None, 1, CpuFMA, Modrm\|Vex=3\|VexOpcode=1\|VexVVVV=1\|VexW =1\|IgnoreSize\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf, { Dword\|Unspecif ied\|BaseIndex\|Disp8\|Disp16\|Disp32\|Disp32S\|RegXMM, RegXMM, RegXMM }

2685 vfnmsub213sd, 3, 0x66af, None, 1, CpuFMA, Modrm\|Vex=3\|VexOpcode=1\|VexVVVV=1\|VexW =2\|IgnoreSize\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf, { Qword\|Unspecif ied\|BaseIndex\|Disp8\|Disp16\|Disp32\|Disp32S\|RegXMM, RegXMM, RegXMM }	2689 vfnmsub213sd, 3, 0x66af, None, 1, CpuFMA, Modrm\|Vex=3\|VexOpcode=1\|VexVVVV=1\|VexW =2\|IgnoreSize\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf, { Qword\|Unspecif ied\|BaseIndex\|Disp8\|Disp16\|Disp32\|Disp32S\|RegXMM, RegXMM, RegXMM }

2686 vfnmsub213ss, 3, 0x66af, None, 1, CpuFMA, Modrm\|Vex=3\|VexOpcode=1\|VexVVVV=1\|VexW =1\|IgnoreSize\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf, { Dword\|Unspecif ied\|BaseIndex\|Disp8\|Disp16\|Disp32\|Disp32S\|RegXMM, RegXMM, RegXMM }	2690 vfnmsub213ss, 3, 0x66af, None, 1, CpuFMA, Modrm\|Vex=3\|VexOpcode=1\|VexVVVV=1\|VexW =1\|IgnoreSize\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf, { Dword\|Unspecif ied\|BaseIndex\|Disp8\|Disp16\|Disp32\|Disp32S\|RegXMM, RegXMM, RegXMM }

2687 vfnmsub231sd, 3, 0x66bf, None, 1, CpuFMA, Modrm\|Vex=3\|VexOpcode=1\|VexVVVV=1\|VexW =2\|IgnoreSize\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf, { Qword\|Unspecif ied\|BaseIndex\|Disp8\|Disp16\|Disp32\|Disp32S\|RegXMM, RegXMM, RegXMM }	2691 vfnmsub231sd, 3, 0x66bf, None, 1, CpuFMA, Modrm\|Vex=3\|VexOpcode=1\|VexVVVV=1\|VexW =2\|IgnoreSize\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf, { Qword\|Unspecif ied\|BaseIndex\|Disp8\|Disp16\|Disp32\|Disp32S\|RegXMM, RegXMM, RegXMM }

2688 vfnmsub231ss, 3, 0x66bf, None, 1, CpuFMA, Modrm\|Vex=3\|VexOpcode=1\|VexVVVV=1\|VexW =1\|IgnoreSize\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf, { Dword\|Unspecif ied\|BaseIndex\|Disp8\|Disp16\|Disp32\|Disp32S\|RegXMM, RegXMM, RegXMM }	2692 vfnmsub231ss, 3, 0x66bf, None, 1, CpuFMA, Modrm\|Vex=3\|VexOpcode=1\|VexVVVV=1\|VexW =1\|IgnoreSize\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf, { Dword\|Unspecif ied\|BaseIndex\|Disp8\|Disp16\|Disp32\|Disp32S\|RegXMM, RegXMM, RegXMM }

2689	2693

	2694 // HLE prefixes

	2695

	2696 xacquire, 0, 0xf2, None, 1, CpuHLE, No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_l dSuf\|IsPrefix, { 0 }

	2697 xrelease, 0, 0xf3, None, 1, CpuHLE, No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_l dSuf\|IsPrefix, { 0 }

	2698

	2699 // RTM instructions

	2700 xabort, 1, 0xc6f8, None, 2, CpuRTM, No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_l dSuf, { Imm8 }

	2701 xbegin, 1, 0xc7f8, None, 2, CpuRTM, JumpDword\|DefaultSize\|No_bSuf\|No_wSuf\|No_lS uf\|No_sSuf\|No_qSuf\|No_ldSuf\|NoRex64, { Disp16\|Disp32 }

	2702 xend, 0, 0xf01d5, None, 3, CpuRTM, No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_ld Suf, { 0 }

	2703 xtest, 0, 0xf01d6, None, 3, CpuHLE\|CpuRTM, No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qS uf\|No_ldSuf, { 0 }

	2704

2690 // BMI2 instructions.	2705 // BMI2 instructions.

2691 bzhi, 3, 0xf5, None, 1, CpuBMI2, Modrm\|CheckRegSize\|Vex=3\|VexOpcode=1\|VexVVVV=1\| No_bSuf\|No_wSuf\|No_sSuf\|No_ldSuf, { Reg32\|Reg64, Reg32\|Reg64\|Dword\|Qword\|Unspeci fied\|BaseIndex\|Disp8\|Disp16\|Disp32\|Disp32S, Reg32\|Reg64 }	2706 bzhi, 3, 0xf5, None, 1, CpuBMI2, Modrm\|CheckRegSize\|Vex=3\|VexOpcode=1\|VexVVVV=1\| No_bSuf\|No_wSuf\|No_sSuf\|No_ldSuf, { Reg32\|Reg64, Reg32\|Reg64\|Dword\|Qword\|Unspeci fied\|BaseIndex\|Disp8\|Disp16\|Disp32\|Disp32S, Reg32\|Reg64 }

2692 mulx, 3, 0xf2f6, None, 1, CpuBMI2, Modrm\|CheckRegSize\|Vex=3\|VexOpcode=1\|VexVVVV= 1\|No_bSuf\|No_wSuf\|No_sSuf\|No_ldSuf, { Reg32\|Reg64\|Dword\|Qword\|Unspecified\|BaseIn dex\|Disp8\|Disp16\|Disp32\|Disp32S, Reg32\|Reg64, Reg32\|Reg64 }	2707 mulx, 3, 0xf2f6, None, 1, CpuBMI2, Modrm\|CheckRegSize\|Vex=3\|VexOpcode=1\|VexVVVV= 1\|No_bSuf\|No_wSuf\|No_sSuf\|No_ldSuf, { Reg32\|Reg64\|Dword\|Qword\|Unspecified\|BaseIn dex\|Disp8\|Disp16\|Disp32\|Disp32S, Reg32\|Reg64, Reg32\|Reg64 }

2693 pdep, 3, 0xf2f5, None, 1, CpuBMI2, Modrm\|CheckRegSize\|Vex=3\|VexOpcode=1\|VexVVVV= 1\|No_bSuf\|No_wSuf\|No_sSuf\|No_ldSuf, { Reg32\|Reg64\|Dword\|Qword\|Unspecified\|BaseIn dex\|Disp8\|Disp16\|Disp32\|Disp32S, Reg32\|Reg64, Reg32\|Reg64 }	2708 pdep, 3, 0xf2f5, None, 1, CpuBMI2, Modrm\|CheckRegSize\|Vex=3\|VexOpcode=1\|VexVVVV= 1\|No_bSuf\|No_wSuf\|No_sSuf\|No_ldSuf, { Reg32\|Reg64\|Dword\|Qword\|Unspecified\|BaseIn dex\|Disp8\|Disp16\|Disp32\|Disp32S, Reg32\|Reg64, Reg32\|Reg64 }

2694 pext, 3, 0xf3f5, None, 1, CpuBMI2, Modrm\|CheckRegSize\|Vex=3\|VexOpcode=1\|VexVVVV= 1\|No_bSuf\|No_wSuf\|No_sSuf\|No_ldSuf, { Reg32\|Reg64\|Dword\|Qword\|Unspecified\|BaseIn dex\|Disp8\|Disp16\|Disp32\|Disp32S, Reg32\|Reg64, Reg32\|Reg64 }	2709 pext, 3, 0xf3f5, None, 1, CpuBMI2, Modrm\|CheckRegSize\|Vex=3\|VexOpcode=1\|VexVVVV= 1\|No_bSuf\|No_wSuf\|No_sSuf\|No_ldSuf, { Reg32\|Reg64\|Dword\|Qword\|Unspecified\|BaseIn dex\|Disp8\|Disp16\|Disp32\|Disp32S, Reg32\|Reg64, Reg32\|Reg64 }

2695 rorx, 3, 0xf2f0, None, 1, CpuBMI2, Modrm\|CheckRegSize\|Vex=3\|VexOpcode=2\|VexVVVV= 0\|No_bSuf\|No_wSuf\|No_sSuf\|No_ldSuf, { Imm8, Reg32\|Reg64\|Dword\|Qword\|Unspecified\| BaseIndex\|Disp8\|Disp16\|Disp32\|Disp32S, Reg32\|Reg64 }	2710 rorx, 3, 0xf2f0, None, 1, CpuBMI2, Modrm\|CheckRegSize\|Vex=3\|VexOpcode=2\|VexVVVV= 0\|No_bSuf\|No_wSuf\|No_sSuf\|No_ldSuf, { Imm8, Reg32\|Reg64\|Dword\|Qword\|Unspecified\| BaseIndex\|Disp8\|Disp16\|Disp32\|Disp32S, Reg32\|Reg64 }

2696 sarx, 3, 0xf3f7, None, 1, CpuBMI2, Modrm\|CheckRegSize\|Vex=3\|VexOpcode=1\|VexVVVV= 1\|No_bSuf\|No_wSuf\|No_sSuf\|No_ldSuf, { Reg32\|Reg64, Reg32\|Reg64\|Dword\|Qword\|Unspe cified\|BaseIndex\|Disp8\|Disp16\|Disp32\|Disp32S, Reg32\|Reg64 }	2711 sarx, 3, 0xf3f7, None, 1, CpuBMI2, Modrm\|CheckRegSize\|Vex=3\|VexOpcode=1\|VexVVVV= 1\|No_bSuf\|No_wSuf\|No_sSuf\|No_ldSuf, { Reg32\|Reg64, Reg32\|Reg64\|Dword\|Qword\|Unspe cified\|BaseIndex\|Disp8\|Disp16\|Disp32\|Disp32S, Reg32\|Reg64 }

2697 shlx, 3, 0x66f7, None, 1, CpuBMI2, Modrm\|CheckRegSize\|Vex=3\|VexOpcode=1\|VexVVVV= 1\|No_bSuf\|No_wSuf\|No_sSuf\|No_ldSuf, { Reg32\|Reg64, Reg32\|Reg64\|Dword\|Qword\|Unspe cified\|BaseIndex\|Disp8\|Disp16\|Disp32\|Disp32S, Reg32\|Reg64 }	2712 shlx, 3, 0x66f7, None, 1, CpuBMI2, Modrm\|CheckRegSize\|Vex=3\|VexOpcode=1\|VexVVVV= 1\|No_bSuf\|No_wSuf\|No_sSuf\|No_ldSuf, { Reg32\|Reg64, Reg32\|Reg64\|Dword\|Qword\|Unspe cified\|BaseIndex\|Disp8\|Disp16\|Disp32\|Disp32S, Reg32\|Reg64 }

2698 shrx, 3, 0xf2f7, None, 1, CpuBMI2, Modrm\|CheckRegSize\|Vex=3\|VexOpcode=1\|VexVVVV= 1\|No_bSuf\|No_wSuf\|No_sSuf\|No_ldSuf, { Reg32\|Reg64, Reg32\|Reg64\|Dword\|Qword\|Unspe cified\|BaseIndex\|Disp8\|Disp16\|Disp32\|Disp32S, Reg32\|Reg64 }	2713 shrx, 3, 0xf2f7, None, 1, CpuBMI2, Modrm\|CheckRegSize\|Vex=3\|VexOpcode=1\|VexVVVV= 1\|No_bSuf\|No_wSuf\|No_sSuf\|No_ldSuf, { Reg32\|Reg64, Reg32\|Reg64\|Dword\|Qword\|Unspe cified\|BaseIndex\|Disp8\|Disp16\|Disp32\|Disp32S, Reg32\|Reg64 }

2699	2714

(...skipping 244 matching lines...) Expand 10 before \| Expand all \| Expand 10 after Loading...
2944 blcmsk, 2, 0x02, 0x1, 1, CpuTBM, Modrm\|CheckRegSize\|Vex=3\|VexOpcode=4\|VexVVVV= 2\|No_bSuf\|No_wSuf\|No_sSuf\|No_ldSuf, { Reg32\|Reg64\|Dword\|Qword\|Disp8\|Disp16\|Disp3 2\|Disp32S\|Unspecified\|BaseIndex, Reg32\|Reg64 }	2959 blcmsk, 2, 0x02, 0x1, 1, CpuTBM, Modrm\|CheckRegSize\|Vex=3\|VexOpcode=4\|VexVVVV= 2\|No_bSuf\|No_wSuf\|No_sSuf\|No_ldSuf, { Reg32\|Reg64\|Dword\|Qword\|Disp8\|Disp16\|Disp3 2\|Disp32S\|Unspecified\|BaseIndex, Reg32\|Reg64 }

2945 blcs, 2, 0x01, 0x3, 1, CpuTBM, Modrm\|CheckRegSize\|Vex=3\|VexOpcode=4\|VexVVVV=2 \|No_bSuf\|No_wSuf\|No_sSuf\|No_ldSuf, { Reg32\|Reg64\|Dword\|Qword\|Disp8\|Disp16\|Disp32 \|Disp32S\|Unspecified\|BaseIndex, Reg32\|Reg64 }	2960 blcs, 2, 0x01, 0x3, 1, CpuTBM, Modrm\|CheckRegSize\|Vex=3\|VexOpcode=4\|VexVVVV=2 \|No_bSuf\|No_wSuf\|No_sSuf\|No_ldSuf, { Reg32\|Reg64\|Dword\|Qword\|Disp8\|Disp16\|Disp32 \|Disp32S\|Unspecified\|BaseIndex, Reg32\|Reg64 }

2946 blsfill, 2, 0x01, 0x2, 1, CpuTBM, Modrm\|CheckRegSize\|Vex=3\|VexOpcode=4\|VexVVVV =2\|No_bSuf\|No_wSuf\|No_sSuf\|No_ldSuf, { Reg32\|Reg64\|Dword\|Qword\|Disp8\|Disp16\|Disp 32\|Disp32S\|Unspecified\|BaseIndex, Reg32\|Reg64 }	2961 blsfill, 2, 0x01, 0x2, 1, CpuTBM, Modrm\|CheckRegSize\|Vex=3\|VexOpcode=4\|VexVVVV =2\|No_bSuf\|No_wSuf\|No_sSuf\|No_ldSuf, { Reg32\|Reg64\|Dword\|Qword\|Disp8\|Disp16\|Disp 32\|Disp32S\|Unspecified\|BaseIndex, Reg32\|Reg64 }

2947 blsic, 2, 0x01, 0x6, 1, CpuTBM, Modrm\|CheckRegSize\|Vex=3\|VexOpcode=4\|VexVVVV= 2\|No_bSuf\|No_wSuf\|No_sSuf\|No_ldSuf, { Reg32\|Reg64\|Dword\|Qword\|Disp8\|Disp16\|Disp3 2\|Disp32S\|Unspecified\|BaseIndex, Reg32\|Reg64 }	2962 blsic, 2, 0x01, 0x6, 1, CpuTBM, Modrm\|CheckRegSize\|Vex=3\|VexOpcode=4\|VexVVVV= 2\|No_bSuf\|No_wSuf\|No_sSuf\|No_ldSuf, { Reg32\|Reg64\|Dword\|Qword\|Disp8\|Disp16\|Disp3 2\|Disp32S\|Unspecified\|BaseIndex, Reg32\|Reg64 }

2948 t1mskc, 2, 0x01, 0x7, 1, CpuTBM, Modrm\|CheckRegSize\|Vex=3\|VexOpcode=4\|VexVVVV= 2\|No_bSuf\|No_wSuf\|No_sSuf\|No_ldSuf, { Reg32\|Reg64\|Dword\|Qword\|Disp8\|Disp16\|Disp3 2\|Disp32S\|Unspecified\|BaseIndex, Reg32\|Reg64 }	2963 t1mskc, 2, 0x01, 0x7, 1, CpuTBM, Modrm\|CheckRegSize\|Vex=3\|VexOpcode=4\|VexVVVV= 2\|No_bSuf\|No_wSuf\|No_sSuf\|No_ldSuf, { Reg32\|Reg64\|Dword\|Qword\|Disp8\|Disp16\|Disp3 2\|Disp32S\|Unspecified\|BaseIndex, Reg32\|Reg64 }

2949 tzmsk, 2, 0x01, 0x4, 1, CpuTBM, Modrm\|CheckRegSize\|Vex=3\|VexOpcode=4\|VexVVVV= 2\|No_bSuf\|No_wSuf\|No_sSuf\|No_ldSuf, { Reg32\|Reg64\|Dword\|Qword\|Disp8\|Disp16\|Disp3 2\|Disp32S\|Unspecified\|BaseIndex, Reg32\|Reg64 }	2964 tzmsk, 2, 0x01, 0x4, 1, CpuTBM, Modrm\|CheckRegSize\|Vex=3\|VexOpcode=4\|VexVVVV= 2\|No_bSuf\|No_wSuf\|No_sSuf\|No_ldSuf, { Reg32\|Reg64\|Dword\|Qword\|Disp8\|Disp16\|Disp3 2\|Disp32S\|Unspecified\|BaseIndex, Reg32\|Reg64 }

2950	2965

2951 // AMD 3DNow! instructions.	2966 // AMD 3DNow! instructions.

2952	2967

2953 prefetch, 1, 0xf0d, 0x0, 2, Cpu3dnow, Modrm\|IgnoreSize\|No_bSuf\|No_wSuf\|No_lSuf\|N o_sSuf\|No_qSuf\|No_ldSuf, { Byte\|Unspecified\|BaseIndex\|Disp8\|Disp16\|Disp32\|Disp32 S }	2968 prefetch, 1, 0xf0d, 0x0, 2, Cpu3dnow, Modrm\|IgnoreSize\|No_bSuf\|No_wSuf\|No_lSuf\|N o_sSuf\|No_qSuf\|No_ldSuf, { Byte\|Unspecified\|BaseIndex\|Disp8\|Disp16\|Disp32\|Disp32 S }

2954 prefetchw, 1, 0xf0d, 0x1, 2, Cpu3dnow, Modrm\|IgnoreSize\|No_bSuf\|No_wSuf\|No_lSuf\| No_sSuf\|No_qSuf\|No_ldSuf, { Byte\|Unspecified\|BaseIndex\|Disp8\|Disp16\|Disp32\|Disp3 2S }	2969 prefetchw, 1, 0xf0d, 0x1, 2, Cpu3dnow\|CpuPRFCHW, Modrm\|IgnoreSize\|No_bSuf\|No_wSu f\|No_lSuf\|No_sSuf\|No_qSuf\|No_ldSuf, { Byte\|Unspecified\|BaseIndex\|Disp8\|Disp16\|Di sp32\|Disp32S }

2955 femms, 0, 0xf0e, None, 2, Cpu3dnow, No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_l dSuf, { 0 }	2970 femms, 0, 0xf0e, None, 2, Cpu3dnow, No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|No_l dSuf, { 0 }

2956 pavgusb, 2, 0xf0f, 0xbf, 2, Cpu3dnow, Modrm\|IgnoreSize\|No_bSuf\|No_wSuf\|No_lSuf\|N o_sSuf\|No_qSuf\|No_ldSuf\|ImmExt, { Qword\|Unspecified\|BaseIndex\|Disp8\|Disp16\|Disp3 2\|Disp32S\|RegMMX, RegMMX }	2971 pavgusb, 2, 0xf0f, 0xbf, 2, Cpu3dnow, Modrm\|IgnoreSize\|No_bSuf\|No_wSuf\|No_lSuf\|N o_sSuf\|No_qSuf\|No_ldSuf\|ImmExt, { Qword\|Unspecified\|BaseIndex\|Disp8\|Disp16\|Disp3 2\|Disp32S\|RegMMX, RegMMX }

2957 pf2id, 2, 0xf0f, 0x1d, 2, Cpu3dnow, Modrm\|IgnoreSize\|No_bSuf\|No_wSuf\|No_lSuf\|No_ sSuf\|No_qSuf\|No_ldSuf\|ImmExt, { Qword\|Unspecified\|BaseIndex\|Disp8\|Disp16\|Disp32\| Disp32S\|RegMMX, RegMMX }	2972 pf2id, 2, 0xf0f, 0x1d, 2, Cpu3dnow, Modrm\|IgnoreSize\|No_bSuf\|No_wSuf\|No_lSuf\|No_ sSuf\|No_qSuf\|No_ldSuf\|ImmExt, { Qword\|Unspecified\|BaseIndex\|Disp8\|Disp16\|Disp32\| Disp32S\|RegMMX, RegMMX }

2958 pf2iw, 2, 0xf0f, 0x1c, 2, Cpu3dnowA, Modrm\|IgnoreSize\|No_bSuf\|No_wSuf\|No_lSuf\|No _sSuf\|No_qSuf\|No_ldSuf\|ImmExt, { Qword\|Unspecified\|BaseIndex\|Disp8\|Disp16\|Disp32 \|Disp32S\|RegMMX, RegMMX }	2973 pf2iw, 2, 0xf0f, 0x1c, 2, Cpu3dnowA, Modrm\|IgnoreSize\|No_bSuf\|No_wSuf\|No_lSuf\|No _sSuf\|No_qSuf\|No_ldSuf\|ImmExt, { Qword\|Unspecified\|BaseIndex\|Disp8\|Disp16\|Disp32 \|Disp32S\|RegMMX, RegMMX }

2959 pfacc, 2, 0xf0f, 0xae, 2, Cpu3dnow, Modrm\|IgnoreSize\|No_bSuf\|No_wSuf\|No_lSuf\|No_ sSuf\|No_qSuf\|No_ldSuf\|ImmExt, { Qword\|Unspecified\|BaseIndex\|Disp8\|Disp16\|Disp32\| Disp32S\|RegMMX, RegMMX }	2974 pfacc, 2, 0xf0f, 0xae, 2, Cpu3dnow, Modrm\|IgnoreSize\|No_bSuf\|No_wSuf\|No_lSuf\|No_ sSuf\|No_qSuf\|No_ldSuf\|ImmExt, { Qword\|Unspecified\|BaseIndex\|Disp8\|Disp16\|Disp32\| Disp32S\|RegMMX, RegMMX }

2960 pfadd, 2, 0xf0f, 0x9e, 2, Cpu3dnow, Modrm\|IgnoreSize\|No_bSuf\|No_wSuf\|No_lSuf\|No_ sSuf\|No_qSuf\|No_ldSuf\|ImmExt, { Qword\|Unspecified\|BaseIndex\|Disp8\|Disp16\|Disp32\| Disp32S\|RegMMX, RegMMX }	2975 pfadd, 2, 0xf0f, 0x9e, 2, Cpu3dnow, Modrm\|IgnoreSize\|No_bSuf\|No_wSuf\|No_lSuf\|No_ sSuf\|No_qSuf\|No_ldSuf\|ImmExt, { Qword\|Unspecified\|BaseIndex\|Disp8\|Disp16\|Disp32\| Disp32S\|RegMMX, RegMMX }

2961 pfcmpeq, 2, 0xf0f, 0xb0, 2, Cpu3dnow, Modrm\|IgnoreSize\|No_bSuf\|No_wSuf\|No_lSuf\|N o_sSuf\|No_qSuf\|No_ldSuf\|ImmExt, { Qword\|Unspecified\|BaseIndex\|Disp8\|Disp16\|Disp3 2\|Disp32S\|RegMMX, RegMMX }	2976 pfcmpeq, 2, 0xf0f, 0xb0, 2, Cpu3dnow, Modrm\|IgnoreSize\|No_bSuf\|No_wSuf\|No_lSuf\|N o_sSuf\|No_qSuf\|No_ldSuf\|ImmExt, { Qword\|Unspecified\|BaseIndex\|Disp8\|Disp16\|Disp3 2\|Disp32S\|RegMMX, RegMMX }

2962 pfcmpge, 2, 0xf0f, 0x90, 2, Cpu3dnow, Modrm\|IgnoreSize\|No_bSuf\|No_wSuf\|No_lSuf\|N o_sSuf\|No_qSuf\|No_ldSuf\|ImmExt, { Qword\|Unspecified\|BaseIndex\|Disp8\|Disp16\|Disp3 2\|Disp32S\|RegMMX, RegMMX }	2977 pfcmpge, 2, 0xf0f, 0x90, 2, Cpu3dnow, Modrm\|IgnoreSize\|No_bSuf\|No_wSuf\|No_lSuf\|N o_sSuf\|No_qSuf\|No_ldSuf\|ImmExt, { Qword\|Unspecified\|BaseIndex\|Disp8\|Disp16\|Disp3 2\|Disp32S\|RegMMX, RegMMX }

2963 pfcmpgt, 2, 0xf0f, 0xa0, 2, Cpu3dnow, Modrm\|IgnoreSize\|No_bSuf\|No_wSuf\|No_lSuf\|N o_sSuf\|No_qSuf\|No_ldSuf\|ImmExt, { Qword\|Unspecified\|BaseIndex\|Disp8\|Disp16\|Disp3 2\|Disp32S\|RegMMX, RegMMX }	2978 pfcmpgt, 2, 0xf0f, 0xa0, 2, Cpu3dnow, Modrm\|IgnoreSize\|No_bSuf\|No_wSuf\|No_lSuf\|N o_sSuf\|No_qSuf\|No_ldSuf\|ImmExt, { Qword\|Unspecified\|BaseIndex\|Disp8\|Disp16\|Disp3 2\|Disp32S\|RegMMX, RegMMX }

2964 pfmax, 2, 0xf0f, 0xa4, 2, Cpu3dnow, Modrm\|IgnoreSize\|No_bSuf\|No_wSuf\|No_lSuf\|No_ sSuf\|No_qSuf\|No_ldSuf\|ImmExt, { Qword\|Unspecified\|BaseIndex\|Disp8\|Disp16\|Disp32\| Disp32S\|RegMMX, RegMMX }	2979 pfmax, 2, 0xf0f, 0xa4, 2, Cpu3dnow, Modrm\|IgnoreSize\|No_bSuf\|No_wSuf\|No_lSuf\|No_ sSuf\|No_qSuf\|No_ldSuf\|ImmExt, { Qword\|Unspecified\|BaseIndex\|Disp8\|Disp16\|Disp32\| Disp32S\|RegMMX, RegMMX }

(...skipping 48 matching lines...) Expand 10 before \| Expand all \| Expand 10 after Loading...
3013 extrq, 3, 0x660f78, 0x0, 2, CpuSSE4a, Modrm\|IgnoreSize\|No_bSuf\|No_wSuf\|No_lSuf\|N o_sSuf\|No_qSuf\|No_ldSuf, { Imm8, Imm8, RegXMM }	3028 extrq, 3, 0x660f78, 0x0, 2, CpuSSE4a, Modrm\|IgnoreSize\|No_bSuf\|No_wSuf\|No_lSuf\|N o_sSuf\|No_qSuf\|No_ldSuf, { Imm8, Imm8, RegXMM }

3014 extrq, 2, 0x660f79, None, 2, CpuSSE4a, Modrm\|IgnoreSize\|No_bSuf\|No_wSuf\|No_lSuf\| No_sSuf\|No_qSuf\|No_ldSuf, { RegXMM, RegXMM }	3029 extrq, 2, 0x660f79, None, 2, CpuSSE4a, Modrm\|IgnoreSize\|No_bSuf\|No_wSuf\|No_lSuf\| No_sSuf\|No_qSuf\|No_ldSuf, { RegXMM, RegXMM }

3015 insertq, 2, 0xf20f79, None, 2, CpuSSE4a, Modrm\|IgnoreSize\|No_bSuf\|No_wSuf\|No_lSu f\|No_sSuf\|No_qSuf\|No_ldSuf, { RegXMM, RegXMM }	3030 insertq, 2, 0xf20f79, None, 2, CpuSSE4a, Modrm\|IgnoreSize\|No_bSuf\|No_wSuf\|No_lSu f\|No_sSuf\|No_qSuf\|No_ldSuf, { RegXMM, RegXMM }

3016 insertq, 4, 0xf20f78, None, 2, CpuSSE4a, Modrm\|IgnoreSize\|No_bSuf\|No_wSuf\|No_lSu f\|No_sSuf\|No_qSuf\|No_ldSuf, { Imm8, Imm8, RegXMM, RegXMM }	3031 insertq, 4, 0xf20f78, None, 2, CpuSSE4a, Modrm\|IgnoreSize\|No_bSuf\|No_wSuf\|No_lSu f\|No_sSuf\|No_qSuf\|No_ldSuf, { Imm8, Imm8, RegXMM, RegXMM }

3017	3032

3018 // ABM instructions	3033 // ABM instructions

3019 popcnt, 2, 0xf30fb8, None, 2, CpuABM\|CpuSSE4_2, Modrm\|CheckRegSize\|No_bSuf\|No_sS uf\|No_ldSuf\|NoAVX, { Reg16\|Reg32\|Reg64\|Word\|Dword\|Qword\|Unspecified\|BaseIndex\|Di sp8\|Disp16\|Disp32\|Disp32S, Reg16\|Reg32\|Reg64 }	3034 popcnt, 2, 0xf30fb8, None, 2, CpuABM\|CpuSSE4_2, Modrm\|CheckRegSize\|No_bSuf\|No_sS uf\|No_ldSuf\|NoAVX, { Reg16\|Reg32\|Reg64\|Word\|Dword\|Qword\|Unspecified\|BaseIndex\|Di sp8\|Disp16\|Disp32\|Disp32S, Reg16\|Reg32\|Reg64 }

3020 lzcnt, 2, 0xf30fbd, None, 2, CpuABM\|CpuLZCNT, Modrm\|CheckRegSize\|No_bSuf\|No_sSuf \|No_ldSuf, { Reg16\|Reg32\|Reg64\|Word\|Dword\|Qword\|Unspecified\|BaseIndex\|Disp8\|Disp 16\|Disp32\|Disp32S, Reg16\|Reg32\|Reg64 }	3035 lzcnt, 2, 0xf30fbd, None, 2, CpuABM\|CpuLZCNT, Modrm\|CheckRegSize\|No_bSuf\|No_sSuf \|No_ldSuf, { Reg16\|Reg32\|Reg64\|Word\|Dword\|Qword\|Unspecified\|BaseIndex\|Disp8\|Disp 16\|Disp32\|Disp32S, Reg16\|Reg32\|Reg64 }

3021	3036

3022 // VIA PadLock extensions.	3037 // VIA PadLock extensions.

3023 xstore-rng, 0, 0xfa7, 0xc0, 2, CpuPadLock, No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qS uf\|No_ldSuf\|IsString\|ImmExt, { 0 }	3038 xstore-rng, 0, 0xfa7, 0xc0, 2, CpuPadLock, No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qS uf\|No_ldSuf\|IsString\|RepPrefixOk\|ImmExt, { 0 }

3024 xcrypt-ecb, 0, 0xf30fa7, 0xc8, 2, CpuPadLock, No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No _qSuf\|No_ldSuf\|IsString\|ImmExt, { 0 }	3039 xcrypt-ecb, 0, 0xf30fa7, 0xc8, 2, CpuPadLock, No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No _qSuf\|No_ldSuf\|IsString\|RepPrefixOk\|ImmExt, { 0 }

3025 xcrypt-cbc, 0, 0xf30fa7, 0xd0, 2, CpuPadLock, No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No _qSuf\|No_ldSuf\|IsString\|ImmExt, { 0 }	3040 xcrypt-cbc, 0, 0xf30fa7, 0xd0, 2, CpuPadLock, No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No _qSuf\|No_ldSuf\|IsString\|RepPrefixOk\|ImmExt, { 0 }

3026 xcrypt-ctr, 0, 0xf30fa7, 0xd8, 2, CpuPadLock, No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No _qSuf\|No_ldSuf\|IsString\|ImmExt, { 0 }	3041 xcrypt-ctr, 0, 0xf30fa7, 0xd8, 2, CpuPadLock, No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No _qSuf\|No_ldSuf\|IsString\|RepPrefixOk\|ImmExt, { 0 }

3027 xcrypt-cfb, 0, 0xf30fa7, 0xe0, 2, CpuPadLock, No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No _qSuf\|No_ldSuf\|IsString\|ImmExt, { 0 }	3042 xcrypt-cfb, 0, 0xf30fa7, 0xe0, 2, CpuPadLock, No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No _qSuf\|No_ldSuf\|IsString\|RepPrefixOk\|ImmExt, { 0 }

3028 xcrypt-ofb, 0, 0xf30fa7, 0xe8, 2, CpuPadLock, No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No _qSuf\|No_ldSuf\|IsString\|ImmExt, { 0 }	3043 xcrypt-ofb, 0, 0xf30fa7, 0xe8, 2, CpuPadLock, No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No _qSuf\|No_ldSuf\|IsString\|RepPrefixOk\|ImmExt, { 0 }

3029 montmul, 0, 0xf30fa6, 0xc0, 2, CpuPadLock, No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qS uf\|No_ldSuf\|IsString\|ImmExt, { 0 }	3044 montmul, 0, 0xf30fa6, 0xc0, 2, CpuPadLock, No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qS uf\|No_ldSuf\|IsString\|RepPrefixOk\|ImmExt, { 0 }

3030 xsha1, 0, 0xf30fa6, 0xc8, 2, CpuPadLock, No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf \|No_ldSuf\|IsString\|ImmExt, { 0 }	3045 xsha1, 0, 0xf30fa6, 0xc8, 2, CpuPadLock, No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf \|No_ldSuf\|IsString\|RepPrefixOk\|ImmExt, { 0 }

3031 xsha256, 0, 0xf30fa6, 0xd0, 2, CpuPadLock, No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qS uf\|No_ldSuf\|IsString\|ImmExt, { 0 }	3046 xsha256, 0, 0xf30fa6, 0xd0, 2, CpuPadLock, No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qS uf\|No_ldSuf\|IsString\|RepPrefixOk\|ImmExt, { 0 }

3032 // Aliases without hyphens.	3047 // Aliases without hyphens.

3033 xstorerng, 0, 0xfa7, 0xc0, 2, CpuPadLock, No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSu f\|No_ldSuf\|IsString\|ImmExt, { 0 }	3048 xstorerng, 0, 0xfa7, 0xc0, 2, CpuPadLock, No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSu f\|No_ldSuf\|IsString\|RepPrefixOk\|ImmExt, { 0 }

3034 xcryptecb, 0, 0xf30fa7, 0xc8, 2, CpuPadLock, No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_ qSuf\|No_ldSuf\|IsString\|ImmExt, { 0 }	3049 xcryptecb, 0, 0xf30fa7, 0xc8, 2, CpuPadLock, No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_ qSuf\|No_ldSuf\|IsString\|RepPrefixOk\|ImmExt, { 0 }

3035 xcryptcbc, 0, 0xf30fa7, 0xd0, 2, CpuPadLock, No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_ qSuf\|No_ldSuf\|IsString\|ImmExt, { 0 }	3050 xcryptcbc, 0, 0xf30fa7, 0xd0, 2, CpuPadLock, No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_ qSuf\|No_ldSuf\|IsString\|RepPrefixOk\|ImmExt, { 0 }

3036 xcryptctr, 0, 0xf30fa7, 0xd8, 2, CpuPadLock, No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_ qSuf\|No_ldSuf\|IsString\|ImmExt, { 0 }	3051 xcryptctr, 0, 0xf30fa7, 0xd8, 2, CpuPadLock, No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_ qSuf\|No_ldSuf\|IsString\|RepPrefixOk\|ImmExt, { 0 }

3037 xcryptcfb, 0, 0xf30fa7, 0xe0, 2, CpuPadLock, No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_ qSuf\|No_ldSuf\|IsString\|ImmExt, { 0 }	3052 xcryptcfb, 0, 0xf30fa7, 0xe0, 2, CpuPadLock, No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_ qSuf\|No_ldSuf\|IsString\|RepPrefixOk\|ImmExt, { 0 }

3038 xcryptofb, 0, 0xf30fa7, 0xe8, 2, CpuPadLock, No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_ qSuf\|No_ldSuf\|IsString\|ImmExt, { 0 }	3053 xcryptofb, 0, 0xf30fa7, 0xe8, 2, CpuPadLock, No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_ qSuf\|No_ldSuf\|IsString\|RepPrefixOk\|ImmExt, { 0 }

3039 // Alias for xstore-rng.	3054 // Alias for xstore-rng.

3040 xstore, 0, 0xfa7, 0xc0, 2, CpuPadLock, No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|N o_ldSuf\|IsString\|ImmExt, { 0 }	3055 xstore, 0, 0xfa7, 0xc0, 2, CpuPadLock, No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qSuf\|N o_ldSuf\|IsString\|RepPrefixOk\|ImmExt, { 0 }

	3056

	3057 // Multy-precision Add Carry, rdseed instructions.

	3058 adcx, 2, 0x660f38f6, None, 3, CpuADX, Modrm\|CheckRegSize\|No_bSuf\|No_wSuf\|No_sSuf \|No_ldSuf, { Reg32\|Reg64\|Dword\|Qword\|Unspecified\|BaseIndex\|Disp8\|Disp16\|Disp32\|D isp32S, Reg32\|Reg64 }

	3059 adox, 2, 0xf30f38f6, None, 3, CpuADX, Modrm\|CheckRegSize\|No_bSuf\|No_wSuf\|No_sSuf \|No_ldSuf, { Reg32\|Reg64\|Dword\|Qword\|Unspecified\|BaseIndex\|Disp8\|Disp16\|Disp32\|D isp32S, Reg32\|Reg64 }

	3060 rdseed, 1, 0xfc7, 0x7, 2, CpuRdSeed, Modrm\|No_bSuf\|No_wSuf\|No_lSuf\|No_sSuf\|No_qS uf\|No_ldSuf, { Reg16\|Reg32\|Reg64 }

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