Merge GDB 7.5.1

opcodes/i386-opc.h

 /* Declarations for Intel 80386 opcode table
-   Copyright 2007, 2008, 2009, 2010
+   Copyright 2007, 2008, 2009, 2010, 2012
    Free Software Foundation, Inc.
 
    This file is part of the GNU opcodes library.
 
    This library is free software; you can redistribute it and/or modify
    it under the terms of the GNU General Public License as published by
    the Free Software Foundation; either version 3, or (at your option)
    any later version.
 
    It is distributed in the hope that it will be useful, but WITHOUT
@@ skipping 114 matching lines @@
   /* FSGSBASE Instructions required */
   CpuFSGSBase,
   /* RDRND Instructions required */
   CpuRdRnd,
   /* F16C Instructions required */
   CpuF16C,
   /* Intel BMI2 support required */
   CpuBMI2,
   /* LZCNT support required */
   CpuLZCNT,
+  /* HLE support required */
+  CpuHLE,
+  /* RTM support required */
+  CpuRTM,
   /* INVPCID Instructions required */
   CpuINVPCID,
+  /* VMFUNC Instruction required */
+  CpuVMFUNC,
   /* 64bit support available, used by -march= in assembler.  */
   CpuLM,
+  /* RDRSEED instruction required.  */
+  CpuRDSEED,
+  /* Multi-presisionn add-carry instructions are required.  */
+  CpuADX,
+  /* Supports prefetchw instruction.  */
+  CpuPRFCHW,
   /* 64bit support required  */
   Cpu64,
   /* Not supported in the 64bit mode  */
   CpuNo64,
   /* The last bitfield in i386_cpu_flags.  */
   CpuMax = CpuNo64
 };
 
 #define CpuNumOfUints \
   (CpuMax / sizeof (unsigned int) / CHAR_BIT + 1)
@@ skipping 54 matching lines @@
       unsigned int cpubmi:1;
       unsigned int cputbm:1;
       unsigned int cpumovbe:1;
       unsigned int cpuept:1;
       unsigned int cpurdtscp:1;
       unsigned int cpufsgsbase:1;
       unsigned int cpurdrnd:1;
       unsigned int cpuf16c:1;
       unsigned int cpubmi2:1;
       unsigned int cpulzcnt:1;
+      unsigned int cpuhle:1;
+      unsigned int cpurtm:1;
       unsigned int cpuinvpcid:1;
+      unsigned int cpuvmfunc:1;
       unsigned int cpulm:1;
+      unsigned int cpurdseed:1;
+      unsigned int cpuadx:1;
+      unsigned int cpuprfchw:1;
       unsigned int cpu64:1;
       unsigned int cpuno64:1;
 #ifdef CpuUnused
       unsigned int unused:(CpuNumOfBits - CpuUnused);
 #endif
     } bitfield;
   unsigned int array[CpuNumOfUints];
 } i386_cpu_flags;
 
 /* Position of opcode_modifier bits.  */
@@ skipping 56 matching lines @@
   IsString,
   /* quick test for lockable instructions */
   IsLockable,
   /* fake an extra reg operand for clr, imul and special register
      processing for some instructions.  */
   RegKludge,
   /* The first operand must be xmm0 */
   FirstXmm0,
   /* An implicit xmm0 as the first operand */
   Implicit1stXmm0,
+  /* The HLE prefix is OK:
+     1. With a LOCK prefix.
+     2. With or without a LOCK prefix.
+     3. With a RELEASE (0xf3) prefix.
+   */
+#define HLEPrefixNone           0
+#define HLEPrefixLock           1
+#define HLEPrefixAny            2
+#define HLEPrefixRelease        3
+  HLEPrefixOk,
+  /* An instruction on which a "rep" prefix is acceptable.  */
+  RepPrefixOk,
   /* Convert to DWORD */
   ToDword,
   /* Convert to QWORD */
   ToQword,
   /* Address prefix changes operand 0 */
   AddrPrefixOp0,
   /* opcode is a prefix */
   IsPrefix,
   /* instruction has extension in 8 bit imm */
   ImmExt,
   /* instruction don't need Rex64 prefix.  */
   NoRex64,
   /* instruction require Rex64 prefix.  */
   Rex64,
   /* deprecated fp insn, gets a warning */
   Ugh,
   /* insn has VEX prefix:
         1: 128bit VEX prefix.
         2: 256bit VEX prefix.
         3: Scalar VEX prefix.
    */
 #define VEX128          1
 #define VEX256          2
 #define VEXScalar       3
   Vex,
   /* How to encode VEX.vvvv:
      0: VEX.vvvv must be 1111b.
      1: VEX.NDS.  Register-only source is encoded in VEX.vvvv where
         the content of source registers will be preserved.
-        VEX.DDS.  The second register operand is encoded in VEX.vvvv 
+        VEX.DDS.  The second register operand is encoded in VEX.vvvv
         where the content of first source register will be overwritten
         by the result.
         VEX.NDD2.  The second destination register operand is encoded in
         VEX.vvvv for instructions with 2 destination register operands.
         For assembler, there are no difference between VEX.NDS, VEX.DDS
         and VEX.NDD2.
      2. VEX.NDD.  Register destination is encoded in VEX.vvvv for
      instructions with 1 destination register operand.
      3. VEX.LWP.  Register destination is encoded in VEX.vvvv and one
         of the operands can access a memory location.
@@ skipping 83 matching lines @@
   unsigned int no_lsuf:1;
   unsigned int no_ssuf:1;
   unsigned int no_qsuf:1;
   unsigned int no_ldsuf:1;
   unsigned int fwait:1;
   unsigned int isstring:1;
   unsigned int islockable:1;
   unsigned int regkludge:1;
   unsigned int firstxmm0:1;
   unsigned int implicit1stxmm0:1;
+  unsigned int hleprefixok:2;
+  unsigned int repprefixok:1;
   unsigned int todword:1;
   unsigned int toqword:1;
   unsigned int addrprefixop0:1;
   unsigned int isprefix:1;
   unsigned int immext:1;
   unsigned int norex64:1;
   unsigned int rex64:1;
   unsigned int ugh:1;
   unsigned int vex:2;
   unsigned int vexvvvv:2;
@@ skipping 199 matching lines @@
   unsigned int base_opcode;
 #define Opcode_D        0x2 /* Direction bit:
                                set if Reg --> Regmem;
                                unset if Regmem --> Reg. */
 #define Opcode_FloatR   0x8 /* Bit to swap src/dest for float insns. */
 #define Opcode_FloatD 0x400 /* Direction bit for float insns. */
 
   /* extension_opcode is the 3 bit extension for group <n> insns.
      This field is also used to store the 8-bit opcode suffix for the
      AMD 3DNow! instructions.
-     If this template has no extension opcode (the usual case) use None 
+     If this template has no extension opcode (the usual case) use None
      Instructions */
   unsigned int extension_opcode;
 #define None 0xffff             /* If no extension_opcode is possible.  */
 
   /* Opcode length.  */
   unsigned char opcode_length;
 
   /* cpu feature flags */
   i386_cpu_flags cpu_flags;
 
@@ skipping 47 matching lines @@
   unsigned int seg_prefix;
 }
 seg_entry;
 
 extern const seg_entry cs;
 extern const seg_entry ds;
 extern const seg_entry ss;
 extern const seg_entry es;
 extern const seg_entry fs;
 extern const seg_entry gs;