Merge GDB 7.5.1

opcodes/i386-dis.c

 /* Print i386 instructions for GDB, the GNU debugger.
    Copyright 1988, 1989, 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
    2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011
    Free Software Foundation, Inc.
 
    This file is part of the GNU opcodes library.
 
    This library is free software; you can redistribute it and/or modify
    it under the terms of the GNU General Public License as published by
    the Free Software Foundation; either version 3, or (at your option)
@@ skipping 90 matching lines @@
 static void VCMP_Fixup (int, int);
 static void OP_0f07 (int, int);
 static void OP_Monitor (int, int);
 static void OP_Mwait (int, int);
 static void NOP_Fixup1 (int, int);
 static void NOP_Fixup2 (int, int);
 static void OP_3DNowSuffix (int, int);
 static void CMP_Fixup (int, int);
 static void BadOp (void);
 static void REP_Fixup (int, int);
+static void HLE_Fixup1 (int, int);
+static void HLE_Fixup2 (int, int);
+static void HLE_Fixup3 (int, int);
 static void CMPXCHG8B_Fixup (int, int);
 static void XMM_Fixup (int, int);
 static void CRC32_Fixup (int, int);
 static void FXSAVE_Fixup (int, int);
 static void OP_LWPCB_E (int, int);
 static void OP_LWP_E (int, int);
 static void OP_Vex_2src_1 (int, int);
 static void OP_Vex_2src_2 (int, int);
 
 static void MOVBE_Fixup (int, int);
@@ skipping 284 matching lines @@
 /* Used handle "rep" prefix for string instructions.  */
 #define Xbr { REP_Fixup, eSI_reg }
 #define Xvr { REP_Fixup, eSI_reg }
 #define Ybr { REP_Fixup, eDI_reg }
 #define Yvr { REP_Fixup, eDI_reg }
 #define Yzr { REP_Fixup, eDI_reg }
 #define indirDXr { REP_Fixup, indir_dx_reg }
 #define ALr { REP_Fixup, al_reg }
 #define eAXr { REP_Fixup, eAX_reg }
 
+/* Used handle HLE prefix for lockable instructions.  */
+#define Ebh1 { HLE_Fixup1, b_mode }
+#define Evh1 { HLE_Fixup1, v_mode }
+#define Ebh2 { HLE_Fixup2, b_mode }
+#define Evh2 { HLE_Fixup2, v_mode }
+#define Ebh3 { HLE_Fixup3, b_mode }
+#define Evh3 { HLE_Fixup3, v_mode }
+
 #define cond_jump_flag { NULL, cond_jump_mode }
 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
 
 /* bits in sizeflag */
 #define SUFFIX_ALWAYS 4
 #define AFLAG 2
 #define DFLAG 1
 
 enum
 {
@@ skipping 210 matching lines @@
   REG_VEX_0F38F3,
   REG_XOP_LWPCB,
   REG_XOP_LWP,
   REG_XOP_TBM_01,
   REG_XOP_TBM_02
 };
 
 enum
 {
   MOD_8D = 0,
+  MOD_C6_REG_7,
+  MOD_C7_REG_7,
   MOD_0F01_REG_0,
   MOD_0F01_REG_1,
   MOD_0F01_REG_2,
   MOD_0F01_REG_3,
   MOD_0F01_REG_7,
   MOD_0F12_PREFIX_0,
   MOD_0F13,
   MOD_0F16_PREFIX_0,
   MOD_0F17,
   MOD_0F18_REG_0,
@@ skipping 68 matching lines @@
   MOD_VEX_0F382D_PREFIX_2,
   MOD_VEX_0F382E_PREFIX_2,
   MOD_VEX_0F382F_PREFIX_2,
   MOD_VEX_0F385A_PREFIX_2,
   MOD_VEX_0F388C_PREFIX_2,
   MOD_VEX_0F388E_PREFIX_2,
 };
 
 enum
 {
-  RM_0F01_REG_0 = 0,
+  RM_C6_REG_7 = 0,
+  RM_C7_REG_7,
+  RM_0F01_REG_0,
   RM_0F01_REG_1,
   RM_0F01_REG_2,
   RM_0F01_REG_3,
   RM_0F01_REG_7,
   RM_0FAE_REG_5,
   RM_0FAE_REG_6,
   RM_0FAE_REG_7
 };
 
 enum
@@ skipping 85 matching lines @@
   PREFIX_0F3880,
   PREFIX_0F3881,
   PREFIX_0F3882,
   PREFIX_0F38DB,
   PREFIX_0F38DC,
   PREFIX_0F38DD,
   PREFIX_0F38DE,
   PREFIX_0F38DF,
   PREFIX_0F38F0,
   PREFIX_0F38F1,
+  PREFIX_0F38F6,
   PREFIX_0F3A08,
   PREFIX_0F3A09,
   PREFIX_0F3A0A,
   PREFIX_0F3A0B,
   PREFIX_0F3A0C,
   PREFIX_0F3A0D,
   PREFIX_0F3A0E,
   PREFIX_0F3A14,
   PREFIX_0F3A15,
   PREFIX_0F3A16,
@@ skipping 790 matching lines @@
    "LW" => print 'd', 'q' depending on the VEX.W bit
 
    Many of the above letters print nothing in Intel mode.  See "putop"
    for the details.
 
    Braces '{' and '}', and vertical bars '|', indicate alternative
    mnemonic strings for AT&T and Intel.  */
 
 static const struct dis386 dis386[] = {
   /* 00 */
-  { "addB",             { Eb, Gb } },
-  { "addS",             { Ev, Gv } },
+  { "addB",             { Ebh1, Gb } },
+  { "addS",             { Evh1, Gv } },
   { "addB",             { Gb, EbS } },
   { "addS",             { Gv, EvS } },
   { "addB",             { AL, Ib } },
   { "addS",             { eAX, Iv } },
   { X86_64_TABLE (X86_64_06) },
   { X86_64_TABLE (X86_64_07) },
   /* 08 */
-  { "orB",              { Eb, Gb } },
-  { "orS",              { Ev, Gv } },
+  { "orB",              { Ebh1, Gb } },
+  { "orS",              { Evh1, Gv } },
   { "orB",              { Gb, EbS } },
   { "orS",              { Gv, EvS } },
   { "orB",              { AL, Ib } },
   { "orS",              { eAX, Iv } },
   { X86_64_TABLE (X86_64_0D) },
   { Bad_Opcode },       /* 0x0f extended opcode escape */
   /* 10 */
-  { "adcB",             { Eb, Gb } },
-  { "adcS",             { Ev, Gv } },
+  { "adcB",             { Ebh1, Gb } },
+  { "adcS",             { Evh1, Gv } },
   { "adcB",             { Gb, EbS } },
   { "adcS",             { Gv, EvS } },
   { "adcB",             { AL, Ib } },
   { "adcS",             { eAX, Iv } },
   { X86_64_TABLE (X86_64_16) },
   { X86_64_TABLE (X86_64_17) },
   /* 18 */
-  { "sbbB",             { Eb, Gb } },
-  { "sbbS",             { Ev, Gv } },
+  { "sbbB",             { Ebh1, Gb } },
+  { "sbbS",             { Evh1, Gv } },
   { "sbbB",             { Gb, EbS } },
   { "sbbS",             { Gv, EvS } },
   { "sbbB",             { AL, Ib } },
   { "sbbS",             { eAX, Iv } },
   { X86_64_TABLE (X86_64_1E) },
   { X86_64_TABLE (X86_64_1F) },
   /* 20 */
-  { "andB",             { Eb, Gb } },
-  { "andS",             { Ev, Gv } },
+  { "andB",             { Ebh1, Gb } },
+  { "andS",             { Evh1, Gv } },
   { "andB",             { Gb, EbS } },
   { "andS",             { Gv, EvS } },
   { "andB",             { AL, Ib } },
   { "andS",             { eAX, Iv } },
   { Bad_Opcode },       /* SEG ES prefix */
   { X86_64_TABLE (X86_64_27) },
   /* 28 */
-  { "subB",             { Eb, Gb } },
-  { "subS",             { Ev, Gv } },
+  { "subB",             { Ebh1, Gb } },
+  { "subS",             { Evh1, Gv } },
   { "subB",             { Gb, EbS } },
   { "subS",             { Gv, EvS } },
   { "subB",             { AL, Ib } },
   { "subS",             { eAX, Iv } },
   { Bad_Opcode },       /* SEG CS prefix */
   { X86_64_TABLE (X86_64_2F) },
   /* 30 */
-  { "xorB",             { Eb, Gb } },
-  { "xorS",             { Ev, Gv } },
+  { "xorB",             { Ebh1, Gb } },
+  { "xorS",             { Evh1, Gv } },
   { "xorB",             { Gb, EbS } },
   { "xorS",             { Gv, EvS } },
   { "xorB",             { AL, Ib } },
   { "xorS",             { eAX, Iv } },
   { Bad_Opcode },       /* SEG SS prefix */
   { X86_64_TABLE (X86_64_37) },
   /* 38 */
   { "cmpB",             { Eb, Gb } },
   { "cmpS",             { Ev, Gv } },
   { "cmpB",             { Gb, EbS } },
@@ skipping 74 matching lines @@
   { "jgeH",             { Jb, XX, cond_jump_flag } },
   { "jleH",             { Jb, XX, cond_jump_flag } },
   { "jgH",              { Jb, XX, cond_jump_flag } },
   /* 80 */
   { REG_TABLE (REG_80) },
   { REG_TABLE (REG_81) },
   { Bad_Opcode },
   { REG_TABLE (REG_82) },
   { "testB",            { Eb, Gb } },
   { "testS",            { Ev, Gv } },
-  { "xchgB",            { Eb, Gb } },
-  { "xchgS",            { Ev, Gv } },
+  { "xchgB",            { Ebh2, Gb } },
+  { "xchgS",            { Evh2, Gv } },
   /* 88 */
-  { "movB",             { Eb, Gb } },
-  { "movS",             { Ev, Gv } },
+  { "movB",             { Ebh3, Gb } },
+  { "movS",             { Evh3, Gv } },
   { "movB",             { Gb, EbS } },
   { "movS",             { Gv, EvS } },
   { "movD",             { Sv, Sw } },
   { MOD_TABLE (MOD_8D) },
   { "movD",             { Sw, Sv } },
   { REG_TABLE (REG_8F) },
   /* 90 */
   { PREFIX_TABLE (PREFIX_90) },
   { "xchgS",            { RMeCX, eAX } },
   { "xchgS",            { RMeDX, eAX } },
@@ skipping 308 matching lines @@
   { "cpuid",            { XX } },
   { "btS",              { Ev, Gv } },
   { "shldS",            { Ev, Gv, Ib } },
   { "shldS",            { Ev, Gv, CL } },
   { REG_TABLE (REG_0FA6) },
   { REG_TABLE (REG_0FA7) },
   /* a8 */
   { "pushT",            { gs } },
   { "popT",             { gs } },
   { "rsm",              { XX } },
-  { "btsS",             { Ev, Gv } },
+  { "btsS",             { Evh1, Gv } },
   { "shrdS",            { Ev, Gv, Ib } },
   { "shrdS",            { Ev, Gv, CL } },
   { REG_TABLE (REG_0FAE) },
   { "imulS",            { Gv, Ev } },
   /* b0 */
-  { "cmpxchgB",         { Eb, Gb } },
-  { "cmpxchgS",         { Ev, Gv } },
+  { "cmpxchgB",         { Ebh1, Gb } },
+  { "cmpxchgS",         { Evh1, Gv } },
   { MOD_TABLE (MOD_0FB2) },
-  { "btrS",             { Ev, Gv } },
+  { "btrS",             { Evh1, Gv } },
   { MOD_TABLE (MOD_0FB4) },
   { MOD_TABLE (MOD_0FB5) },
   { "movz{bR|x}",       { Gv, Eb } },
   { "movz{wR|x}",       { Gv, Ew } }, /* yes, there really is movzww ! */
   /* b8 */
   { PREFIX_TABLE (PREFIX_0FB8) },
   { "ud1",              { XX } },
   { REG_TABLE (REG_0FBA) },
-  { "btcS",             { Ev, Gv } },
+  { "btcS",             { Evh1, Gv } },
   { PREFIX_TABLE (PREFIX_0FBC) },
   { PREFIX_TABLE (PREFIX_0FBD) },
   { "movs{bR|x}",       { Gv, Eb } },
   { "movs{wR|x}",       { Gv, Ew } }, /* yes, there really is movsww ! */
   /* c0 */
-  { "xaddB",            { Eb, Gb } },
-  { "xaddS",            { Ev, Gv } },
+  { "xaddB",            { Ebh1, Gb } },
+  { "xaddS",            { Evh1, Gv } },
   { PREFIX_TABLE (PREFIX_0FC2) },
   { PREFIX_TABLE (PREFIX_0FC3) },
   { "pinsrw",           { MX, Edqw, Ib } },
   { "pextrw",           { Gdq, MS, Ib } },
   { "shufpX",           { XM, EXx, Ib } },
   { REG_TABLE (REG_0FC7) },
   /* c8 */
   { "bswap",            { RMeAX } },
   { "bswap",            { RMeCX } },
   { "bswap",            { RMeDX } },
@@ skipping 261 matching lines @@
 static const char *att_names_ymm[] = {
   "%ymm0", "%ymm1", "%ymm2", "%ymm3",
   "%ymm4", "%ymm5", "%ymm6", "%ymm7",
   "%ymm8", "%ymm9", "%ymm10", "%ymm11",
   "%ymm12", "%ymm13", "%ymm14", "%ymm15"
 };
 
 static const struct dis386 reg_table[][8] = {
   /* REG_80 */
   {
-    { "addA",   { Eb, Ib } },
-    { "orA",    { Eb, Ib } },
-    { "adcA",   { Eb, Ib } },
-    { "sbbA",   { Eb, Ib } },
-    { "andA",   { Eb, Ib } },
-    { "subA",   { Eb, Ib } },
-    { "xorA",   { Eb, Ib } },
+    { "addA",   { Ebh1, Ib } },
+    { "orA",    { Ebh1, Ib } },
+    { "adcA",   { Ebh1, Ib } },
+    { "sbbA",   { Ebh1, Ib } },
+    { "andA",   { Ebh1, Ib } },
+    { "subA",   { Ebh1, Ib } },
+    { "xorA",   { Ebh1, Ib } },
     { "cmpA",   { Eb, Ib } },
   },
   /* REG_81 */
   {
-    { "addQ",   { Ev, Iv } },
-    { "orQ",    { Ev, Iv } },
-    { "adcQ",   { Ev, Iv } },
-    { "sbbQ",   { Ev, Iv } },
-    { "andQ",   { Ev, Iv } },
-    { "subQ",   { Ev, Iv } },
-    { "xorQ",   { Ev, Iv } },
+    { "addQ",   { Evh1, Iv } },
+    { "orQ",    { Evh1, Iv } },
+    { "adcQ",   { Evh1, Iv } },
+    { "sbbQ",   { Evh1, Iv } },
+    { "andQ",   { Evh1, Iv } },
+    { "subQ",   { Evh1, Iv } },
+    { "xorQ",   { Evh1, Iv } },
     { "cmpQ",   { Ev, Iv } },
   },
   /* REG_82 */
   {
-    { "addQ",   { Ev, sIb } },
-    { "orQ",    { Ev, sIb } },
-    { "adcQ",   { Ev, sIb } },
-    { "sbbQ",   { Ev, sIb } },
-    { "andQ",   { Ev, sIb } },
-    { "subQ",   { Ev, sIb } },
-    { "xorQ",   { Ev, sIb } },
+    { "addQ",   { Evh1, sIb } },
+    { "orQ",    { Evh1, sIb } },
+    { "adcQ",   { Evh1, sIb } },
+    { "sbbQ",   { Evh1, sIb } },
+    { "andQ",   { Evh1, sIb } },
+    { "subQ",   { Evh1, sIb } },
+    { "xorQ",   { Evh1, sIb } },
     { "cmpQ",   { Ev, sIb } },
   },
   /* REG_8F */
   {
     { "popU",   { stackEv } },
     { XOP_8F_TABLE (XOP_09) },
     { Bad_Opcode },
     { Bad_Opcode },
     { Bad_Opcode },
     { XOP_8F_TABLE (XOP_09) },
@@ skipping 15 matching lines @@
     { "rorQ",   { Ev, Ib } },
     { "rclQ",   { Ev, Ib } },
     { "rcrQ",   { Ev, Ib } },
     { "shlQ",   { Ev, Ib } },
     { "shrQ",   { Ev, Ib } },
     { Bad_Opcode },
     { "sarQ",   { Ev, Ib } },
   },
   /* REG_C6 */
   {
-    { "movA",   { Eb, Ib } },
+    { "movA",   { Ebh3, Ib } },
+    { Bad_Opcode },
+    { Bad_Opcode },
+    { Bad_Opcode },
+    { Bad_Opcode },
+    { Bad_Opcode },
+    { Bad_Opcode },
+    { MOD_TABLE (MOD_C6_REG_7) },
   },
   /* REG_C7 */
   {
-    { "movQ",   { Ev, Iv } },
+    { "movQ",   { Evh3, Iv } },
+    { Bad_Opcode },
+    { Bad_Opcode },
+    { Bad_Opcode },
+    { Bad_Opcode },
+    { Bad_Opcode },
+    { Bad_Opcode },
+    { MOD_TABLE (MOD_C7_REG_7) },
   },
   /* REG_D0 */
   {
     { "rolA",   { Eb, I1 } },
     { "rorA",   { Eb, I1 } },
     { "rclA",   { Eb, I1 } },
     { "rcrA",   { Eb, I1 } },
     { "shlA",   { Eb, I1 } },
     { "shrA",   { Eb, I1 } },
     { Bad_Opcode },
@@ skipping 29 matching lines @@
     { "rcrQ",   { Ev, CL } },
     { "shlQ",   { Ev, CL } },
     { "shrQ",   { Ev, CL } },
     { Bad_Opcode },
     { "sarQ",   { Ev, CL } },
   },
   /* REG_F6 */
   {
     { "testA",  { Eb, Ib } },
     { Bad_Opcode },
-    { "notA",   { Eb } },
-    { "negA",   { Eb } },
+    { "notA",   { Ebh1 } },
+    { "negA",   { Ebh1 } },
     { "mulA",   { Eb } },       /* Don't print the implicit %al register,  */
     { "imulA",  { Eb } },       /* to distinguish these opcodes from other */
     { "divA",   { Eb } },       /* mul/imul opcodes.  Do the same for div  */
     { "idivA",  { Eb } },       /* and idiv for consistency.               */
   },
   /* REG_F7 */
   {
     { "testQ",  { Ev, Iv } },
     { Bad_Opcode },
-    { "notQ",   { Ev } },
-    { "negQ",   { Ev } },
+    { "notQ",   { Evh1 } },
+    { "negQ",   { Evh1 } },
     { "mulQ",   { Ev } },       /* Don't print the implicit register.  */
     { "imulQ",  { Ev } },
     { "divQ",   { Ev } },
     { "idivQ",  { Ev } },
   },
   /* REG_FE */
   {
-    { "incA",   { Eb } },
-    { "decA",   { Eb } },
+    { "incA",   { Ebh1 } },
+    { "decA",   { Ebh1 } },
   },
   /* REG_FF */
   {
-    { "incQ",   { Ev } },
-    { "decQ",   { Ev } },
+    { "incQ",   { Evh1 } },
+    { "decQ",   { Evh1 } },
     { "call{T|}", { indirEv } },
     { "Jcall{T|}", { indirEp } },
     { "jmp{T|}", { indirEv } },
     { "Jjmp{T|}", { indirEp } },
     { "pushU",  { stackEv } },
     { Bad_Opcode },
   },
   /* REG_0F00 */
   {
     { "sldtD",  { Sv } },
@@ skipping 85 matching lines @@
     { MOD_TABLE (MOD_0FAE_REG_6) },
     { MOD_TABLE (MOD_0FAE_REG_7) },
   },
   /* REG_0FBA */
   {
     { Bad_Opcode },
     { Bad_Opcode },
     { Bad_Opcode },
     { Bad_Opcode },
     { "btQ",    { Ev, Ib } },
-    { "btsQ",   { Ev, Ib } },
-    { "btrQ",   { Ev, Ib } },
-    { "btcQ",   { Ev, Ib } },
+    { "btsQ",   { Evh1, Ib } },
+    { "btrQ",   { Evh1, Ib } },
+    { "btcQ",   { Evh1, Ib } },
   },
   /* REG_0FC7 */
   {
     { Bad_Opcode },
     { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } } },
     { Bad_Opcode },
     { Bad_Opcode },
     { Bad_Opcode },
     { Bad_Opcode },
     { MOD_TABLE (MOD_0FC7_REG_6) },
@@ skipping 747 matching lines @@
   },
 
   /* PREFIX_0F38F1 */
   {
     { "movbeS", { { MOVBE_Fixup, v_mode }, Gv } },
     { Bad_Opcode },
     { "movbeS", { { MOVBE_Fixup, v_mode }, Gv } },
     { "crc32",  { Gdq, { CRC32_Fixup, v_mode } } },     
   },
 
+  /* PREFIX_0F38F6 */
+  {
+    { Bad_Opcode },
+    { "adoxS",  { Gdq, Edq} },
+    { "adcxS",  { Gdq, Edq} },
+    { Bad_Opcode },
+  },
+
   /* PREFIX_0F3A08 */
   {
     { Bad_Opcode },
     { Bad_Opcode },
     { "roundps", { XM, EXx, Ib } },
   },
 
   /* PREFIX_0F3A09 */
   {
     { Bad_Opcode },
@@ skipping 2550 matching lines @@
     { Bad_Opcode },
     { Bad_Opcode },
     { Bad_Opcode },
     /* f0 */
     { PREFIX_TABLE (PREFIX_0F38F0) },
     { PREFIX_TABLE (PREFIX_0F38F1) },
     { Bad_Opcode },
     { Bad_Opcode },
     { Bad_Opcode },
     { Bad_Opcode },
-    { Bad_Opcode },
+    { PREFIX_TABLE (PREFIX_0F38F6) },
     { Bad_Opcode },
     /* f8 */
     { Bad_Opcode },
     { Bad_Opcode },
     { Bad_Opcode },
     { Bad_Opcode },
     { Bad_Opcode },
     { Bad_Opcode },
     { Bad_Opcode },
     { Bad_Opcode },
@@ skipping 4019 matching lines @@
     { "vaeskeygenassist", { XM, EXx, Ib } },
   },
 };
 
 static const struct dis386 mod_table[][2] = {
   {
     /* MOD_8D */
     { "leaS",           { Gv, M } },
   },
   {
+    /* MOD_C6_REG_7 */
+    { Bad_Opcode },
+    { RM_TABLE (RM_C6_REG_7) },
+  },
+  {
+    /* MOD_C7_REG_7 */
+    { Bad_Opcode },
+    { RM_TABLE (RM_C7_REG_7) },
+  },
+  {
     /* MOD_0F01_REG_0 */
     { X86_64_TABLE (X86_64_0F01_REG_0) },
     { RM_TABLE (RM_0F01_REG_0) },
   },
   {
     /* MOD_0F01_REG_1 */
     { X86_64_TABLE (X86_64_0F01_REG_1) },
     { RM_TABLE (RM_0F01_REG_1) },
   },
   {
@@ skipping 198 matching lines @@
     { "lgsS",           { Gv, Mp } },
   },
   {
     /* MOD_0FC7_REG_6 */
     { PREFIX_TABLE (PREFIX_0FC7_REG_6) },
     { "rdrand",         { Ev } },
   },
   {
     /* MOD_0FC7_REG_7 */
     { "vmptrst",        { Mq } },
+    { "rdseed",         { Ev } },
   },
   {
     /* MOD_0FD7 */
     { Bad_Opcode },
     { "pmovmskb",       { Gdq, MS } },
   },
   {
     /* MOD_0FE7_PREFIX_2 */
     { "movntdq",        { Mx, XM } },
   },
@@ skipping 150 matching lines @@
     { "vpmaskmov%LW",   { XM, Vex, Mx } },
   },
   {
     /* MOD_VEX_0F388E_PREFIX_2 */
     { "vpmaskmov%LW",   { Mx, Vex, XM } },
   },
 };
 
 static const struct dis386 rm_table[][8] = {
   {
+    /* RM_C6_REG_7 */
+    { "xabort",         { Skip_MODRM, Ib } },
+  },
+  {
+    /* RM_C7_REG_7 */
+    { "xbeginT",        { Skip_MODRM, Jv } },
+  },
+  {
     /* RM_0F01_REG_0 */
     { Bad_Opcode },
     { "vmcall",         { Skip_MODRM } },
     { "vmlaunch",       { Skip_MODRM } },
     { "vmresume",       { Skip_MODRM } },
     { "vmxoff",         { Skip_MODRM } },
   },
   {
     /* RM_0F01_REG_1 */
     { "monitor",        { { OP_Monitor, 0 } } },
     { "mwait",          { { OP_Mwait, 0 } } },
   },
   {
     /* RM_0F01_REG_2 */
     { "xgetbv",         { Skip_MODRM } },
     { "xsetbv",         { Skip_MODRM } },
+    { Bad_Opcode },
+    { Bad_Opcode },
+    { "vmfunc",         { Skip_MODRM } },
+    { "xend",           { Skip_MODRM } },
+    { "xtest",          { Skip_MODRM } },
+    { Bad_Opcode },
   },
   {
     /* RM_0F01_REG_3 */
     { "vmrun",          { Skip_MODRM } },
     { "vmmcall",        { Skip_MODRM } },
     { "vmload",         { Skip_MODRM } },
     { "vmsave",         { Skip_MODRM } },
     { "stgi",           { Skip_MODRM } },
     { "clgi",           { Skip_MODRM } },
     { "skinit",         { Skip_MODRM } },
@@ skipping 20 matching lines @@
 
 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
 
 /* We use the high bit to indicate different name for the same
    prefix.  */
 #define ADDR16_PREFIX   (0x67 | 0x100)
 #define ADDR32_PREFIX   (0x67 | 0x200)
 #define DATA16_PREFIX   (0x66 | 0x100)
 #define DATA32_PREFIX   (0x66 | 0x200)
 #define REP_PREFIX      (0xf3 | 0x100)
+#define XACQUIRE_PREFIX (0xf2 | 0x200)
+#define XRELEASE_PREFIX (0xf3 | 0x400)
 
 static int
 ckprefix (void)
 {
   int newrex, i, length;
   rex = 0;
   rex_ignored = 0;
   prefixes = 0;
   used_prefixes = 0;
   rex_used = 0;
@@ skipping 210 matching lines @@
     case ADDR16_PREFIX:
       return "addr16";
     case ADDR32_PREFIX:
       return "addr32";
     case DATA16_PREFIX:
       return "data16";
     case DATA32_PREFIX:
       return "data32";
     case REP_PREFIX:
       return "rep";
+    case XACQUIRE_PREFIX:
+      return "xacquire";
+    case XRELEASE_PREFIX:
+      return "xrelease";
     default:
       return NULL;
     }
 }
 
 static char op_out[MAX_OPERANDS][100];
 static int op_ad, op_index[MAX_OPERANDS];
 static int two_source_ops;
 static bfd_vma op_address[MAX_OPERANDS];
 static bfd_vma op_riprel[MAX_OPERANDS];
@@ skipping 3598 matching lines @@
       break;
     case eSI_reg:
       OP_DSreg (bytemode, sizeflag);
       break;
     default:
       abort ();
       break;
     }
 }
 
+/* Similar to OP_E.  But the 0xf2/0xf3 prefixes should be displayed as
+   "xacquire"/"xrelease" for memory operand if there is a LOCK prefix.
+ */
+
+static void
+HLE_Fixup1 (int bytemode, int sizeflag)
+{
+  if (modrm.mod != 3
+      && (prefixes & PREFIX_LOCK) != 0)
+    {
+      if (prefixes & PREFIX_REPZ)
+        all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
+      if (prefixes & PREFIX_REPNZ)
+        all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
+    }
+
+  OP_E (bytemode, sizeflag);
+}
+
+/* Similar to OP_E.  But the 0xf2/0xf3 prefixes should be displayed as
+   "xacquire"/"xrelease" for memory operand.  No check for LOCK prefix.
+ */
+
+static void
+HLE_Fixup2 (int bytemode, int sizeflag)
+{
+  if (modrm.mod != 3)
+    {
+      if (prefixes & PREFIX_REPZ)
+        all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
+      if (prefixes & PREFIX_REPNZ)
+        all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
+    }
+
+  OP_E (bytemode, sizeflag);
+}
+
+/* Similar to OP_E.  But the 0xf3 prefixes should be displayed as
+   "xrelease" for memory operand.  No check for LOCK prefix.   */
+
+static void
+HLE_Fixup3 (int bytemode, int sizeflag)
+{
+  if (modrm.mod != 3
+      && last_repz_prefix > last_repnz_prefix
+      && (prefixes & PREFIX_REPZ) != 0)
+    all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
+
+  OP_E (bytemode, sizeflag);
+}
+
 static void
 CMPXCHG8B_Fixup (int bytemode, int sizeflag)
 {
   USED_REX (REX_W);
   if (rex & REX_W)
     {
       /* Change cmpxchg8b to cmpxchg16b.  */
       char *p = mnemonicendp - 2;
       mnemonicendp = stpcpy (p, "16b");
       bytemode = o_mode;
     }
+  else if ((prefixes & PREFIX_LOCK) != 0)
+    {
+      if (prefixes & PREFIX_REPZ)
+        all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
+      if (prefixes & PREFIX_REPNZ)
+        all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
+    }
+
   OP_M (bytemode, sizeflag);
 }
 
 static void
 XMM_Fixup (int reg, int sizeflag ATTRIBUTE_UNUSED)
 {
   const char **names;
 
   if (need_vex)
     {
@@ skipping 676 matching lines @@
   const char **names;
 
   if (vex.w)
     names = names64;
   else
     names = names32;
 
   oappend (names[vex.register_specifier]);
 }