Merge GDB 7.5.1

include/opcode/sparc.h

 /* Definitions for opcode table for the sparc.
    Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 2000, 2002,
    2003, 2005, 2010, 2011 Free Software Foundation, Inc.
 
    This file is part of GAS, the GNU Assembler, GDB, the GNU debugger, and
    the GNU Binutils.
 
    GAS/GDB is free software; you can redistribute it and/or modify
    it under the terms of the GNU General Public License as published by
    the Free Software Foundation; either version 3, or (at your option)
@@ skipping 81 matching lines @@
 /* Structure of an opcode table entry.  */
 
 typedef struct sparc_opcode
 {
   const char *name;
   unsigned long match;  /* Bits that must be set.  */
   unsigned long lose;   /* Bits that must not be set.  */
   const char *args;
   /* This was called "delayed" in versions before the flags.  */
   unsigned int flags;
+  unsigned int hwcaps;
   short architecture;   /* Bitmask of sparc_opcode_arch_val's.  */
 } sparc_opcode;
 
 /* FIXME: Add F_ANACHRONISTIC flag for v9.  */
 #define F_DELAYED       0x00000001 /* Delayed branch.  */
 #define F_ALIAS         0x00000002 /* Alias for a "real" instruction.  */
 #define F_UNBR          0x00000004 /* Unconditional branch.  */
 #define F_CONDBR        0x00000008 /* Conditional branch.  */
 #define F_JSR           0x00000010 /* Subroutine call.  */
 #define F_FLOAT         0x00000020 /* Floating point instruction (not a branch).  */
 #define F_FBR           0x00000040 /* Floating point branch.  */
-#define F_MUL32         0x00000100 /* umul/umulcc/smul/smulcc insns */
-#define F_DIV32         0x00000200 /* udiv/udivcc/sdiv/sdivcc insns */
-#define F_FSMULD        0x00000400 /* 'fsmuld' insn */
-#define F_V8PLUS        0x00000800 /* v9 insns available to 32bit */
-#define F_POPC          0x00001000 /* 'popc' insn */
-#define F_VIS           0x00002000 /* VIS insns */
-#define F_VIS2          0x00004000 /* VIS2 insns */
-#define F_ASI_BLK_INIT  0x00008000 /* block init ASIs */
-#define F_FMAF          0x00010000 /* fused multiply-add */
-#define F_VIS3          0x00020000 /* VIS3 insns */
-#define F_HPC           0x00040000 /* HPC insns */
-#define F_RANDOM        0x00080000 /* 'random' insn */
-#define F_TRANS         0x00100000 /* transaction insns */
-#define F_FJFMAU        0x00200000 /* unfused multiply-add */
-#define F_IMA           0x00400000 /* integer multiply-add */
-#define F_ASI_CACHE_SPARING \
-                        0x00800000 /* cache sparing ASIs */
 
-#define F_HWCAP_MASK    0x00ffff00
+/* These must match the HWCAP_* values precisely.  */
+#define HWCAP_MUL32     0x00000001 /* umul/umulcc/smul/smulcc insns */
+#define HWCAP_DIV32     0x00000002 /* udiv/udivcc/sdiv/sdivcc insns */
+#define HWCAP_FSMULD    0x00000004 /* 'fsmuld' insn */
+#define HWCAP_V8PLUS    0x00000008 /* v9 insns available to 32bit */
+#define HWCAP_POPC      0x00000010 /* 'popc' insn */
+#define HWCAP_VIS       0x00000020 /* VIS insns */
+#define HWCAP_VIS2      0x00000040 /* VIS2 insns */
+#define HWCAP_ASI_BLK_INIT      \
+                        0x00000080 /* block init ASIs */
+#define HWCAP_FMAF      0x00000100 /* fused multiply-add */
+#define HWCAP_VIS3      0x00000400 /* VIS3 insns */
+#define HWCAP_HPC       0x00000800 /* HPC insns */
+#define HWCAP_RANDOM    0x00001000 /* 'random' insn */
+#define HWCAP_TRANS     0x00002000 /* transaction insns */
+#define HWCAP_FJFMAU    0x00004000 /* unfused multiply-add */
+#define HWCAP_IMA       0x00008000 /* integer multiply-add */
+#define HWCAP_ASI_CACHE_SPARING \
+                        0x00010000 /* cache sparing ASIs */
+#define HWCAP_AES       0x00020000 /* AES crypto insns */
+#define HWCAP_DES       0x00040000 /* DES crypto insns */
+#define HWCAP_KASUMI    0x00080000 /* KASUMI crypto insns */
+#define HWCAP_CAMELLIA  0x00100000 /* CAMELLIA crypto insns */
+#define HWCAP_MD5       0x00200000 /* MD5 hashing insns */
+#define HWCAP_SHA1      0x00400000 /* SHA1 hashing insns */
+#define HWCAP_SHA256    0x00800000 /* SHA256 hashing insns */
+#define HWCAP_SHA512    0x01000000 /* SHA512 hashing insns */
+#define HWCAP_MPMUL     0x02000000 /* Multiple Precision Multiply */
+#define HWCAP_MONT      0x04000000 /* Montgomery Mult/Sqrt */
+#define HWCAP_PAUSE     0x08000000 /* Pause insn */
+#define HWCAP_CBCOND    0x10000000 /* Compare and Branch insns */
+#define HWCAP_CRC32C    0x20000000 /* CRC32C insn */
 
 /* All sparc opcodes are 32 bits, except for the `set' instruction (really a
    macro), which is 64 bits. It is handled as a special case.
 
    The match component is a mask saying which bits must match a particular
    opcode in order for an instruction to be an instance of that opcode.
 
    The args component is a string containing one character for each operand of the
    instruction.
 
@@ skipping 59 matching lines @@
         7       %fcc1. (v9)
         8       %fcc2. (v9)
         9       %fcc3. (v9)
         !       Privileged Register in rd (v9)
         ?       Privileged Register in rs1 (v9)
         *       Prefetch function constant. (v9)
         x       OPF field (v9 impdep).
         0       32/64 bit immediate for set or setx (v9) insns
         _       Ancillary state register in rd (v9a)
         /       Ancillary state register in rs1 (v9a)
-        (       entire floating point state register (%efsr).  */
+        (       entire floating point state register (%efsr)
+        )       5 bit immediate placed in RS3 field
+        =       2+8 bit PC relative immediate. (v9)  */
 
 #define OP2(x)          (((x) & 0x7) << 22)  /* Op2 field of format2 insns.  */
 #define OP3(x)          (((x) & 0x3f) << 19) /* Op3 field of format3 insns.  */
 #define OP(x)           ((unsigned) ((x) & 0x3) << 30) /* Op field of all insns.  */
 #define OPF(x)          (((x) & 0x1ff) << 5) /* Opf field of float insns.  */
 #define OPF_LOW5(x)     OPF ((x) & 0x1f)     /* V9.  */
 #define OPF_LOW4(x)     OPF ((x) & 0xf)      /* V9.  */
 #define F3F(x, y, z)    (OP (x) | OP3 (y) | OPF (z)) /* Format3 float insns.  */
 #define F3I(x)          (((x) & 0x1) << 13)  /* Immediate field of format 3 insns.  */
 #define F2(x, y)        (OP (x) | OP2(y))    /* Format 2 insns.  */
@@ skipping 27 matching lines @@
 extern int sparc_encode_prefetch (const char *);
 extern const char *sparc_decode_prefetch (int);
 extern int sparc_encode_sparclet_cpreg (const char *);
 extern const char *sparc_decode_sparclet_cpreg (int);
 
 /* Local Variables:
    fill-column: 131
    comment-column: 0
    End: */