Merge GDB 7.5.1

gdb/spu-tdep.c

 /* SPU target-dependent code for GDB, the GNU debugger.
    Copyright (C) 2006-2012 Free Software Foundation, Inc.
 
    Contributed by Ulrich Weigand <uweigand@de.ibm.com>.
    Based on a port by Sid Manning <sid@us.ibm.com>.
 
    This file is part of GDB.
 
    This program is free software; you can redistribute it and/or modify
    it under the terms of the GNU General Public License as published by
@@ skipping 831 matching lines @@
            control or the beginning of the function or reach the hard
            limit for the size of an epilogue.  */
 
 static int
 spu_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc)
 {
   enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
   CORE_ADDR scan_pc, func_start, func_end, epilogue_start, epilogue_end;
   bfd_byte buf[4];
   unsigned int insn;
-  int rt, ra, rb, rc, immed;
+  int rt, ra, rb, immed;
 
   /* Find the search limits based on function boundaries and hard limit.
      We assume the epilogue can be up to 64 instructions long.  */
 
   const int spu_max_epilogue_size = 64 * 4;
 
   if (!find_pc_partial_function (pc, NULL, &func_start, &func_end))
     return 0;
 
   if (pc - func_start < spu_max_epilogue_size)
@@ skipping 580 matching lines @@
 {
   struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
   CORE_ADDR pc = get_frame_register_unsigned (this_frame, SPU_PC_REGNUM);
   CORE_ADDR sp = get_frame_register_unsigned (this_frame, SPU_SP_REGNUM);
   return frame_id_build (SPUADDR (tdep->id, sp), SPUADDR (tdep->id, pc & -4));
 }
 
 /* Function return value access.  */
 
 static enum return_value_convention
-spu_return_value (struct gdbarch *gdbarch, struct type *func_type,
+spu_return_value (struct gdbarch *gdbarch, struct value *function,
                   struct type *type, struct regcache *regcache,
                   gdb_byte *out, const gdb_byte *in)
 {
+  struct type *func_type = function ? value_type (function) : NULL;
   enum return_value_convention rvc;
   int opencl_vector = 0;
 
   if (func_type)
     {
       func_type = check_typedef (func_type);
 
       if (TYPE_CODE (func_type) == TYPE_CODE_PTR)
         func_type = check_typedef (TYPE_TARGET_TYPE (func_type));
 
@@ skipping 468 matching lines @@
           sal = find_function_start_sal (sym, 1);
           pc = sal.pc;
         }
     }
 
   /* Use a numerical address for the set_breakpoint command to avoid having
      the breakpoint re-set incorrectly.  */
   xsnprintf (buf, sizeof buf, "*%s", core_addr_to_string (pc));
   create_breakpoint (get_objfile_arch (objfile), buf /* arg */,
                      NULL /* cond_string */, -1 /* thread */,
+                     NULL /* extra_string */,
                      0 /* parse_condition_and_thread */, 1 /* tempflag */,
                      bp_breakpoint /* type_wanted */,
                      0 /* ignore_count */,
                      AUTO_BOOLEAN_FALSE /* pending_break_support */,
                      &bkpt_breakpoint_ops /* ops */, 0 /* from_tty */,
                      1 /* enabled */, 0 /* internal  */, 0);
 }
 
 
 /* Look up OBJFILE loaded into FRAME's SPU context.  */
@@ skipping 68 matching lines @@
 static void
 info_spu_event_command (char *args, int from_tty)
 {
   struct frame_info *frame = get_selected_frame (NULL);
   ULONGEST event_status = 0;
   ULONGEST event_mask = 0;
   struct cleanup *chain;
   gdb_byte buf[100];
   char annex[32];
   LONGEST len;
-  int rc, id;
+  int id;
 
   if (gdbarch_bfd_arch_info (get_frame_arch (frame))->arch != bfd_arch_spu)
     error (_("\"info spu\" is only supported on the SPU architecture."));
 
   id = get_frame_register_unsigned (frame, SPU_ID_REGNUM);
 
   xsnprintf (annex, sizeof annex, "%d/event_status", id);
   len = target_read (&current_target, TARGET_OBJECT_SPU, annex,
                      buf, 0, (sizeof (buf) - 1));
   if (len <= 0)
@@ skipping 36 matching lines @@
   ULONGEST signal1 = 0;
   ULONGEST signal1_type = 0;
   int signal1_pending = 0;
   ULONGEST signal2 = 0;
   ULONGEST signal2_type = 0;
   int signal2_pending = 0;
   struct cleanup *chain;
   char annex[32];
   gdb_byte buf[100];
   LONGEST len;
-  int rc, id;
+  int id;
 
   if (gdbarch_bfd_arch_info (gdbarch)->arch != bfd_arch_spu)
     error (_("\"info spu\" is only supported on the SPU architecture."));
 
   id = get_frame_register_unsigned (frame, SPU_ID_REGNUM);
 
   xsnprintf (annex, sizeof annex, "%d/signal1", id);
   len = target_read (&current_target, TARGET_OBJECT_SPU, annex, buf, 0, 4);
   if (len < 0)
     error (_("Could not read signal1."));
@@ skipping 100 matching lines @@
 static void
 info_spu_mailbox_command (char *args, int from_tty)
 {
   struct frame_info *frame = get_selected_frame (NULL);
   struct gdbarch *gdbarch = get_frame_arch (frame);
   enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
   struct cleanup *chain;
   char annex[32];
   gdb_byte buf[1024];
   LONGEST len;
-  int i, id;
+  int id;
 
   if (gdbarch_bfd_arch_info (gdbarch)->arch != bfd_arch_spu)
     error (_("\"info spu\" is only supported on the SPU architecture."));
 
   id = get_frame_register_unsigned (frame, SPU_ID_REGNUM);
 
   chain = make_cleanup_ui_out_tuple_begin_end (current_uiout, "SPUInfoMailbox");
 
   xsnprintf (annex, sizeof annex, "%d/mbox_info", id);
   len = target_read (&current_target, TARGET_OBJECT_SPU, annex,
@@ skipping 127 matching lines @@
 
   ui_out_table_body (current_uiout);
 
   for (i = 0; i < nr; i++)
     {
       struct cleanup *cmd_chain;
       ULONGEST mfc_cq_dw0;
       ULONGEST mfc_cq_dw1;
       ULONGEST mfc_cq_dw2;
       int mfc_cmd_opcode, mfc_cmd_tag, rclass_id, tclass_id;
-      int lsa, size, list_lsa, list_size, mfc_lsa, mfc_size;
+      int list_lsa, list_size, mfc_lsa, mfc_size;
       ULONGEST mfc_ea;
       int list_valid_p, noop_valid_p, qw_valid_p, ea_valid_p, cmd_error_p;
 
       /* Decode contents of MFC Command Queue Context Save/Restore Registers.
          See "Cell Broadband Engine Registers V1.3", section 3.3.2.1.  */
 
       mfc_cq_dw0
         = extract_unsigned_integer (buf + 32*seq[i], 8, byte_order);
       mfc_cq_dw1
         = extract_unsigned_integer (buf + 32*seq[i] + 8, 8, byte_order);
@@ skipping 73 matching lines @@
   enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
   ULONGEST dma_info_type;
   ULONGEST dma_info_mask;
   ULONGEST dma_info_status;
   ULONGEST dma_info_stall_and_notify;
   ULONGEST dma_info_atomic_command_status;
   struct cleanup *chain;
   char annex[32];
   gdb_byte buf[1024];
   LONGEST len;
-  int i, id;
+  int id;
 
   if (gdbarch_bfd_arch_info (get_frame_arch (frame))->arch != bfd_arch_spu)
     error (_("\"info spu\" is only supported on the SPU architecture."));
 
   id = get_frame_register_unsigned (frame, SPU_ID_REGNUM);
 
   xsnprintf (annex, sizeof annex, "%d/dma_info", id);
   len = target_read (&current_target, TARGET_OBJECT_SPU, annex,
                      buf, 0, 40 + 16 * 32);
   if (len <= 0)
@@ skipping 58 matching lines @@
   struct frame_info *frame = get_selected_frame (NULL);
   struct gdbarch *gdbarch = get_frame_arch (frame);
   enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
   ULONGEST dma_info_type;
   ULONGEST dma_info_mask;
   ULONGEST dma_info_status;
   struct cleanup *chain;
   char annex[32];
   gdb_byte buf[1024];
   LONGEST len;
-  int i, id;
+  int id;
 
   if (gdbarch_bfd_arch_info (gdbarch)->arch != bfd_arch_spu)
     error (_("\"info spu\" is only supported on the SPU architecture."));
 
   id = get_frame_register_unsigned (frame, SPU_ID_REGNUM);
 
   xsnprintf (annex, sizeof annex, "%d/proxydma_info", id);
   len = target_read (&current_target, TARGET_OBJECT_SPU, annex,
                      buf, 0, 24 + 8 * 32);
   if (len <= 0)
@@ skipping 265 matching lines @@
   add_cmd ("mailbox", class_info, info_spu_mailbox_command,
            _("Display SPU mailbox facility status.\n"),
            &infospucmdlist);
   add_cmd ("dma", class_info, info_spu_dma_command,
            _("Display MFC DMA status.\n"),
            &infospucmdlist);
   add_cmd ("proxydma", class_info, info_spu_proxydma_command,
            _("Display MFC Proxy-DMA status.\n"),
            &infospucmdlist);
 }