OLD | NEW |
1 /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger. | 1 /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger. |
2 | 2 |
3 Copyright (C) 1988-2012 Free Software Foundation, Inc. | 3 Copyright (C) 1988-2012 Free Software Foundation, Inc. |
4 | 4 |
5 Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU | 5 Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU |
6 and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin. | 6 and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin. |
7 | 7 |
8 This file is part of GDB. | 8 This file is part of GDB. |
9 | 9 |
10 This program is free software; you can redistribute it and/or modify | 10 This program is free software; you can redistribute it and/or modify |
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55 #include "target-descriptions.h" | 55 #include "target-descriptions.h" |
56 #include "dwarf2-frame.h" | 56 #include "dwarf2-frame.h" |
57 #include "user-regs.h" | 57 #include "user-regs.h" |
58 #include "valprint.h" | 58 #include "valprint.h" |
59 #include "ax.h" | 59 #include "ax.h" |
60 | 60 |
61 static const struct objfile_data *mips_pdr_data; | 61 static const struct objfile_data *mips_pdr_data; |
62 | 62 |
63 static struct type *mips_register_type (struct gdbarch *gdbarch, int regnum); | 63 static struct type *mips_register_type (struct gdbarch *gdbarch, int regnum); |
64 | 64 |
| 65 static int mips32_instruction_has_delay_slot (struct gdbarch *, CORE_ADDR); |
| 66 static int micromips_instruction_has_delay_slot (struct gdbarch *, CORE_ADDR, |
| 67 int); |
| 68 static int mips16_instruction_has_delay_slot (struct gdbarch *, CORE_ADDR, |
| 69 int); |
| 70 |
65 /* A useful bit in the CP0 status register (MIPS_PS_REGNUM). */ | 71 /* A useful bit in the CP0 status register (MIPS_PS_REGNUM). */ |
66 /* This bit is set if we are emulating 32-bit FPRs on a 64-bit chip. */ | 72 /* This bit is set if we are emulating 32-bit FPRs on a 64-bit chip. */ |
67 #define ST0_FR (1 << 26) | 73 #define ST0_FR (1 << 26) |
68 | 74 |
69 /* The sizes of floating point registers. */ | 75 /* The sizes of floating point registers. */ |
70 | 76 |
71 enum | 77 enum |
72 { | 78 { |
73 MIPS_FPU_SINGLE_REGSIZE = 4, | 79 MIPS_FPU_SINGLE_REGSIZE = 4, |
74 MIPS_FPU_DOUBLE_REGSIZE = 8 | 80 MIPS_FPU_DOUBLE_REGSIZE = 8 |
75 }; | 81 }; |
76 | 82 |
77 enum | 83 enum |
78 { | 84 { |
79 MIPS32_REGSIZE = 4, | 85 MIPS32_REGSIZE = 4, |
80 MIPS64_REGSIZE = 8 | 86 MIPS64_REGSIZE = 8 |
81 }; | 87 }; |
82 | 88 |
83 static const char *mips_abi_string; | 89 static const char *mips_abi_string; |
84 | 90 |
85 static const char *mips_abi_strings[] = { | 91 static const char *const mips_abi_strings[] = { |
86 "auto", | 92 "auto", |
87 "n32", | 93 "n32", |
88 "o32", | 94 "o32", |
89 "n64", | 95 "n64", |
90 "o64", | 96 "o64", |
91 "eabi32", | 97 "eabi32", |
92 "eabi64", | 98 "eabi64", |
93 NULL | 99 NULL |
94 }; | 100 }; |
95 | 101 |
| 102 /* For backwards compatibility we default to MIPS16. This flag is |
| 103 overridden as soon as unambiguous ELF file flags tell us the |
| 104 compressed ISA encoding used. */ |
| 105 static const char mips_compression_mips16[] = "mips16"; |
| 106 static const char mips_compression_micromips[] = "micromips"; |
| 107 static const char *const mips_compression_strings[] = |
| 108 { |
| 109 mips_compression_mips16, |
| 110 mips_compression_micromips, |
| 111 NULL |
| 112 }; |
| 113 |
| 114 static const char *mips_compression_string = mips_compression_mips16; |
| 115 |
96 /* The standard register names, and all the valid aliases for them. */ | 116 /* The standard register names, and all the valid aliases for them. */ |
97 struct register_alias | 117 struct register_alias |
98 { | 118 { |
99 const char *name; | 119 const char *name; |
100 int regnum; | 120 int regnum; |
101 }; | 121 }; |
102 | 122 |
103 /* Aliases for o32 and most other ABIs. */ | 123 /* Aliases for o32 and most other ABIs. */ |
104 const struct register_alias mips_o32_aliases[] = { | 124 const struct register_alias mips_o32_aliases[] = { |
105 { "ta0", 12 }, | 125 { "ta0", 12 }, |
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172 { | 192 { |
173 return gdbarch_tdep (gdbarch)->regnum; | 193 return gdbarch_tdep (gdbarch)->regnum; |
174 } | 194 } |
175 | 195 |
176 static int | 196 static int |
177 mips_fpa0_regnum (struct gdbarch *gdbarch) | 197 mips_fpa0_regnum (struct gdbarch *gdbarch) |
178 { | 198 { |
179 return mips_regnum (gdbarch)->fp0 + 12; | 199 return mips_regnum (gdbarch)->fp0 + 12; |
180 } | 200 } |
181 | 201 |
| 202 /* Return 1 if REGNUM refers to a floating-point general register, raw |
| 203 or cooked. Otherwise return 0. */ |
| 204 |
| 205 static int |
| 206 mips_float_register_p (struct gdbarch *gdbarch, int regnum) |
| 207 { |
| 208 int rawnum = regnum % gdbarch_num_regs (gdbarch); |
| 209 |
| 210 return (rawnum >= mips_regnum (gdbarch)->fp0 |
| 211 && rawnum < mips_regnum (gdbarch)->fp0 + 32); |
| 212 } |
| 213 |
182 #define MIPS_EABI(gdbarch) (gdbarch_tdep (gdbarch)->mips_abi \ | 214 #define MIPS_EABI(gdbarch) (gdbarch_tdep (gdbarch)->mips_abi \ |
183 == MIPS_ABI_EABI32 \ | 215 == MIPS_ABI_EABI32 \ |
184 || gdbarch_tdep (gdbarch)->mips_abi == MIPS_ABI_EABI64) | 216 || gdbarch_tdep (gdbarch)->mips_abi == MIPS_ABI_EABI64) |
185 | 217 |
186 #define MIPS_LAST_FP_ARG_REGNUM(gdbarch) \ | 218 #define MIPS_LAST_FP_ARG_REGNUM(gdbarch) \ |
187 (gdbarch_tdep (gdbarch)->mips_last_fp_arg_regnum) | 219 (gdbarch_tdep (gdbarch)->mips_last_fp_arg_regnum) |
188 | 220 |
189 #define MIPS_LAST_ARG_REGNUM(gdbarch) \ | 221 #define MIPS_LAST_ARG_REGNUM(gdbarch) \ |
190 (gdbarch_tdep (gdbarch)->mips_last_arg_regnum) | 222 (gdbarch_tdep (gdbarch)->mips_last_arg_regnum) |
191 | 223 |
192 #define MIPS_FPU_TYPE(gdbarch) (gdbarch_tdep (gdbarch)->mips_fpu_type) | 224 #define MIPS_FPU_TYPE(gdbarch) (gdbarch_tdep (gdbarch)->mips_fpu_type) |
193 | 225 |
194 /* MIPS16 function addresses are odd (bit 0 is set). Here are some | |
195 functions to test, set, or clear bit 0 of addresses. */ | |
196 | |
197 static CORE_ADDR | |
198 is_mips16_addr (CORE_ADDR addr) | |
199 { | |
200 return ((addr) & 1); | |
201 } | |
202 | |
203 static CORE_ADDR | |
204 unmake_mips16_addr (CORE_ADDR addr) | |
205 { | |
206 return ((addr) & ~(CORE_ADDR) 1); | |
207 } | |
208 | |
209 static CORE_ADDR | |
210 make_mips16_addr (CORE_ADDR addr) | |
211 { | |
212 return ((addr) | (CORE_ADDR) 1); | |
213 } | |
214 | |
215 /* Return the MIPS ABI associated with GDBARCH. */ | 226 /* Return the MIPS ABI associated with GDBARCH. */ |
216 enum mips_abi | 227 enum mips_abi |
217 mips_abi (struct gdbarch *gdbarch) | 228 mips_abi (struct gdbarch *gdbarch) |
218 { | 229 { |
219 return gdbarch_tdep (gdbarch)->mips_abi; | 230 return gdbarch_tdep (gdbarch)->mips_abi; |
220 } | 231 } |
221 | 232 |
222 int | 233 int |
223 mips_isa_regsize (struct gdbarch *gdbarch) | 234 mips_isa_regsize (struct gdbarch *gdbarch) |
224 { | 235 { |
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248 case MIPS_ABI_O64: | 259 case MIPS_ABI_O64: |
249 case MIPS_ABI_EABI64: | 260 case MIPS_ABI_EABI64: |
250 return 8; | 261 return 8; |
251 case MIPS_ABI_UNKNOWN: | 262 case MIPS_ABI_UNKNOWN: |
252 case MIPS_ABI_LAST: | 263 case MIPS_ABI_LAST: |
253 default: | 264 default: |
254 internal_error (__FILE__, __LINE__, _("bad switch")); | 265 internal_error (__FILE__, __LINE__, _("bad switch")); |
255 } | 266 } |
256 } | 267 } |
257 | 268 |
| 269 /* MIPS16/microMIPS function addresses are odd (bit 0 is set). Here |
| 270 are some functions to handle addresses associated with compressed |
| 271 code including but not limited to testing, setting, or clearing |
| 272 bit 0 of such addresses. */ |
| 273 |
| 274 /* Return one iff compressed code is the MIPS16 instruction set. */ |
| 275 |
| 276 static int |
| 277 is_mips16_isa (struct gdbarch *gdbarch) |
| 278 { |
| 279 return gdbarch_tdep (gdbarch)->mips_isa == ISA_MIPS16; |
| 280 } |
| 281 |
| 282 /* Return one iff compressed code is the microMIPS instruction set. */ |
| 283 |
| 284 static int |
| 285 is_micromips_isa (struct gdbarch *gdbarch) |
| 286 { |
| 287 return gdbarch_tdep (gdbarch)->mips_isa == ISA_MICROMIPS; |
| 288 } |
| 289 |
| 290 /* Return one iff ADDR denotes compressed code. */ |
| 291 |
| 292 static int |
| 293 is_compact_addr (CORE_ADDR addr) |
| 294 { |
| 295 return ((addr) & 1); |
| 296 } |
| 297 |
| 298 /* Return one iff ADDR denotes standard ISA code. */ |
| 299 |
| 300 static int |
| 301 is_mips_addr (CORE_ADDR addr) |
| 302 { |
| 303 return !is_compact_addr (addr); |
| 304 } |
| 305 |
| 306 /* Return one iff ADDR denotes MIPS16 code. */ |
| 307 |
| 308 static int |
| 309 is_mips16_addr (struct gdbarch *gdbarch, CORE_ADDR addr) |
| 310 { |
| 311 return is_compact_addr (addr) && is_mips16_isa (gdbarch); |
| 312 } |
| 313 |
| 314 /* Return one iff ADDR denotes microMIPS code. */ |
| 315 |
| 316 static int |
| 317 is_micromips_addr (struct gdbarch *gdbarch, CORE_ADDR addr) |
| 318 { |
| 319 return is_compact_addr (addr) && is_micromips_isa (gdbarch); |
| 320 } |
| 321 |
| 322 /* Strip the ISA (compression) bit off from ADDR. */ |
| 323 |
| 324 static CORE_ADDR |
| 325 unmake_compact_addr (CORE_ADDR addr) |
| 326 { |
| 327 return ((addr) & ~(CORE_ADDR) 1); |
| 328 } |
| 329 |
| 330 /* Add the ISA (compression) bit to ADDR. */ |
| 331 |
| 332 static CORE_ADDR |
| 333 make_compact_addr (CORE_ADDR addr) |
| 334 { |
| 335 return ((addr) | (CORE_ADDR) 1); |
| 336 } |
| 337 |
258 /* Functions for setting and testing a bit in a minimal symbol that | 338 /* Functions for setting and testing a bit in a minimal symbol that |
259 marks it as 16-bit function. The MSB of the minimal symbol's | 339 marks it as MIPS16 or microMIPS function. The MSB of the minimal |
260 "info" field is used for this purpose. | 340 symbol's "info" field is used for this purpose. |
261 | 341 |
262 gdbarch_elf_make_msymbol_special tests whether an ELF symbol is "special", | 342 gdbarch_elf_make_msymbol_special tests whether an ELF symbol is |
263 i.e. refers to a 16-bit function, and sets a "special" bit in a | 343 "special", i.e. refers to a MIPS16 or microMIPS function, and sets |
264 minimal symbol to mark it as a 16-bit function | 344 one of the "special" bits in a minimal symbol to mark it accordingly. |
| 345 The test checks an ELF-private flag that is valid for true function |
| 346 symbols only; in particular synthetic symbols such as for PLT stubs |
| 347 have no ELF-private part at all. |
265 | 348 |
266 MSYMBOL_IS_SPECIAL tests the "special" bit in a minimal symbol */ | 349 msymbol_is_mips16 and msymbol_is_micromips test the "special" bit |
| 350 in a minimal symbol. */ |
267 | 351 |
268 static void | 352 static void |
269 mips_elf_make_msymbol_special (asymbol * sym, struct minimal_symbol *msym) | 353 mips_elf_make_msymbol_special (asymbol * sym, struct minimal_symbol *msym) |
270 { | 354 { |
271 if (((elf_symbol_type *) (sym))->internal_elf_sym.st_other == STO_MIPS16) | 355 elf_symbol_type *elfsym = (elf_symbol_type *) sym; |
272 { | 356 |
273 MSYMBOL_TARGET_FLAG_1 (msym) = 1; | 357 if ((sym->flags & BSF_SYNTHETIC) != 0) |
274 } | 358 return; |
| 359 |
| 360 if (ELF_ST_IS_MICROMIPS (elfsym->internal_elf_sym.st_other)) |
| 361 MSYMBOL_TARGET_FLAG_2 (msym) = 1; |
| 362 else if (ELF_ST_IS_MIPS16 (elfsym->internal_elf_sym.st_other)) |
| 363 MSYMBOL_TARGET_FLAG_1 (msym) = 1; |
275 } | 364 } |
276 | 365 |
| 366 /* Return one iff MSYM refers to standard ISA code. */ |
| 367 |
277 static int | 368 static int |
278 msymbol_is_special (struct minimal_symbol *msym) | 369 msymbol_is_mips (struct minimal_symbol *msym) |
| 370 { |
| 371 return !(MSYMBOL_TARGET_FLAG_1 (msym) | MSYMBOL_TARGET_FLAG_2 (msym)); |
| 372 } |
| 373 |
| 374 /* Return one iff MSYM refers to MIPS16 code. */ |
| 375 |
| 376 static int |
| 377 msymbol_is_mips16 (struct minimal_symbol *msym) |
279 { | 378 { |
280 return MSYMBOL_TARGET_FLAG_1 (msym); | 379 return MSYMBOL_TARGET_FLAG_1 (msym); |
281 } | 380 } |
282 | 381 |
| 382 /* Return one iff MSYM refers to microMIPS code. */ |
| 383 |
| 384 static int |
| 385 msymbol_is_micromips (struct minimal_symbol *msym) |
| 386 { |
| 387 return MSYMBOL_TARGET_FLAG_2 (msym); |
| 388 } |
| 389 |
283 /* XFER a value from the big/little/left end of the register. | 390 /* XFER a value from the big/little/left end of the register. |
284 Depending on the size of the value it might occupy the entire | 391 Depending on the size of the value it might occupy the entire |
285 register or just part of it. Make an allowance for this, aligning | 392 register or just part of it. Make an allowance for this, aligning |
286 things accordingly. */ | 393 things accordingly. */ |
287 | 394 |
288 static void | 395 static void |
289 mips_xfer_register (struct gdbarch *gdbarch, struct regcache *regcache, | 396 mips_xfer_register (struct gdbarch *gdbarch, struct regcache *regcache, |
290 int reg_num, int length, | 397 int reg_num, int length, |
291 enum bfd_endian endian, gdb_byte *in, | 398 enum bfd_endian endian, gdb_byte *in, |
292 const gdb_byte *out, int buf_offset) | 399 const gdb_byte *out, int buf_offset) |
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383 { NUM_MIPS_PROCESSOR_REGS = (90 - 32) }; | 490 { NUM_MIPS_PROCESSOR_REGS = (90 - 32) }; |
384 | 491 |
385 /* Generic MIPS. */ | 492 /* Generic MIPS. */ |
386 | 493 |
387 static const char *mips_generic_reg_names[NUM_MIPS_PROCESSOR_REGS] = { | 494 static const char *mips_generic_reg_names[NUM_MIPS_PROCESSOR_REGS] = { |
388 "sr", "lo", "hi", "bad", "cause", "pc", | 495 "sr", "lo", "hi", "bad", "cause", "pc", |
389 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", | 496 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", |
390 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | 497 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", |
391 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | 498 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", |
392 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | 499 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", |
393 "fsr", "fir", "" /*"fp" */ , "", | 500 "fsr", "fir", |
394 "", "", "", "", "", "", "", "", | |
395 "", "", "", "", "", "", "", "", | |
396 }; | 501 }; |
397 | 502 |
398 /* Names of IDT R3041 registers. */ | 503 /* Names of IDT R3041 registers. */ |
399 | 504 |
400 static const char *mips_r3041_reg_names[] = { | 505 static const char *mips_r3041_reg_names[] = { |
401 "sr", "lo", "hi", "bad", "cause", "pc", | 506 "sr", "lo", "hi", "bad", "cause", "pc", |
402 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", | 507 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", |
403 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | 508 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", |
404 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | 509 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", |
405 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | 510 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", |
406 "fsr", "fir", "", /*"fp" */ "", | 511 "fsr", "fir", "", /*"fp" */ "", |
407 "", "", "bus", "ccfg", "", "", "", "", | 512 "", "", "bus", "ccfg", "", "", "", "", |
408 "", "", "port", "cmp", "", "", "epc", "prid", | 513 "", "", "port", "cmp", "", "", "epc", "prid", |
409 }; | 514 }; |
410 | 515 |
411 /* Names of tx39 registers. */ | 516 /* Names of tx39 registers. */ |
412 | 517 |
413 static const char *mips_tx39_reg_names[NUM_MIPS_PROCESSOR_REGS] = { | 518 static const char *mips_tx39_reg_names[NUM_MIPS_PROCESSOR_REGS] = { |
414 "sr", "lo", "hi", "bad", "cause", "pc", | 519 "sr", "lo", "hi", "bad", "cause", "pc", |
415 "", "", "", "", "", "", "", "", | 520 "", "", "", "", "", "", "", "", |
416 "", "", "", "", "", "", "", "", | 521 "", "", "", "", "", "", "", "", |
417 "", "", "", "", "", "", "", "", | 522 "", "", "", "", "", "", "", "", |
418 "", "", "", "", "", "", "", "", | 523 "", "", "", "", "", "", "", "", |
419 "", "", "", "", | 524 "", "", "", "", |
420 "", "", "", "", "", "", "", "", | 525 "", "", "", "", "", "", "", "", |
421 "", "", "config", "cache", "debug", "depc", "epc", "" | 526 "", "", "config", "cache", "debug", "depc", "epc", |
422 }; | 527 }; |
423 | 528 |
424 /* Names of IRIX registers. */ | 529 /* Names of IRIX registers. */ |
425 static const char *mips_irix_reg_names[NUM_MIPS_PROCESSOR_REGS] = { | 530 static const char *mips_irix_reg_names[NUM_MIPS_PROCESSOR_REGS] = { |
426 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", | 531 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", |
427 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", | 532 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", |
428 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", | 533 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", |
429 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", | 534 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", |
430 "pc", "cause", "bad", "hi", "lo", "fsr", "fir" | 535 "pc", "cause", "bad", "hi", "lo", "fsr", "fir" |
431 }; | 536 }; |
432 | 537 |
| 538 /* Names of registers with Linux kernels. */ |
| 539 static const char *mips_linux_reg_names[NUM_MIPS_PROCESSOR_REGS] = { |
| 540 "sr", "lo", "hi", "bad", "cause", "pc", |
| 541 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", |
| 542 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", |
| 543 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", |
| 544 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", |
| 545 "fsr", "fir" |
| 546 }; |
| 547 |
433 | 548 |
434 /* Return the name of the register corresponding to REGNO. */ | 549 /* Return the name of the register corresponding to REGNO. */ |
435 static const char * | 550 static const char * |
436 mips_register_name (struct gdbarch *gdbarch, int regno) | 551 mips_register_name (struct gdbarch *gdbarch, int regno) |
437 { | 552 { |
438 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | 553 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
439 /* GPR names for all ABIs other than n32/n64. */ | 554 /* GPR names for all ABIs other than n32/n64. */ |
440 static char *mips_gpr_names[] = { | 555 static char *mips_gpr_names[] = { |
441 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", | 556 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", |
442 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", | 557 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", |
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477 if (abi == MIPS_ABI_N32 || abi == MIPS_ABI_N64) | 592 if (abi == MIPS_ABI_N32 || abi == MIPS_ABI_N64) |
478 return mips_n32_n64_gpr_names[rawnum]; | 593 return mips_n32_n64_gpr_names[rawnum]; |
479 else | 594 else |
480 return mips_gpr_names[rawnum]; | 595 return mips_gpr_names[rawnum]; |
481 } | 596 } |
482 else if (tdesc_has_registers (gdbarch_target_desc (gdbarch))) | 597 else if (tdesc_has_registers (gdbarch_target_desc (gdbarch))) |
483 return tdesc_register_name (gdbarch, rawnum); | 598 return tdesc_register_name (gdbarch, rawnum); |
484 else if (32 <= rawnum && rawnum < gdbarch_num_regs (gdbarch)) | 599 else if (32 <= rawnum && rawnum < gdbarch_num_regs (gdbarch)) |
485 { | 600 { |
486 gdb_assert (rawnum - 32 < NUM_MIPS_PROCESSOR_REGS); | 601 gdb_assert (rawnum - 32 < NUM_MIPS_PROCESSOR_REGS); |
487 return tdep->mips_processor_reg_names[rawnum - 32]; | 602 if (tdep->mips_processor_reg_names[rawnum - 32]) |
| 603 » return tdep->mips_processor_reg_names[rawnum - 32]; |
| 604 return ""; |
488 } | 605 } |
489 else | 606 else |
490 internal_error (__FILE__, __LINE__, | 607 internal_error (__FILE__, __LINE__, |
491 _("mips_register_name: bad register number %d"), rawnum); | 608 _("mips_register_name: bad register number %d"), rawnum); |
492 } | 609 } |
493 | 610 |
494 /* Return the groups that a MIPS register can be categorised into. */ | 611 /* Return the groups that a MIPS register can be categorised into. */ |
495 | 612 |
496 static int | 613 static int |
497 mips_register_reggroup_p (struct gdbarch *gdbarch, int regnum, | 614 mips_register_reggroup_p (struct gdbarch *gdbarch, int regnum, |
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656 ax_const_l (ax, 32); | 773 ax_const_l (ax, 32); |
657 ax_simple (ax, aop_rsh_signed); | 774 ax_simple (ax, aop_rsh_signed); |
658 } | 775 } |
659 } | 776 } |
660 else | 777 else |
661 internal_error (__FILE__, __LINE__, _("bad register size")); | 778 internal_error (__FILE__, __LINE__, _("bad register size")); |
662 | 779 |
663 return 0; | 780 return 0; |
664 } | 781 } |
665 | 782 |
666 /* Table to translate MIPS16 register field to actual register number. */ | 783 /* Table to translate 3-bit register field to actual register number. */ |
667 static int mips16_to_32_reg[8] = { 16, 17, 2, 3, 4, 5, 6, 7 }; | 784 static const signed char mips_reg3_to_reg[8] = { 16, 17, 2, 3, 4, 5, 6, 7 }; |
668 | 785 |
669 /* Heuristic_proc_start may hunt through the text section for a long | 786 /* Heuristic_proc_start may hunt through the text section for a long |
670 time across a 2400 baud serial line. Allows the user to limit this | 787 time across a 2400 baud serial line. Allows the user to limit this |
671 search. */ | 788 search. */ |
672 | 789 |
673 static unsigned int heuristic_fence_post = 0; | 790 static unsigned int heuristic_fence_post = 0; |
674 | 791 |
675 /* Number of bytes of storage in the actual machine representation for | 792 /* Number of bytes of storage in the actual machine representation for |
676 register N. NOTE: This defines the pseudo register type so need to | 793 register N. NOTE: This defines the pseudo register type so need to |
677 rebuild the architecture vector. */ | 794 rebuild the architecture vector. */ |
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699 /* This predicate tests for the case of an 8 byte floating point | 816 /* This predicate tests for the case of an 8 byte floating point |
700 value that is being transferred to or from a pair of floating point | 817 value that is being transferred to or from a pair of floating point |
701 registers each of which are (or are considered to be) only 4 bytes | 818 registers each of which are (or are considered to be) only 4 bytes |
702 wide. */ | 819 wide. */ |
703 static int | 820 static int |
704 mips_convert_register_float_case_p (struct gdbarch *gdbarch, int regnum, | 821 mips_convert_register_float_case_p (struct gdbarch *gdbarch, int regnum, |
705 struct type *type) | 822 struct type *type) |
706 { | 823 { |
707 return (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG | 824 return (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG |
708 && register_size (gdbarch, regnum) == 4 | 825 && register_size (gdbarch, regnum) == 4 |
709 » && (regnum % gdbarch_num_regs (gdbarch)) | 826 » && mips_float_register_p (gdbarch, regnum) |
710 » » >= mips_regnum (gdbarch)->fp0 | |
711 » && (regnum % gdbarch_num_regs (gdbarch)) | |
712 » » < mips_regnum (gdbarch)->fp0 + 32 | |
713 && TYPE_CODE (type) == TYPE_CODE_FLT && TYPE_LENGTH (type) == 8); | 827 && TYPE_CODE (type) == TYPE_CODE_FLT && TYPE_LENGTH (type) == 8); |
714 } | 828 } |
715 | 829 |
716 /* This predicate tests for the case of a value of less than 8 | 830 /* This predicate tests for the case of a value of less than 8 |
717 bytes in width that is being transfered to or from an 8 byte | 831 bytes in width that is being transfered to or from an 8 byte |
718 general purpose register. */ | 832 general purpose register. */ |
719 static int | 833 static int |
720 mips_convert_register_gpreg_case_p (struct gdbarch *gdbarch, int regnum, | 834 mips_convert_register_gpreg_case_p (struct gdbarch *gdbarch, int regnum, |
721 struct type *type) | 835 struct type *type) |
722 { | 836 { |
723 int num_regs = gdbarch_num_regs (gdbarch); | 837 int num_regs = gdbarch_num_regs (gdbarch); |
724 | 838 |
725 return (register_size (gdbarch, regnum) == 8 | 839 return (register_size (gdbarch, regnum) == 8 |
726 && regnum % num_regs > 0 && regnum % num_regs < 32 | 840 && regnum % num_regs > 0 && regnum % num_regs < 32 |
727 && TYPE_LENGTH (type) < 8); | 841 && TYPE_LENGTH (type) < 8); |
728 } | 842 } |
729 | 843 |
730 static int | 844 static int |
731 mips_convert_register_p (struct gdbarch *gdbarch, | 845 mips_convert_register_p (struct gdbarch *gdbarch, |
732 int regnum, struct type *type) | 846 int regnum, struct type *type) |
733 { | 847 { |
734 return mips_convert_register_float_case_p (gdbarch, regnum, type) | 848 return (mips_convert_register_float_case_p (gdbarch, regnum, type) |
735 || mips_convert_register_gpreg_case_p (gdbarch, regnum, type); | 849 » || mips_convert_register_gpreg_case_p (gdbarch, regnum, type)); |
736 } | 850 } |
737 | 851 |
738 static int | 852 static int |
739 mips_register_to_value (struct frame_info *frame, int regnum, | 853 mips_register_to_value (struct frame_info *frame, int regnum, |
740 struct type *type, gdb_byte *to, | 854 struct type *type, gdb_byte *to, |
741 int *optimizedp, int *unavailablep) | 855 int *optimizedp, int *unavailablep) |
742 { | 856 { |
743 struct gdbarch *gdbarch = get_frame_arch (frame); | 857 struct gdbarch *gdbarch = get_frame_arch (frame); |
744 | 858 |
745 if (mips_convert_register_float_case_p (gdbarch, regnum, type)) | 859 if (mips_convert_register_float_case_p (gdbarch, regnum, type)) |
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825 } | 939 } |
826 } | 940 } |
827 | 941 |
828 /* Return the GDB type object for the "standard" data type of data in | 942 /* Return the GDB type object for the "standard" data type of data in |
829 register REG. */ | 943 register REG. */ |
830 | 944 |
831 static struct type * | 945 static struct type * |
832 mips_register_type (struct gdbarch *gdbarch, int regnum) | 946 mips_register_type (struct gdbarch *gdbarch, int regnum) |
833 { | 947 { |
834 gdb_assert (regnum >= 0 && regnum < 2 * gdbarch_num_regs (gdbarch)); | 948 gdb_assert (regnum >= 0 && regnum < 2 * gdbarch_num_regs (gdbarch)); |
835 if ((regnum % gdbarch_num_regs (gdbarch)) >= mips_regnum (gdbarch)->fp0 | 949 if (mips_float_register_p (gdbarch, regnum)) |
836 && (regnum % gdbarch_num_regs (gdbarch)) | |
837 » < mips_regnum (gdbarch)->fp0 + 32) | |
838 { | 950 { |
839 /* The floating-point registers raw, or cooked, always match | 951 /* The floating-point registers raw, or cooked, always match |
840 mips_isa_regsize(), and also map 1:1, byte for byte. */ | 952 mips_isa_regsize(), and also map 1:1, byte for byte. */ |
841 if (mips_isa_regsize (gdbarch) == 4) | 953 if (mips_isa_regsize (gdbarch) == 4) |
842 return builtin_type (gdbarch)->builtin_float; | 954 return builtin_type (gdbarch)->builtin_float; |
843 else | 955 else |
844 return builtin_type (gdbarch)->builtin_double; | 956 return builtin_type (gdbarch)->builtin_double; |
845 } | 957 } |
846 else if (regnum < gdbarch_num_regs (gdbarch)) | 958 else if (regnum < gdbarch_num_regs (gdbarch)) |
847 { | 959 { |
848 /* The raw or ISA registers. These are all sized according to | 960 /* The raw or ISA registers. These are all sized according to |
849 the ISA regsize. */ | 961 the ISA regsize. */ |
850 if (mips_isa_regsize (gdbarch) == 4) | 962 if (mips_isa_regsize (gdbarch) == 4) |
851 return builtin_type (gdbarch)->builtin_int32; | 963 return builtin_type (gdbarch)->builtin_int32; |
852 else | 964 else |
853 return builtin_type (gdbarch)->builtin_int64; | 965 return builtin_type (gdbarch)->builtin_int64; |
854 } | 966 } |
855 else | 967 else |
856 { | 968 { |
| 969 int rawnum = regnum - gdbarch_num_regs (gdbarch); |
| 970 |
857 /* The cooked or ABI registers. These are sized according to | 971 /* The cooked or ABI registers. These are sized according to |
858 the ABI (with a few complications). */ | 972 the ABI (with a few complications). */ |
859 if (regnum >= (gdbarch_num_regs (gdbarch) | 973 if (rawnum == mips_regnum (gdbarch)->fp_control_status |
860 » » + mips_regnum (gdbarch)->fp_control_status) | 974 » || rawnum == mips_regnum (gdbarch)->fp_implementation_revision) |
861 » && regnum <= gdbarch_num_regs (gdbarch) + MIPS_LAST_EMBED_REGNUM) | 975 » return builtin_type (gdbarch)->builtin_int32; |
| 976 else if (gdbarch_osabi (gdbarch) != GDB_OSABI_IRIX |
| 977 » && gdbarch_osabi (gdbarch) != GDB_OSABI_LINUX |
| 978 » && rawnum >= MIPS_FIRST_EMBED_REGNUM |
| 979 » && rawnum <= MIPS_LAST_EMBED_REGNUM) |
862 /* The pseudo/cooked view of the embedded registers is always | 980 /* The pseudo/cooked view of the embedded registers is always |
863 32-bit. The raw view is handled below. */ | 981 32-bit. The raw view is handled below. */ |
864 return builtin_type (gdbarch)->builtin_int32; | 982 return builtin_type (gdbarch)->builtin_int32; |
865 else if (gdbarch_tdep (gdbarch)->mips64_transfers_32bit_regs_p) | 983 else if (gdbarch_tdep (gdbarch)->mips64_transfers_32bit_regs_p) |
866 /* The target, while possibly using a 64-bit register buffer, | 984 /* The target, while possibly using a 64-bit register buffer, |
867 is only transfering 32-bits of each integer register. | 985 is only transfering 32-bits of each integer register. |
868 Reflect this in the cooked/pseudo (ABI) register value. */ | 986 Reflect this in the cooked/pseudo (ABI) register value. */ |
869 return builtin_type (gdbarch)->builtin_int32; | 987 return builtin_type (gdbarch)->builtin_int32; |
870 else if (mips_abi_regsize (gdbarch) == 4) | 988 else if (mips_abi_regsize (gdbarch) == 4) |
871 /* The ABI is restricted to 32-bit registers (the ISA could be | 989 /* The ABI is restricted to 32-bit registers (the ISA could be |
872 32- or 64-bit). */ | 990 32- or 64-bit). */ |
873 return builtin_type (gdbarch)->builtin_int32; | 991 return builtin_type (gdbarch)->builtin_int32; |
874 else | 992 else |
875 /* 64-bit ABI. */ | 993 /* 64-bit ABI. */ |
876 return builtin_type (gdbarch)->builtin_int64; | 994 return builtin_type (gdbarch)->builtin_int64; |
877 } | 995 } |
878 } | 996 } |
879 | 997 |
880 /* Return the GDB type for the pseudo register REGNUM, which is the | 998 /* Return the GDB type for the pseudo register REGNUM, which is the |
881 ABI-level view. This function is only called if there is a target | 999 ABI-level view. This function is only called if there is a target |
882 description which includes registers, so we know precisely the | 1000 description which includes registers, so we know precisely the |
883 types of hardware registers. */ | 1001 types of hardware registers. */ |
884 | 1002 |
885 static struct type * | 1003 static struct type * |
886 mips_pseudo_register_type (struct gdbarch *gdbarch, int regnum) | 1004 mips_pseudo_register_type (struct gdbarch *gdbarch, int regnum) |
887 { | 1005 { |
888 const int num_regs = gdbarch_num_regs (gdbarch); | 1006 const int num_regs = gdbarch_num_regs (gdbarch); |
889 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
890 int rawnum = regnum % num_regs; | 1007 int rawnum = regnum % num_regs; |
891 struct type *rawtype; | 1008 struct type *rawtype; |
892 | 1009 |
893 gdb_assert (regnum >= num_regs && regnum < 2 * num_regs); | 1010 gdb_assert (regnum >= num_regs && regnum < 2 * num_regs); |
894 | 1011 |
895 /* Absent registers are still absent. */ | 1012 /* Absent registers are still absent. */ |
896 rawtype = gdbarch_register_type (gdbarch, rawnum); | 1013 rawtype = gdbarch_register_type (gdbarch, rawnum); |
897 if (TYPE_LENGTH (rawtype) == 0) | 1014 if (TYPE_LENGTH (rawtype) == 0) |
898 return rawtype; | 1015 return rawtype; |
899 | 1016 |
900 if (rawnum >= MIPS_EMBED_FP0_REGNUM && rawnum < MIPS_EMBED_FP0_REGNUM + 32) | 1017 if (mips_float_register_p (gdbarch, rawnum)) |
901 /* Present the floating point registers however the hardware did; | 1018 /* Present the floating point registers however the hardware did; |
902 do not try to convert between FPU layouts. */ | 1019 do not try to convert between FPU layouts. */ |
903 return rawtype; | 1020 return rawtype; |
904 | 1021 |
905 if (rawnum >= MIPS_EMBED_FP0_REGNUM + 32 && rawnum <= MIPS_LAST_EMBED_REGNUM) | 1022 /* Use pointer types for registers if we can. For n32 we can not, |
| 1023 since we do not have a 64-bit pointer type. */ |
| 1024 if (mips_abi_regsize (gdbarch) |
| 1025 == TYPE_LENGTH (builtin_type (gdbarch)->builtin_data_ptr)) |
| 1026 { |
| 1027 if (rawnum == MIPS_SP_REGNUM |
| 1028 » || rawnum == mips_regnum (gdbarch)->badvaddr) |
| 1029 » return builtin_type (gdbarch)->builtin_data_ptr; |
| 1030 else if (rawnum == mips_regnum (gdbarch)->pc) |
| 1031 » return builtin_type (gdbarch)->builtin_func_ptr; |
| 1032 } |
| 1033 |
| 1034 if (mips_abi_regsize (gdbarch) == 4 && TYPE_LENGTH (rawtype) == 8 |
| 1035 && ((rawnum >= MIPS_ZERO_REGNUM && rawnum <= MIPS_PS_REGNUM) |
| 1036 » || rawnum == mips_regnum (gdbarch)->lo |
| 1037 » || rawnum == mips_regnum (gdbarch)->hi |
| 1038 » || rawnum == mips_regnum (gdbarch)->badvaddr |
| 1039 » || rawnum == mips_regnum (gdbarch)->cause |
| 1040 » || rawnum == mips_regnum (gdbarch)->pc |
| 1041 » || (mips_regnum (gdbarch)->dspacc != -1 |
| 1042 » && rawnum >= mips_regnum (gdbarch)->dspacc |
| 1043 » && rawnum < mips_regnum (gdbarch)->dspacc + 6))) |
| 1044 return builtin_type (gdbarch)->builtin_int32; |
| 1045 |
| 1046 if (gdbarch_osabi (gdbarch) != GDB_OSABI_IRIX |
| 1047 && gdbarch_osabi (gdbarch) != GDB_OSABI_LINUX |
| 1048 && rawnum >= MIPS_EMBED_FP0_REGNUM + 32 |
| 1049 && rawnum <= MIPS_LAST_EMBED_REGNUM) |
906 { | 1050 { |
907 /* The pseudo/cooked view of embedded registers is always | 1051 /* The pseudo/cooked view of embedded registers is always |
908 32-bit, even if the target transfers 64-bit values for them. | 1052 32-bit, even if the target transfers 64-bit values for them. |
909 New targets relying on XML descriptions should only transfer | 1053 New targets relying on XML descriptions should only transfer |
910 the necessary 32 bits, but older versions of GDB expected 64, | 1054 the necessary 32 bits, but older versions of GDB expected 64, |
911 so allow the target to provide 64 bits without interfering | 1055 so allow the target to provide 64 bits without interfering |
912 with the displayed type. */ | 1056 with the displayed type. */ |
913 return builtin_type (gdbarch)->builtin_int32; | 1057 return builtin_type (gdbarch)->builtin_int32; |
914 } | 1058 } |
915 | 1059 |
916 /* Use pointer types for registers if we can. For n32 we can not, | |
917 since we do not have a 64-bit pointer type. */ | |
918 if (mips_abi_regsize (gdbarch) | |
919 == TYPE_LENGTH (builtin_type (gdbarch)->builtin_data_ptr)) | |
920 { | |
921 if (rawnum == MIPS_SP_REGNUM || rawnum == MIPS_EMBED_BADVADDR_REGNUM) | |
922 return builtin_type (gdbarch)->builtin_data_ptr; | |
923 else if (rawnum == MIPS_EMBED_PC_REGNUM) | |
924 return builtin_type (gdbarch)->builtin_func_ptr; | |
925 } | |
926 | |
927 if (mips_abi_regsize (gdbarch) == 4 && TYPE_LENGTH (rawtype) == 8 | |
928 && rawnum >= MIPS_ZERO_REGNUM && rawnum <= MIPS_EMBED_PC_REGNUM) | |
929 return builtin_type (gdbarch)->builtin_int32; | |
930 | |
931 /* For all other registers, pass through the hardware type. */ | 1060 /* For all other registers, pass through the hardware type. */ |
932 return rawtype; | 1061 return rawtype; |
933 } | 1062 } |
934 | 1063 |
935 /* Should the upper word of 64-bit addresses be zeroed? */ | 1064 /* Should the upper word of 64-bit addresses be zeroed? */ |
936 enum auto_boolean mask_address_var = AUTO_BOOLEAN_AUTO; | 1065 enum auto_boolean mask_address_var = AUTO_BOOLEAN_AUTO; |
937 | 1066 |
938 static int | 1067 static int |
939 mips_mask_address_p (struct gdbarch_tdep *tdep) | 1068 mips_mask_address_p (struct gdbarch_tdep *tdep) |
940 { | 1069 { |
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973 printf_filtered | 1102 printf_filtered |
974 ("The 32 bit address mask is set automatically. Currently %s\n", | 1103 ("The 32 bit address mask is set automatically. Currently %s\n", |
975 mips_mask_address_p (tdep) ? "enabled" : "disabled"); | 1104 mips_mask_address_p (tdep) ? "enabled" : "disabled"); |
976 break; | 1105 break; |
977 default: | 1106 default: |
978 internal_error (__FILE__, __LINE__, _("show_mask_address: bad switch")); | 1107 internal_error (__FILE__, __LINE__, _("show_mask_address: bad switch")); |
979 break; | 1108 break; |
980 } | 1109 } |
981 } | 1110 } |
982 | 1111 |
| 1112 /* Tell if the program counter value in MEMADDR is in a standard ISA |
| 1113 function. */ |
| 1114 |
| 1115 int |
| 1116 mips_pc_is_mips (CORE_ADDR memaddr) |
| 1117 { |
| 1118 struct minimal_symbol *sym; |
| 1119 |
| 1120 /* Flags indicating that this is a MIPS16 or microMIPS function is |
| 1121 stored by elfread.c in the high bit of the info field. Use this |
| 1122 to decide if the function is standard MIPS. Otherwise if bit 0 |
| 1123 of the address is clear, then this is a standard MIPS function. */ |
| 1124 sym = lookup_minimal_symbol_by_pc (memaddr); |
| 1125 if (sym) |
| 1126 return msymbol_is_mips (sym); |
| 1127 else |
| 1128 return is_mips_addr (memaddr); |
| 1129 } |
| 1130 |
983 /* Tell if the program counter value in MEMADDR is in a MIPS16 function. */ | 1131 /* Tell if the program counter value in MEMADDR is in a MIPS16 function. */ |
984 | 1132 |
985 int | 1133 int |
986 mips_pc_is_mips16 (CORE_ADDR memaddr) | 1134 mips_pc_is_mips16 (struct gdbarch *gdbarch, CORE_ADDR memaddr) |
987 { | 1135 { |
988 struct minimal_symbol *sym; | 1136 struct minimal_symbol *sym; |
989 | 1137 |
990 /* A flag indicating that this is a MIPS16 function is stored by | 1138 /* A flag indicating that this is a MIPS16 function is stored by |
991 elfread.c in the high bit of the info field. Use this to decide | 1139 elfread.c in the high bit of the info field. Use this to decide |
992 if the function is MIPS16 or normal MIPS. Otherwise if bit 0 of | 1140 if the function is MIPS16. Otherwise if bit 0 of the address is |
993 the address is set, assume this is a MIPS16 address. */ | 1141 set, then ELF file flags will tell if this is a MIPS16 function. */ |
994 sym = lookup_minimal_symbol_by_pc (memaddr); | 1142 sym = lookup_minimal_symbol_by_pc (memaddr); |
995 if (sym) | 1143 if (sym) |
996 return msymbol_is_special (sym); | 1144 return msymbol_is_mips16 (sym); |
997 else | 1145 else |
998 return is_mips16_addr (memaddr); | 1146 return is_mips16_addr (gdbarch, memaddr); |
| 1147 } |
| 1148 |
| 1149 /* Tell if the program counter value in MEMADDR is in a microMIPS function. */ |
| 1150 |
| 1151 int |
| 1152 mips_pc_is_micromips (struct gdbarch *gdbarch, CORE_ADDR memaddr) |
| 1153 { |
| 1154 struct minimal_symbol *sym; |
| 1155 |
| 1156 /* A flag indicating that this is a microMIPS function is stored by |
| 1157 elfread.c in the high bit of the info field. Use this to decide |
| 1158 if the function is microMIPS. Otherwise if bit 0 of the address |
| 1159 is set, then ELF file flags will tell if this is a microMIPS |
| 1160 function. */ |
| 1161 sym = lookup_minimal_symbol_by_pc (memaddr); |
| 1162 if (sym) |
| 1163 return msymbol_is_micromips (sym); |
| 1164 else |
| 1165 return is_micromips_addr (gdbarch, memaddr); |
| 1166 } |
| 1167 |
| 1168 /* Tell the ISA type of the function the program counter value in MEMADDR |
| 1169 is in. */ |
| 1170 |
| 1171 static enum mips_isa |
| 1172 mips_pc_isa (struct gdbarch *gdbarch, CORE_ADDR memaddr) |
| 1173 { |
| 1174 struct minimal_symbol *sym; |
| 1175 |
| 1176 /* A flag indicating that this is a MIPS16 or a microMIPS function |
| 1177 is stored by elfread.c in the high bit of the info field. Use |
| 1178 this to decide if the function is MIPS16 or microMIPS or normal |
| 1179 MIPS. Otherwise if bit 0 of the address is set, then ELF file |
| 1180 flags will tell if this is a MIPS16 or a microMIPS function. */ |
| 1181 sym = lookup_minimal_symbol_by_pc (memaddr); |
| 1182 if (sym) |
| 1183 { |
| 1184 if (msymbol_is_micromips (sym)) |
| 1185 » return ISA_MICROMIPS; |
| 1186 else if (msymbol_is_mips16 (sym)) |
| 1187 » return ISA_MIPS16; |
| 1188 else |
| 1189 » return ISA_MIPS; |
| 1190 } |
| 1191 else |
| 1192 { |
| 1193 if (is_mips_addr (memaddr)) |
| 1194 » return ISA_MIPS; |
| 1195 else if (is_micromips_addr (gdbarch, memaddr)) |
| 1196 » return ISA_MICROMIPS; |
| 1197 else |
| 1198 » return ISA_MIPS16; |
| 1199 } |
| 1200 } |
| 1201 |
| 1202 /* Various MIPS16 thunk (aka stub or trampoline) names. */ |
| 1203 |
| 1204 static const char mips_str_mips16_call_stub[] = "__mips16_call_stub_"; |
| 1205 static const char mips_str_mips16_ret_stub[] = "__mips16_ret_"; |
| 1206 static const char mips_str_call_fp_stub[] = "__call_stub_fp_"; |
| 1207 static const char mips_str_call_stub[] = "__call_stub_"; |
| 1208 static const char mips_str_fn_stub[] = "__fn_stub_"; |
| 1209 |
| 1210 /* This is used as a PIC thunk prefix. */ |
| 1211 |
| 1212 static const char mips_str_pic[] = ".pic."; |
| 1213 |
| 1214 /* Return non-zero if the PC is inside a call thunk (aka stub or |
| 1215 trampoline) that should be treated as a temporary frame. */ |
| 1216 |
| 1217 static int |
| 1218 mips_in_frame_stub (CORE_ADDR pc) |
| 1219 { |
| 1220 CORE_ADDR start_addr; |
| 1221 const char *name; |
| 1222 |
| 1223 /* Find the starting address of the function containing the PC. */ |
| 1224 if (find_pc_partial_function (pc, &name, &start_addr, NULL) == 0) |
| 1225 return 0; |
| 1226 |
| 1227 /* If the PC is in __mips16_call_stub_*, this is a call/return stub. */ |
| 1228 if (strncmp (name, mips_str_mips16_call_stub, |
| 1229 » strlen (mips_str_mips16_call_stub)) == 0) |
| 1230 return 1; |
| 1231 /* If the PC is in __call_stub_*, this is a call/return or a call stub. */ |
| 1232 if (strncmp (name, mips_str_call_stub, strlen (mips_str_call_stub)) == 0) |
| 1233 return 1; |
| 1234 /* If the PC is in __fn_stub_*, this is a call stub. */ |
| 1235 if (strncmp (name, mips_str_fn_stub, strlen (mips_str_fn_stub)) == 0) |
| 1236 return 1; |
| 1237 |
| 1238 return 0;» » » /* Not a stub. */ |
999 } | 1239 } |
1000 | 1240 |
1001 /* MIPS believes that the PC has a sign extended value. Perhaps the | 1241 /* MIPS believes that the PC has a sign extended value. Perhaps the |
1002 all registers should be sign extended for simplicity? */ | 1242 all registers should be sign extended for simplicity? */ |
1003 | 1243 |
1004 static CORE_ADDR | 1244 static CORE_ADDR |
1005 mips_read_pc (struct regcache *regcache) | 1245 mips_read_pc (struct regcache *regcache) |
1006 { | 1246 { |
| 1247 int regnum = gdbarch_pc_regnum (get_regcache_arch (regcache)); |
1007 ULONGEST pc; | 1248 ULONGEST pc; |
1008 int regnum = mips_regnum (get_regcache_arch (regcache))->pc; | 1249 |
1009 regcache_cooked_read_signed (regcache, regnum, &pc); | 1250 regcache_cooked_read_signed (regcache, regnum, &pc); |
1010 if (is_mips16_addr (pc)) | 1251 if (is_compact_addr (pc)) |
1011 pc = unmake_mips16_addr (pc); | 1252 pc = unmake_compact_addr (pc); |
1012 return pc; | 1253 return pc; |
1013 } | 1254 } |
1014 | 1255 |
1015 static CORE_ADDR | 1256 static CORE_ADDR |
1016 mips_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame) | 1257 mips_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame) |
1017 { | 1258 { |
1018 ULONGEST pc; | 1259 CORE_ADDR pc; |
1019 | 1260 |
1020 pc = frame_unwind_register_signed | 1261 pc = frame_unwind_register_signed (next_frame, gdbarch_pc_regnum (gdbarch)); |
1021 » (next_frame, gdbarch_num_regs (gdbarch) + mips_regnum (gdbarch)->pc); | 1262 if (is_compact_addr (pc)) |
1022 if (is_mips16_addr (pc)) | 1263 pc = unmake_compact_addr (pc); |
1023 pc = unmake_mips16_addr (pc); | 1264 /* macro/2012-04-20: This hack skips over MIPS16 call thunks as |
| 1265 intermediate frames. In this case we can get the caller's address |
| 1266 from $ra, or if $ra contains an address within a thunk as well, then |
| 1267 it must be in the return path of __mips16_call_stub_{s,d}{f,c}_{0..10} |
| 1268 and thus the caller's address is in $s2. */ |
| 1269 if (frame_relative_level (next_frame) >= 0 && mips_in_frame_stub (pc)) |
| 1270 { |
| 1271 pc = frame_unwind_register_signed |
| 1272 » (next_frame, gdbarch_num_regs (gdbarch) + MIPS_RA_REGNUM); |
| 1273 if (is_compact_addr (pc)) |
| 1274 » pc = unmake_compact_addr (pc); |
| 1275 if (mips_in_frame_stub (pc)) |
| 1276 » { |
| 1277 » pc = frame_unwind_register_signed |
| 1278 » » (next_frame, gdbarch_num_regs (gdbarch) + MIPS_S2_REGNUM); |
| 1279 » if (is_compact_addr (pc)) |
| 1280 » pc = unmake_compact_addr (pc); |
| 1281 » } |
| 1282 } |
1024 return pc; | 1283 return pc; |
1025 } | 1284 } |
1026 | 1285 |
1027 static CORE_ADDR | 1286 static CORE_ADDR |
1028 mips_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame) | 1287 mips_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame) |
1029 { | 1288 { |
1030 return frame_unwind_register_signed | 1289 return frame_unwind_register_signed |
1031 (next_frame, gdbarch_num_regs (gdbarch) + MIPS_SP_REGNUM); | 1290 (next_frame, gdbarch_num_regs (gdbarch) + MIPS_SP_REGNUM); |
1032 } | 1291 } |
1033 | 1292 |
1034 /* Assuming THIS_FRAME is a dummy, return the frame ID of that | 1293 /* Assuming THIS_FRAME is a dummy, return the frame ID of that |
1035 dummy frame. The frame ID's base needs to match the TOS value | 1294 dummy frame. The frame ID's base needs to match the TOS value |
1036 saved by save_dummy_frame_tos(), and the PC match the dummy frame's | 1295 saved by save_dummy_frame_tos(), and the PC match the dummy frame's |
1037 breakpoint. */ | 1296 breakpoint. */ |
1038 | 1297 |
1039 static struct frame_id | 1298 static struct frame_id |
1040 mips_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame) | 1299 mips_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame) |
1041 { | 1300 { |
1042 return frame_id_build | 1301 return frame_id_build |
1043 (get_frame_register_signed (this_frame, | 1302 (get_frame_register_signed (this_frame, |
1044 gdbarch_num_regs (gdbarch) | 1303 gdbarch_num_regs (gdbarch) |
1045 + MIPS_SP_REGNUM), | 1304 + MIPS_SP_REGNUM), |
1046 get_frame_pc (this_frame)); | 1305 get_frame_pc (this_frame)); |
1047 } | 1306 } |
1048 | 1307 |
1049 static void | 1308 /* Implement the "write_pc" gdbarch method. */ |
| 1309 |
| 1310 void |
1050 mips_write_pc (struct regcache *regcache, CORE_ADDR pc) | 1311 mips_write_pc (struct regcache *regcache, CORE_ADDR pc) |
1051 { | 1312 { |
1052 int regnum = mips_regnum (get_regcache_arch (regcache))->pc; | 1313 int regnum = gdbarch_pc_regnum (get_regcache_arch (regcache)); |
1053 if (mips_pc_is_mips16 (pc)) | 1314 |
1054 regcache_cooked_write_unsigned (regcache, regnum, make_mips16_addr (pc)); | 1315 if (mips_pc_is_mips (pc)) |
| 1316 regcache_cooked_write_unsigned (regcache, regnum, pc); |
1055 else | 1317 else |
1056 regcache_cooked_write_unsigned (regcache, regnum, pc); | 1318 regcache_cooked_write_unsigned (regcache, regnum, make_compact_addr (pc)); |
1057 } | 1319 } |
1058 | 1320 |
1059 /* Fetch and return instruction from the specified location. If the PC | 1321 /* Fetch and return instruction from the specified location. Handle |
1060 is odd, assume it's a MIPS16 instruction; otherwise MIPS32. */ | 1322 MIPS16/microMIPS as appropriate. */ |
1061 | 1323 |
1062 static ULONGEST | 1324 static ULONGEST |
1063 mips_fetch_instruction (struct gdbarch *gdbarch, CORE_ADDR addr) | 1325 mips_fetch_instruction (struct gdbarch *gdbarch, |
| 1326 » » » enum mips_isa isa, CORE_ADDR addr, int *statusp) |
1064 { | 1327 { |
1065 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | 1328 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
1066 gdb_byte buf[MIPS_INSN32_SIZE]; | 1329 gdb_byte buf[MIPS_INSN32_SIZE]; |
1067 int instlen; | 1330 int instlen; |
1068 int status; | 1331 int status; |
1069 | 1332 |
1070 if (mips_pc_is_mips16 (addr)) | 1333 switch (isa) |
1071 { | 1334 { |
| 1335 case ISA_MICROMIPS: |
| 1336 case ISA_MIPS16: |
1072 instlen = MIPS_INSN16_SIZE; | 1337 instlen = MIPS_INSN16_SIZE; |
1073 addr = unmake_mips16_addr (addr); | 1338 addr = unmake_compact_addr (addr); |
| 1339 break; |
| 1340 case ISA_MIPS: |
| 1341 instlen = MIPS_INSN32_SIZE; |
| 1342 break; |
| 1343 default: |
| 1344 internal_error (__FILE__, __LINE__, _("invalid ISA")); |
| 1345 break; |
1074 } | 1346 } |
1075 else | |
1076 instlen = MIPS_INSN32_SIZE; | |
1077 status = target_read_memory (addr, buf, instlen); | 1347 status = target_read_memory (addr, buf, instlen); |
| 1348 if (statusp != NULL) |
| 1349 *statusp = status; |
1078 if (status) | 1350 if (status) |
1079 memory_error (status, addr); | 1351 { |
| 1352 if (statusp == NULL) |
| 1353 » memory_error (status, addr); |
| 1354 return 0; |
| 1355 } |
1080 return extract_unsigned_integer (buf, instlen, byte_order); | 1356 return extract_unsigned_integer (buf, instlen, byte_order); |
1081 } | 1357 } |
1082 | 1358 |
1083 /* These are the fields of 32 bit mips instructions. */ | 1359 /* These are the fields of 32 bit mips instructions. */ |
1084 #define mips32_op(x) (x >> 26) | 1360 #define mips32_op(x) (x >> 26) |
1085 #define itype_op(x) (x >> 26) | 1361 #define itype_op(x) (x >> 26) |
1086 #define itype_rs(x) ((x >> 21) & 0x1f) | 1362 #define itype_rs(x) ((x >> 21) & 0x1f) |
1087 #define itype_rt(x) ((x >> 16) & 0x1f) | 1363 #define itype_rt(x) ((x >> 16) & 0x1f) |
1088 #define itype_immediate(x) (x & 0xffff) | 1364 #define itype_immediate(x) (x & 0xffff) |
1089 | 1365 |
1090 #define jtype_op(x) (x >> 26) | 1366 #define jtype_op(x) (x >> 26) |
1091 #define jtype_target(x) (x & 0x03ffffff) | 1367 #define jtype_target(x) (x & 0x03ffffff) |
1092 | 1368 |
1093 #define rtype_op(x) (x >> 26) | 1369 #define rtype_op(x) (x >> 26) |
1094 #define rtype_rs(x) ((x >> 21) & 0x1f) | 1370 #define rtype_rs(x) ((x >> 21) & 0x1f) |
1095 #define rtype_rt(x) ((x >> 16) & 0x1f) | 1371 #define rtype_rt(x) ((x >> 16) & 0x1f) |
1096 #define rtype_rd(x) ((x >> 11) & 0x1f) | 1372 #define rtype_rd(x) ((x >> 11) & 0x1f) |
1097 #define rtype_shamt(x) ((x >> 6) & 0x1f) | 1373 #define rtype_shamt(x) ((x >> 6) & 0x1f) |
1098 #define rtype_funct(x) (x & 0x3f) | 1374 #define rtype_funct(x) (x & 0x3f) |
1099 | 1375 |
| 1376 /* MicroMIPS instruction fields. */ |
| 1377 #define micromips_op(x) ((x) >> 10) |
| 1378 |
| 1379 /* 16-bit/32-bit-high-part instruction formats, B and S refer to the lowest |
| 1380 bit and the size respectively of the field extracted. */ |
| 1381 #define b0s4_imm(x) ((x) & 0xf) |
| 1382 #define b0s5_imm(x) ((x) & 0x1f) |
| 1383 #define b0s5_reg(x) ((x) & 0x1f) |
| 1384 #define b0s7_imm(x) ((x) & 0x7f) |
| 1385 #define b0s10_imm(x) ((x) & 0x3ff) |
| 1386 #define b1s4_imm(x) (((x) >> 1) & 0xf) |
| 1387 #define b1s9_imm(x) (((x) >> 1) & 0x1ff) |
| 1388 #define b2s3_cc(x) (((x) >> 2) & 0x7) |
| 1389 #define b4s2_regl(x) (((x) >> 4) & 0x3) |
| 1390 #define b5s5_op(x) (((x) >> 5) & 0x1f) |
| 1391 #define b5s5_reg(x) (((x) >> 5) & 0x1f) |
| 1392 #define b6s4_op(x) (((x) >> 6) & 0xf) |
| 1393 #define b7s3_reg(x) (((x) >> 7) & 0x7) |
| 1394 |
| 1395 /* 32-bit instruction formats, B and S refer to the lowest bit and the size |
| 1396 respectively of the field extracted. */ |
| 1397 #define b0s6_op(x) ((x) & 0x3f) |
| 1398 #define b0s11_op(x) ((x) & 0x7ff) |
| 1399 #define b0s12_imm(x) ((x) & 0xfff) |
| 1400 #define b0s16_imm(x) ((x) & 0xffff) |
| 1401 #define b0s26_imm(x) ((x) & 0x3ffffff) |
| 1402 #define b6s10_ext(x) (((x) >> 6) & 0x3ff) |
| 1403 #define b11s5_reg(x) (((x) >> 11) & 0x1f) |
| 1404 #define b12s4_op(x) (((x) >> 12) & 0xf) |
| 1405 |
| 1406 /* Return the size in bytes of the instruction INSN encoded in the ISA |
| 1407 instruction set. */ |
| 1408 |
| 1409 static int |
| 1410 mips_insn_size (enum mips_isa isa, ULONGEST insn) |
| 1411 { |
| 1412 switch (isa) |
| 1413 { |
| 1414 case ISA_MICROMIPS: |
| 1415 if (micromips_op (insn) == 0x1f) |
| 1416 return 3 * MIPS_INSN16_SIZE; |
| 1417 else if (((micromips_op (insn) & 0x4) == 0x4) |
| 1418 || ((micromips_op (insn) & 0x7) == 0x0)) |
| 1419 return 2 * MIPS_INSN16_SIZE; |
| 1420 else |
| 1421 return MIPS_INSN16_SIZE; |
| 1422 case ISA_MIPS16: |
| 1423 if ((insn & 0xf800) == 0xf000) |
| 1424 return 2 * MIPS_INSN16_SIZE; |
| 1425 else |
| 1426 return MIPS_INSN16_SIZE; |
| 1427 case ISA_MIPS: |
| 1428 return MIPS_INSN32_SIZE; |
| 1429 } |
| 1430 internal_error (__FILE__, __LINE__, _("invalid ISA")); |
| 1431 } |
| 1432 |
1100 static LONGEST | 1433 static LONGEST |
1101 mips32_relative_offset (ULONGEST inst) | 1434 mips32_relative_offset (ULONGEST inst) |
1102 { | 1435 { |
1103 return ((itype_immediate (inst) ^ 0x8000) - 0x8000) << 2; | 1436 return ((itype_immediate (inst) ^ 0x8000) - 0x8000) << 2; |
1104 } | 1437 } |
1105 | 1438 |
| 1439 /* Determine the address of the next instruction executed after the INST |
| 1440 floating condition branch instruction at PC. COUNT specifies the |
| 1441 number of the floating condition bits tested by the branch. */ |
| 1442 |
| 1443 static CORE_ADDR |
| 1444 mips32_bc1_pc (struct gdbarch *gdbarch, struct frame_info *frame, |
| 1445 ULONGEST inst, CORE_ADDR pc, int count) |
| 1446 { |
| 1447 int fcsr = mips_regnum (gdbarch)->fp_control_status; |
| 1448 int cnum = (itype_rt (inst) >> 2) & (count - 1); |
| 1449 int tf = itype_rt (inst) & 1; |
| 1450 int mask = (1 << count) - 1; |
| 1451 ULONGEST fcs; |
| 1452 int cond; |
| 1453 |
| 1454 if (fcsr == -1) |
| 1455 /* No way to handle; it'll most likely trap anyway. */ |
| 1456 return pc; |
| 1457 |
| 1458 fcs = get_frame_register_unsigned (frame, fcsr); |
| 1459 cond = ((fcs >> 24) & 0xfe) | ((fcs >> 23) & 0x01); |
| 1460 |
| 1461 if (((cond >> cnum) & mask) != mask * !tf) |
| 1462 pc += mips32_relative_offset (inst); |
| 1463 else |
| 1464 pc += 4; |
| 1465 |
| 1466 return pc; |
| 1467 } |
| 1468 |
1106 /* Determine where to set a single step breakpoint while considering | 1469 /* Determine where to set a single step breakpoint while considering |
1107 branch prediction. */ | 1470 branch prediction. */ |
1108 static CORE_ADDR | 1471 static CORE_ADDR |
1109 mips32_next_pc (struct frame_info *frame, CORE_ADDR pc) | 1472 mips32_next_pc (struct frame_info *frame, CORE_ADDR pc) |
1110 { | 1473 { |
1111 struct gdbarch *gdbarch = get_frame_arch (frame); | 1474 struct gdbarch *gdbarch = get_frame_arch (frame); |
1112 unsigned long inst; | 1475 unsigned long inst; |
1113 int op; | 1476 int op; |
1114 inst = mips_fetch_instruction (gdbarch, pc); | 1477 inst = mips_fetch_instruction (gdbarch, ISA_MIPS, pc, NULL); |
1115 if ((inst & 0xe0000000) != 0) /* Not a special, jump or branch | 1478 if ((inst & 0xe0000000) != 0) /* Not a special, jump or branch |
1116 instruction. */ | 1479 instruction. */ |
1117 { | 1480 { |
1118 if (itype_op (inst) >> 2 == 5) | 1481 if (itype_op (inst) >> 2 == 5) |
1119 /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */ | 1482 /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */ |
1120 { | 1483 { |
1121 op = (itype_op (inst) & 0x03); | 1484 op = (itype_op (inst) & 0x03); |
1122 switch (op) | 1485 switch (op) |
1123 { | 1486 { |
1124 case 0: /* BEQL */ | 1487 case 0: /* BEQL */ |
1125 goto equal_branch; | 1488 goto equal_branch; |
1126 case 1: /* BNEL */ | 1489 case 1: /* BNEL */ |
1127 goto neq_branch; | 1490 goto neq_branch; |
1128 case 2: /* BLEZL */ | 1491 case 2: /* BLEZL */ |
1129 goto less_branch; | 1492 goto less_branch; |
1130 case 3: /* BGTZL */ | 1493 case 3: /* BGTZL */ |
1131 goto greater_branch; | 1494 goto greater_branch; |
1132 default: | 1495 default: |
1133 pc += 4; | 1496 pc += 4; |
1134 } | 1497 } |
1135 } | 1498 } |
1136 else if (itype_op (inst) == 17 && itype_rs (inst) == 8) | 1499 else if (itype_op (inst) == 17 && itype_rs (inst) == 8) |
1137 /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */ | 1500 /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */ |
| 1501 pc = mips32_bc1_pc (gdbarch, frame, inst, pc + 4, 1); |
| 1502 else if (itype_op (inst) == 17 && itype_rs (inst) == 9 |
| 1503 && (itype_rt (inst) & 2) == 0) |
| 1504 /* BC1ANY2F, BC1ANY2T: 010001 01001 xxx0x */ |
| 1505 pc = mips32_bc1_pc (gdbarch, frame, inst, pc + 4, 2); |
| 1506 else if (itype_op (inst) == 17 && itype_rs (inst) == 10 |
| 1507 && (itype_rt (inst) & 2) == 0) |
| 1508 /* BC1ANY4F, BC1ANY4T: 010001 01010 xxx0x */ |
| 1509 pc = mips32_bc1_pc (gdbarch, frame, inst, pc + 4, 4); |
| 1510 else if (itype_op (inst) == 29) |
| 1511 /* JALX: 011101 */ |
| 1512 /* The new PC will be alternate mode. */ |
1138 { | 1513 { |
1139 » int tf = itype_rt (inst) & 0x01; | 1514 » unsigned long reg; |
1140 » int cnum = itype_rt (inst) >> 2; | |
1141 » int fcrcs = | |
1142 » get_frame_register_signed (frame, | |
1143 » » » » mips_regnum (get_frame_arch (frame))-> | |
1144 » » » » » » fp_control_status); | |
1145 » int cond = ((fcrcs >> 24) & 0xfe) | ((fcrcs >> 23) & 0x01); | |
1146 | 1515 |
1147 » if (((cond >> cnum) & 0x01) == tf) | 1516 » reg = jtype_target (inst) << 2; |
1148 » pc += mips32_relative_offset (inst) + 4; | 1517 » /* Add 1 to indicate 16-bit mode -- invert ISA mode. */ |
1149 » else | 1518 » pc = ((pc + 4) & ~(CORE_ADDR) 0x0fffffff) + reg + 1; |
1150 » pc += 8; | |
1151 } | 1519 } |
1152 else | 1520 else |
1153 pc += 4; /* Not a branch, next instruction is easy. */ | 1521 pc += 4; /* Not a branch, next instruction is easy. */ |
1154 } | 1522 } |
1155 else | 1523 else |
1156 { /* This gets way messy. */ | 1524 { /* This gets way messy. */ |
1157 | 1525 |
1158 /* Further subdivide into SPECIAL, REGIMM and other. */ | 1526 /* Further subdivide into SPECIAL, REGIMM and other. */ |
1159 switch (op = itype_op (inst) & 0x07) /* Extract bits 28,27,26. */ | 1527 switch (op = itype_op (inst) & 0x07) /* Extract bits 28,27,26. */ |
1160 { | 1528 { |
(...skipping 39 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... |
1200 break; | 1568 break; |
1201 case 1: /* BGEZ */ | 1569 case 1: /* BGEZ */ |
1202 case 3: /* BGEZL */ | 1570 case 3: /* BGEZL */ |
1203 case 17: /* BGEZAL */ | 1571 case 17: /* BGEZAL */ |
1204 case 19: /* BGEZALL */ | 1572 case 19: /* BGEZALL */ |
1205 if (get_frame_register_signed (frame, itype_rs (inst)) >= 0) | 1573 if (get_frame_register_signed (frame, itype_rs (inst)) >= 0) |
1206 pc += mips32_relative_offset (inst) + 4; | 1574 pc += mips32_relative_offset (inst) + 4; |
1207 else | 1575 else |
1208 pc += 8; /* after the delay slot */ | 1576 pc += 8; /* after the delay slot */ |
1209 break; | 1577 break; |
| 1578 case 0x1c: /* BPOSGE32 */ |
| 1579 case 0x1e: /* BPOSGE64 */ |
| 1580 pc += 4; |
| 1581 if (itype_rs (inst) == 0) |
| 1582 { |
| 1583 unsigned int pos = (op & 2) ? 64 : 32; |
| 1584 int dspctl = mips_regnum (gdbarch)->dspctl; |
| 1585 |
| 1586 if (dspctl == -1) |
| 1587 /* No way to handle; it'll most likely trap anyway. */ |
| 1588 break; |
| 1589 |
| 1590 if ((get_frame_register_unsigned (frame, |
| 1591 dspctl) & 0x7f) >= pos) |
| 1592 pc += mips32_relative_offset (inst); |
| 1593 else |
| 1594 pc += 4; |
| 1595 } |
| 1596 break; |
1210 /* All of the other instructions in the REGIMM category */ | 1597 /* All of the other instructions in the REGIMM category */ |
1211 default: | 1598 default: |
1212 pc += 4; | 1599 pc += 4; |
1213 } | 1600 } |
1214 } | 1601 } |
1215 break; /* end REGIMM */ | 1602 break; /* end REGIMM */ |
1216 case 2: /* J */ | 1603 case 2: /* J */ |
1217 case 3: /* JAL */ | 1604 case 3: /* JAL */ |
1218 { | 1605 { |
1219 unsigned long reg; | 1606 unsigned long reg; |
1220 reg = jtype_target (inst) << 2; | 1607 reg = jtype_target (inst) << 2; |
1221 /* Upper four bits get never changed... */ | 1608 /* Upper four bits get never changed... */ |
1222 pc = reg + ((pc + 4) & ~(CORE_ADDR) 0x0fffffff); | 1609 pc = reg + ((pc + 4) & ~(CORE_ADDR) 0x0fffffff); |
1223 } | 1610 } |
1224 break; | 1611 break; |
1225 /* FIXME case JALX : */ | |
1226 { | |
1227 unsigned long reg; | |
1228 reg = jtype_target (inst) << 2; | |
1229 pc = reg + ((pc + 4) & ~(CORE_ADDR) 0x0fffffff) + 1; /* yes, +1 */ | |
1230 /* Add 1 to indicate 16 bit mode - Invert ISA mode */ | |
1231 } | |
1232 break; /* The new PC will be alternate mode */ | |
1233 case 4: /* BEQ, BEQL */ | 1612 case 4: /* BEQ, BEQL */ |
1234 equal_branch: | 1613 equal_branch: |
1235 if (get_frame_register_signed (frame, itype_rs (inst)) == | 1614 if (get_frame_register_signed (frame, itype_rs (inst)) == |
1236 get_frame_register_signed (frame, itype_rt (inst))) | 1615 get_frame_register_signed (frame, itype_rt (inst))) |
1237 pc += mips32_relative_offset (inst) + 4; | 1616 pc += mips32_relative_offset (inst) + 4; |
1238 else | 1617 else |
1239 pc += 8; | 1618 pc += 8; |
1240 break; | 1619 break; |
1241 case 5: /* BNE, BNEL */ | 1620 case 5: /* BNE, BNEL */ |
1242 neq_branch: | 1621 neq_branch: |
(...skipping 15 matching lines...) Expand all Loading... |
1258 if (get_frame_register_signed (frame, itype_rs (inst)) > 0) | 1637 if (get_frame_register_signed (frame, itype_rs (inst)) > 0) |
1259 pc += mips32_relative_offset (inst) + 4; | 1638 pc += mips32_relative_offset (inst) + 4; |
1260 else | 1639 else |
1261 pc += 8; | 1640 pc += 8; |
1262 break; | 1641 break; |
1263 } /* switch */ | 1642 } /* switch */ |
1264 } /* else */ | 1643 } /* else */ |
1265 return pc; | 1644 return pc; |
1266 } /* mips32_next_pc */ | 1645 } /* mips32_next_pc */ |
1267 | 1646 |
| 1647 /* Extract the 7-bit signed immediate offset from the microMIPS instruction |
| 1648 INSN. */ |
| 1649 |
| 1650 static LONGEST |
| 1651 micromips_relative_offset7 (ULONGEST insn) |
| 1652 { |
| 1653 return ((b0s7_imm (insn) ^ 0x40) - 0x40) << 1; |
| 1654 } |
| 1655 |
| 1656 /* Extract the 10-bit signed immediate offset from the microMIPS instruction |
| 1657 INSN. */ |
| 1658 |
| 1659 static LONGEST |
| 1660 micromips_relative_offset10 (ULONGEST insn) |
| 1661 { |
| 1662 return ((b0s10_imm (insn) ^ 0x200) - 0x200) << 1; |
| 1663 } |
| 1664 |
| 1665 /* Extract the 16-bit signed immediate offset from the microMIPS instruction |
| 1666 INSN. */ |
| 1667 |
| 1668 static LONGEST |
| 1669 micromips_relative_offset16 (ULONGEST insn) |
| 1670 { |
| 1671 return ((b0s16_imm (insn) ^ 0x8000) - 0x8000) << 1; |
| 1672 } |
| 1673 |
| 1674 /* Return the size in bytes of the microMIPS instruction at the address PC. */ |
| 1675 |
| 1676 static int |
| 1677 micromips_pc_insn_size (struct gdbarch *gdbarch, CORE_ADDR pc) |
| 1678 { |
| 1679 ULONGEST insn; |
| 1680 |
| 1681 insn = mips_fetch_instruction (gdbarch, ISA_MICROMIPS, pc, NULL); |
| 1682 return mips_insn_size (ISA_MICROMIPS, insn); |
| 1683 } |
| 1684 |
| 1685 /* Calculate the address of the next microMIPS instruction to execute |
| 1686 after the INSN coprocessor 1 conditional branch instruction at the |
| 1687 address PC. COUNT denotes the number of coprocessor condition bits |
| 1688 examined by the branch. */ |
| 1689 |
| 1690 static CORE_ADDR |
| 1691 micromips_bc1_pc (struct gdbarch *gdbarch, struct frame_info *frame, |
| 1692 ULONGEST insn, CORE_ADDR pc, int count) |
| 1693 { |
| 1694 int fcsr = mips_regnum (gdbarch)->fp_control_status; |
| 1695 int cnum = b2s3_cc (insn >> 16) & (count - 1); |
| 1696 int tf = b5s5_op (insn >> 16) & 1; |
| 1697 int mask = (1 << count) - 1; |
| 1698 ULONGEST fcs; |
| 1699 int cond; |
| 1700 |
| 1701 if (fcsr == -1) |
| 1702 /* No way to handle; it'll most likely trap anyway. */ |
| 1703 return pc; |
| 1704 |
| 1705 fcs = get_frame_register_unsigned (frame, fcsr); |
| 1706 cond = ((fcs >> 24) & 0xfe) | ((fcs >> 23) & 0x01); |
| 1707 |
| 1708 if (((cond >> cnum) & mask) != mask * !tf) |
| 1709 pc += micromips_relative_offset16 (insn); |
| 1710 else |
| 1711 pc += micromips_pc_insn_size (gdbarch, pc); |
| 1712 |
| 1713 return pc; |
| 1714 } |
| 1715 |
| 1716 /* Calculate the address of the next microMIPS instruction to execute |
| 1717 after the instruction at the address PC. */ |
| 1718 |
| 1719 static CORE_ADDR |
| 1720 micromips_next_pc (struct frame_info *frame, CORE_ADDR pc) |
| 1721 { |
| 1722 struct gdbarch *gdbarch = get_frame_arch (frame); |
| 1723 ULONGEST insn; |
| 1724 |
| 1725 insn = mips_fetch_instruction (gdbarch, ISA_MICROMIPS, pc, NULL); |
| 1726 pc += MIPS_INSN16_SIZE; |
| 1727 switch (mips_insn_size (ISA_MICROMIPS, insn)) |
| 1728 { |
| 1729 /* 48-bit instructions. */ |
| 1730 case 3 * MIPS_INSN16_SIZE: /* POOL48A: bits 011111 */ |
| 1731 /* No branch or jump instructions in this category. */ |
| 1732 pc += 2 * MIPS_INSN16_SIZE; |
| 1733 break; |
| 1734 |
| 1735 /* 32-bit instructions. */ |
| 1736 case 2 * MIPS_INSN16_SIZE: |
| 1737 insn <<= 16; |
| 1738 insn |= mips_fetch_instruction (gdbarch, ISA_MICROMIPS, pc, NULL); |
| 1739 pc += MIPS_INSN16_SIZE; |
| 1740 switch (micromips_op (insn >> 16)) |
| 1741 { |
| 1742 case 0x00: /* POOL32A: bits 000000 */ |
| 1743 if (b0s6_op (insn) == 0x3c |
| 1744 /* POOL32Axf: bits 000000 ... 111100 */ |
| 1745 && (b6s10_ext (insn) & 0x2bf) == 0x3c) |
| 1746 /* JALR, JALR.HB: 000000 000x111100 111100 */ |
| 1747 /* JALRS, JALRS.HB: 000000 010x111100 111100 */ |
| 1748 pc = get_frame_register_signed (frame, b0s5_reg (insn >> 16)); |
| 1749 break; |
| 1750 |
| 1751 case 0x10: /* POOL32I: bits 010000 */ |
| 1752 switch (b5s5_op (insn >> 16)) |
| 1753 { |
| 1754 case 0x00: /* BLTZ: bits 010000 00000 */ |
| 1755 case 0x01: /* BLTZAL: bits 010000 00001 */ |
| 1756 case 0x11: /* BLTZALS: bits 010000 10001 */ |
| 1757 if (get_frame_register_signed (frame, |
| 1758 b0s5_reg (insn >> 16)) < 0) |
| 1759 pc += micromips_relative_offset16 (insn); |
| 1760 else |
| 1761 pc += micromips_pc_insn_size (gdbarch, pc); |
| 1762 break; |
| 1763 |
| 1764 case 0x02: /* BGEZ: bits 010000 00010 */ |
| 1765 case 0x03: /* BGEZAL: bits 010000 00011 */ |
| 1766 case 0x13: /* BGEZALS: bits 010000 10011 */ |
| 1767 if (get_frame_register_signed (frame, |
| 1768 b0s5_reg (insn >> 16)) >= 0) |
| 1769 pc += micromips_relative_offset16 (insn); |
| 1770 else |
| 1771 pc += micromips_pc_insn_size (gdbarch, pc); |
| 1772 break; |
| 1773 |
| 1774 case 0x04: /* BLEZ: bits 010000 00100 */ |
| 1775 if (get_frame_register_signed (frame, |
| 1776 b0s5_reg (insn >> 16)) <= 0) |
| 1777 pc += micromips_relative_offset16 (insn); |
| 1778 else |
| 1779 pc += micromips_pc_insn_size (gdbarch, pc); |
| 1780 break; |
| 1781 |
| 1782 case 0x05: /* BNEZC: bits 010000 00101 */ |
| 1783 if (get_frame_register_signed (frame, |
| 1784 b0s5_reg (insn >> 16)) != 0) |
| 1785 pc += micromips_relative_offset16 (insn); |
| 1786 break; |
| 1787 |
| 1788 case 0x06: /* BGTZ: bits 010000 00110 */ |
| 1789 if (get_frame_register_signed (frame, |
| 1790 b0s5_reg (insn >> 16)) > 0) |
| 1791 pc += micromips_relative_offset16 (insn); |
| 1792 else |
| 1793 pc += micromips_pc_insn_size (gdbarch, pc); |
| 1794 break; |
| 1795 |
| 1796 case 0x07: /* BEQZC: bits 010000 00111 */ |
| 1797 if (get_frame_register_signed (frame, |
| 1798 b0s5_reg (insn >> 16)) == 0) |
| 1799 pc += micromips_relative_offset16 (insn); |
| 1800 break; |
| 1801 |
| 1802 case 0x14: /* BC2F: bits 010000 10100 xxx00 */ |
| 1803 case 0x15: /* BC2T: bits 010000 10101 xxx00 */ |
| 1804 if (((insn >> 16) & 0x3) == 0x0) |
| 1805 /* BC2F, BC2T: don't know how to handle these. */ |
| 1806 break; |
| 1807 break; |
| 1808 |
| 1809 case 0x1a: /* BPOSGE64: bits 010000 11010 */ |
| 1810 case 0x1b: /* BPOSGE32: bits 010000 11011 */ |
| 1811 { |
| 1812 unsigned int pos = (b5s5_op (insn >> 16) & 1) ? 32 : 64; |
| 1813 int dspctl = mips_regnum (gdbarch)->dspctl; |
| 1814 |
| 1815 if (dspctl == -1) |
| 1816 /* No way to handle; it'll most likely trap anyway. */ |
| 1817 break; |
| 1818 |
| 1819 if ((get_frame_register_unsigned (frame, |
| 1820 dspctl) & 0x7f) >= pos) |
| 1821 pc += micromips_relative_offset16 (insn); |
| 1822 else |
| 1823 pc += micromips_pc_insn_size (gdbarch, pc); |
| 1824 } |
| 1825 break; |
| 1826 |
| 1827 case 0x1c: /* BC1F: bits 010000 11100 xxx00 */ |
| 1828 /* BC1ANY2F: bits 010000 11100 xxx01 */ |
| 1829 case 0x1d: /* BC1T: bits 010000 11101 xxx00 */ |
| 1830 /* BC1ANY2T: bits 010000 11101 xxx01 */ |
| 1831 if (((insn >> 16) & 0x2) == 0x0) |
| 1832 pc = micromips_bc1_pc (gdbarch, frame, insn, pc, |
| 1833 ((insn >> 16) & 0x1) + 1); |
| 1834 break; |
| 1835 |
| 1836 case 0x1e: /* BC1ANY4F: bits 010000 11110 xxx01 */ |
| 1837 case 0x1f: /* BC1ANY4T: bits 010000 11111 xxx01 */ |
| 1838 if (((insn >> 16) & 0x3) == 0x1) |
| 1839 pc = micromips_bc1_pc (gdbarch, frame, insn, pc, 4); |
| 1840 break; |
| 1841 } |
| 1842 break; |
| 1843 |
| 1844 case 0x1d: /* JALS: bits 011101 */ |
| 1845 case 0x35: /* J: bits 110101 */ |
| 1846 case 0x3d: /* JAL: bits 111101 */ |
| 1847 pc = ((pc | 0x7fffffe) ^ 0x7fffffe) | (b0s26_imm (insn) << 1); |
| 1848 break; |
| 1849 |
| 1850 case 0x25: /* BEQ: bits 100101 */ |
| 1851 if (get_frame_register_signed (frame, b0s5_reg (insn >> 16)) |
| 1852 == get_frame_register_signed (frame, b5s5_reg (insn >> 16))) |
| 1853 pc += micromips_relative_offset16 (insn); |
| 1854 else |
| 1855 pc += micromips_pc_insn_size (gdbarch, pc); |
| 1856 break; |
| 1857 |
| 1858 case 0x2d: /* BNE: bits 101101 */ |
| 1859 if (get_frame_register_signed (frame, b0s5_reg (insn >> 16)) |
| 1860 != get_frame_register_signed (frame, b5s5_reg (insn >> 16))) |
| 1861 pc += micromips_relative_offset16 (insn); |
| 1862 else |
| 1863 pc += micromips_pc_insn_size (gdbarch, pc); |
| 1864 break; |
| 1865 |
| 1866 case 0x3c: /* JALX: bits 111100 */ |
| 1867 pc = ((pc | 0xfffffff) ^ 0xfffffff) | (b0s26_imm (insn) << 2); |
| 1868 break; |
| 1869 } |
| 1870 break; |
| 1871 |
| 1872 /* 16-bit instructions. */ |
| 1873 case MIPS_INSN16_SIZE: |
| 1874 switch (micromips_op (insn)) |
| 1875 { |
| 1876 case 0x11: /* POOL16C: bits 010001 */ |
| 1877 if ((b5s5_op (insn) & 0x1c) == 0xc) |
| 1878 /* JR16, JRC, JALR16, JALRS16: 010001 011xx */ |
| 1879 pc = get_frame_register_signed (frame, b0s5_reg (insn)); |
| 1880 else if (b5s5_op (insn) == 0x18) |
| 1881 /* JRADDIUSP: bits 010001 11000 */ |
| 1882 pc = get_frame_register_signed (frame, MIPS_RA_REGNUM); |
| 1883 break; |
| 1884 |
| 1885 case 0x23: /* BEQZ16: bits 100011 */ |
| 1886 { |
| 1887 int rs = mips_reg3_to_reg[b7s3_reg (insn)]; |
| 1888 |
| 1889 if (get_frame_register_signed (frame, rs) == 0) |
| 1890 pc += micromips_relative_offset7 (insn); |
| 1891 else |
| 1892 pc += micromips_pc_insn_size (gdbarch, pc); |
| 1893 } |
| 1894 break; |
| 1895 |
| 1896 case 0x2b: /* BNEZ16: bits 101011 */ |
| 1897 { |
| 1898 int rs = mips_reg3_to_reg[b7s3_reg (insn)]; |
| 1899 |
| 1900 if (get_frame_register_signed (frame, rs) != 0) |
| 1901 pc += micromips_relative_offset7 (insn); |
| 1902 else |
| 1903 pc += micromips_pc_insn_size (gdbarch, pc); |
| 1904 } |
| 1905 break; |
| 1906 |
| 1907 case 0x33: /* B16: bits 110011 */ |
| 1908 pc += micromips_relative_offset10 (insn); |
| 1909 break; |
| 1910 } |
| 1911 break; |
| 1912 } |
| 1913 |
| 1914 return pc; |
| 1915 } |
| 1916 |
1268 /* Decoding the next place to set a breakpoint is irregular for the | 1917 /* Decoding the next place to set a breakpoint is irregular for the |
1269 mips 16 variant, but fortunately, there fewer instructions. We have | 1918 mips 16 variant, but fortunately, there fewer instructions. We have |
1270 to cope ith extensions for 16 bit instructions and a pair of actual | 1919 to cope ith extensions for 16 bit instructions and a pair of actual |
1271 32 bit instructions. We dont want to set a single step instruction | 1920 32 bit instructions. We dont want to set a single step instruction |
1272 on the extend instruction either. */ | 1921 on the extend instruction either. */ |
1273 | 1922 |
1274 /* Lots of mips16 instruction formats */ | 1923 /* Lots of mips16 instruction formats */ |
1275 /* Predicting jumps requires itype,ritype,i8type | 1924 /* Predicting jumps requires itype,ritype,i8type |
1276 and their extensions extItype,extritype,extI8type. */ | 1925 and their extensions extItype,extritype,extI8type. */ |
1277 enum mips16_inst_fmts | 1926 enum mips16_inst_fmts |
(...skipping 114 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... |
1392 regx = (inst >> 8) & 0x07; /* i8 funct */ | 2041 regx = (inst >> 8) & 0x07; /* i8 funct */ |
1393 regy = -1; | 2042 regy = -1; |
1394 break; | 2043 break; |
1395 } | 2044 } |
1396 case jalxtype: | 2045 case jalxtype: |
1397 { | 2046 { |
1398 unsigned long value; | 2047 unsigned long value; |
1399 unsigned int nexthalf; | 2048 unsigned int nexthalf; |
1400 value = ((inst & 0x1f) << 5) | ((inst >> 5) & 0x1f); | 2049 value = ((inst & 0x1f) << 5) | ((inst >> 5) & 0x1f); |
1401 value = value << 16; | 2050 value = value << 16; |
1402 » nexthalf = mips_fetch_instruction (gdbarch, pc + 2); /* low bit | 2051 » nexthalf = mips_fetch_instruction (gdbarch, ISA_MIPS16, pc + 2, NULL); |
1403 » » » » » » » » still set. */ | 2052 » » » » » » /* Low bit still set. */ |
1404 value |= nexthalf; | 2053 value |= nexthalf; |
1405 offset = value; | 2054 offset = value; |
1406 regx = -1; | 2055 regx = -1; |
1407 regy = -1; | 2056 regy = -1; |
1408 break; | 2057 break; |
1409 } | 2058 } |
1410 default: | 2059 default: |
1411 internal_error (__FILE__, __LINE__, _("bad switch")); | 2060 internal_error (__FILE__, __LINE__, _("bad switch")); |
1412 } | 2061 } |
1413 upk->offset = offset; | 2062 upk->offset = offset; |
(...skipping 11 matching lines...) Expand all Loading... |
1425 static CORE_ADDR | 2074 static CORE_ADDR |
1426 extended_mips16_next_pc (struct frame_info *frame, CORE_ADDR pc, | 2075 extended_mips16_next_pc (struct frame_info *frame, CORE_ADDR pc, |
1427 unsigned int extension, unsigned int insn) | 2076 unsigned int extension, unsigned int insn) |
1428 { | 2077 { |
1429 struct gdbarch *gdbarch = get_frame_arch (frame); | 2078 struct gdbarch *gdbarch = get_frame_arch (frame); |
1430 int op = (insn >> 11); | 2079 int op = (insn >> 11); |
1431 switch (op) | 2080 switch (op) |
1432 { | 2081 { |
1433 case 2: /* Branch */ | 2082 case 2: /* Branch */ |
1434 { | 2083 { |
1435 CORE_ADDR offset; | |
1436 struct upk_mips16 upk; | 2084 struct upk_mips16 upk; |
1437 unpack_mips16 (gdbarch, pc, extension, insn, itype, &upk); | 2085 unpack_mips16 (gdbarch, pc, extension, insn, itype, &upk); |
1438 pc += (upk.offset << 1) + 2; | 2086 pc += (upk.offset << 1) + 2; |
1439 break; | 2087 break; |
1440 } | 2088 } |
1441 case 3: /* JAL , JALX - Watch out, these are 32 bit | 2089 case 3: /* JAL , JALX - Watch out, these are 32 bit |
1442 instructions. */ | 2090 instructions. */ |
1443 { | 2091 { |
1444 struct upk_mips16 upk; | 2092 struct upk_mips16 upk; |
1445 unpack_mips16 (gdbarch, pc, extension, insn, jalxtype, &upk); | 2093 unpack_mips16 (gdbarch, pc, extension, insn, jalxtype, &upk); |
1446 pc = add_offset_16 (pc, upk.offset); | 2094 pc = add_offset_16 (pc, upk.offset); |
1447 if ((insn >> 10) & 0x01) /* Exchange mode */ | 2095 if ((insn >> 10) & 0x01) /* Exchange mode */ |
1448 pc = pc & ~0x01; /* Clear low bit, indicate 32 bit mode. */ | 2096 pc = pc & ~0x01; /* Clear low bit, indicate 32 bit mode. */ |
1449 else | 2097 else |
1450 pc |= 0x01; | 2098 pc |= 0x01; |
1451 break; | 2099 break; |
1452 } | 2100 } |
1453 case 4: /* beqz */ | 2101 case 4: /* beqz */ |
1454 { | 2102 { |
1455 struct upk_mips16 upk; | 2103 struct upk_mips16 upk; |
1456 int reg; | 2104 int reg; |
1457 unpack_mips16 (gdbarch, pc, extension, insn, ritype, &upk); | 2105 unpack_mips16 (gdbarch, pc, extension, insn, ritype, &upk); |
1458 » reg = get_frame_register_signed (frame, mips16_to_32_reg[upk.regx]); | 2106 » reg = get_frame_register_signed (frame, mips_reg3_to_reg[upk.regx]); |
1459 if (reg == 0) | 2107 if (reg == 0) |
1460 pc += (upk.offset << 1) + 2; | 2108 pc += (upk.offset << 1) + 2; |
1461 else | 2109 else |
1462 pc += 2; | 2110 pc += 2; |
1463 break; | 2111 break; |
1464 } | 2112 } |
1465 case 5: /* bnez */ | 2113 case 5: /* bnez */ |
1466 { | 2114 { |
1467 struct upk_mips16 upk; | 2115 struct upk_mips16 upk; |
1468 int reg; | 2116 int reg; |
1469 unpack_mips16 (gdbarch, pc, extension, insn, ritype, &upk); | 2117 unpack_mips16 (gdbarch, pc, extension, insn, ritype, &upk); |
1470 » reg = get_frame_register_signed (frame, mips16_to_32_reg[upk.regx]); | 2118 » reg = get_frame_register_signed (frame, mips_reg3_to_reg[upk.regx]); |
1471 if (reg != 0) | 2119 if (reg != 0) |
1472 pc += (upk.offset << 1) + 2; | 2120 pc += (upk.offset << 1) + 2; |
1473 else | 2121 else |
1474 pc += 2; | 2122 pc += 2; |
1475 break; | 2123 break; |
1476 } | 2124 } |
1477 case 12: /* I8 Formats btez btnez */ | 2125 case 12: /* I8 Formats btez btnez */ |
1478 { | 2126 { |
1479 struct upk_mips16 upk; | 2127 struct upk_mips16 upk; |
1480 int reg; | 2128 int reg; |
(...skipping 12 matching lines...) Expand all Loading... |
1493 { | 2141 { |
1494 struct upk_mips16 upk; | 2142 struct upk_mips16 upk; |
1495 /* upk.fmt = rrtype; */ | 2143 /* upk.fmt = rrtype; */ |
1496 op = insn & 0x1f; | 2144 op = insn & 0x1f; |
1497 if (op == 0) | 2145 if (op == 0) |
1498 { | 2146 { |
1499 int reg; | 2147 int reg; |
1500 upk.regx = (insn >> 8) & 0x07; | 2148 upk.regx = (insn >> 8) & 0x07; |
1501 upk.regy = (insn >> 5) & 0x07; | 2149 upk.regy = (insn >> 5) & 0x07; |
1502 if ((upk.regy & 1) == 0) | 2150 if ((upk.regy & 1) == 0) |
1503 » reg = mips16_to_32_reg[upk.regx]; | 2151 » reg = mips_reg3_to_reg[upk.regx]; |
1504 else | 2152 else |
1505 reg = 31; /* Function return instruction. */ | 2153 reg = 31; /* Function return instruction. */ |
1506 pc = get_frame_register_signed (frame, reg); | 2154 pc = get_frame_register_signed (frame, reg); |
1507 } | 2155 } |
1508 else | 2156 else |
1509 pc += 2; | 2157 pc += 2; |
1510 break; | 2158 break; |
1511 } | 2159 } |
1512 case 30: | 2160 case 30: |
1513 /* This is an instruction extension. Fetch the real instruction | 2161 /* This is an instruction extension. Fetch the real instruction |
(...skipping 19 matching lines...) Expand all Loading... |
1533 { | 2181 { |
1534 struct gdbarch *gdbarch = get_frame_arch (frame); | 2182 struct gdbarch *gdbarch = get_frame_arch (frame); |
1535 unsigned int insn = fetch_mips_16 (gdbarch, pc); | 2183 unsigned int insn = fetch_mips_16 (gdbarch, pc); |
1536 return extended_mips16_next_pc (frame, pc, 0, insn); | 2184 return extended_mips16_next_pc (frame, pc, 0, insn); |
1537 } | 2185 } |
1538 | 2186 |
1539 /* The mips_next_pc function supports single_step when the remote | 2187 /* The mips_next_pc function supports single_step when the remote |
1540 target monitor or stub is not developed enough to do a single_step. | 2188 target monitor or stub is not developed enough to do a single_step. |
1541 It works by decoding the current instruction and predicting where a | 2189 It works by decoding the current instruction and predicting where a |
1542 branch will go. This isnt hard because all the data is available. | 2190 branch will go. This isnt hard because all the data is available. |
1543 The MIPS32 and MIPS16 variants are quite different. */ | 2191 The MIPS32, MIPS16 and microMIPS variants are quite different. */ |
1544 static CORE_ADDR | 2192 static CORE_ADDR |
1545 mips_next_pc (struct frame_info *frame, CORE_ADDR pc) | 2193 mips_next_pc (struct frame_info *frame, CORE_ADDR pc) |
1546 { | 2194 { |
1547 if (mips_pc_is_mips16 (pc)) | 2195 struct gdbarch *gdbarch = get_frame_arch (frame); |
| 2196 |
| 2197 if (mips_pc_is_mips16 (gdbarch, pc)) |
1548 return mips16_next_pc (frame, pc); | 2198 return mips16_next_pc (frame, pc); |
| 2199 else if (mips_pc_is_micromips (gdbarch, pc)) |
| 2200 return micromips_next_pc (frame, pc); |
1549 else | 2201 else |
1550 return mips32_next_pc (frame, pc); | 2202 return mips32_next_pc (frame, pc); |
1551 } | 2203 } |
1552 | 2204 |
1553 struct mips_frame_cache | 2205 struct mips_frame_cache |
1554 { | 2206 { |
1555 CORE_ADDR base; | 2207 CORE_ADDR base; |
1556 struct trad_frame_saved_reg *saved_regs; | 2208 struct trad_frame_saved_reg *saved_regs; |
1557 }; | 2209 }; |
1558 | 2210 |
(...skipping 96 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... |
1655 if (limit_pc > start_pc + 200) | 2307 if (limit_pc > start_pc + 200) |
1656 limit_pc = start_pc + 200; | 2308 limit_pc = start_pc + 200; |
1657 | 2309 |
1658 for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += MIPS_INSN16_SIZE) | 2310 for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += MIPS_INSN16_SIZE) |
1659 { | 2311 { |
1660 /* Save the previous instruction. If it's an EXTEND, we'll extract | 2312 /* Save the previous instruction. If it's an EXTEND, we'll extract |
1661 the immediate offset extension from it in mips16_get_imm. */ | 2313 the immediate offset extension from it in mips16_get_imm. */ |
1662 prev_inst = inst; | 2314 prev_inst = inst; |
1663 | 2315 |
1664 /* Fetch and decode the instruction. */ | 2316 /* Fetch and decode the instruction. */ |
1665 inst = (unsigned short) mips_fetch_instruction (gdbarch, cur_pc); | 2317 inst = (unsigned short) mips_fetch_instruction (gdbarch, ISA_MIPS16, |
| 2318 » » » » » » cur_pc, NULL); |
1666 | 2319 |
1667 /* Normally we ignore extend instructions. However, if it is | 2320 /* Normally we ignore extend instructions. However, if it is |
1668 not followed by a valid prologue instruction, then this | 2321 not followed by a valid prologue instruction, then this |
1669 instruction is not part of the prologue either. We must | 2322 instruction is not part of the prologue either. We must |
1670 remember in this case to adjust the end_prologue_addr back | 2323 remember in this case to adjust the end_prologue_addr back |
1671 over the extend. */ | 2324 over the extend. */ |
1672 if ((inst & 0xf800) == 0xf000) /* extend */ | 2325 if ((inst & 0xf800) == 0xf000) /* extend */ |
1673 { | 2326 { |
1674 extend_bytes = MIPS_INSN16_SIZE; | 2327 extend_bytes = MIPS_INSN16_SIZE; |
1675 continue; | 2328 continue; |
(...skipping 10 matching lines...) Expand all Loading... |
1686 frame_offset -= offset; | 2339 frame_offset -= offset; |
1687 else | 2340 else |
1688 /* Exit loop if a positive stack adjustment is found, which | 2341 /* Exit loop if a positive stack adjustment is found, which |
1689 usually means that the stack cleanup code in the function | 2342 usually means that the stack cleanup code in the function |
1690 epilogue is reached. */ | 2343 epilogue is reached. */ |
1691 break; | 2344 break; |
1692 } | 2345 } |
1693 else if ((inst & 0xf800) == 0xd000) /* sw reg,n($sp) */ | 2346 else if ((inst & 0xf800) == 0xd000) /* sw reg,n($sp) */ |
1694 { | 2347 { |
1695 offset = mips16_get_imm (prev_inst, inst, 8, 4, 0); | 2348 offset = mips16_get_imm (prev_inst, inst, 8, 4, 0); |
1696 » reg = mips16_to_32_reg[(inst & 0x700) >> 8]; | 2349 » reg = mips_reg3_to_reg[(inst & 0x700) >> 8]; |
1697 set_reg_offset (gdbarch, this_cache, reg, sp + offset); | 2350 set_reg_offset (gdbarch, this_cache, reg, sp + offset); |
1698 } | 2351 } |
1699 else if ((inst & 0xff00) == 0xf900) /* sd reg,n($sp) */ | 2352 else if ((inst & 0xff00) == 0xf900) /* sd reg,n($sp) */ |
1700 { | 2353 { |
1701 offset = mips16_get_imm (prev_inst, inst, 5, 8, 0); | 2354 offset = mips16_get_imm (prev_inst, inst, 5, 8, 0); |
1702 » reg = mips16_to_32_reg[(inst & 0xe0) >> 5]; | 2355 » reg = mips_reg3_to_reg[(inst & 0xe0) >> 5]; |
1703 set_reg_offset (gdbarch, this_cache, reg, sp + offset); | 2356 set_reg_offset (gdbarch, this_cache, reg, sp + offset); |
1704 } | 2357 } |
1705 else if ((inst & 0xff00) == 0x6200) /* sw $ra,n($sp) */ | 2358 else if ((inst & 0xff00) == 0x6200) /* sw $ra,n($sp) */ |
1706 { | 2359 { |
1707 offset = mips16_get_imm (prev_inst, inst, 8, 4, 0); | 2360 offset = mips16_get_imm (prev_inst, inst, 8, 4, 0); |
1708 set_reg_offset (gdbarch, this_cache, MIPS_RA_REGNUM, sp + offset); | 2361 set_reg_offset (gdbarch, this_cache, MIPS_RA_REGNUM, sp + offset); |
1709 } | 2362 } |
1710 else if ((inst & 0xff00) == 0xfa00) /* sd $ra,n($sp) */ | 2363 else if ((inst & 0xff00) == 0xfa00) /* sd $ra,n($sp) */ |
1711 { | 2364 { |
1712 offset = mips16_get_imm (prev_inst, inst, 8, 8, 0); | 2365 offset = mips16_get_imm (prev_inst, inst, 8, 8, 0); |
1713 set_reg_offset (gdbarch, this_cache, MIPS_RA_REGNUM, sp + offset); | 2366 set_reg_offset (gdbarch, this_cache, MIPS_RA_REGNUM, sp + offset); |
1714 } | 2367 } |
1715 else if (inst == 0x673d) /* move $s1, $sp */ | 2368 else if (inst == 0x673d) /* move $s1, $sp */ |
1716 { | 2369 { |
1717 frame_addr = sp; | 2370 frame_addr = sp; |
1718 frame_reg = 17; | 2371 frame_reg = 17; |
1719 } | 2372 } |
1720 else if ((inst & 0xff00) == 0x0100) /* addiu $s1,sp,n */ | 2373 else if ((inst & 0xff00) == 0x0100) /* addiu $s1,sp,n */ |
1721 { | 2374 { |
1722 offset = mips16_get_imm (prev_inst, inst, 8, 4, 0); | 2375 offset = mips16_get_imm (prev_inst, inst, 8, 4, 0); |
1723 frame_addr = sp + offset; | 2376 frame_addr = sp + offset; |
1724 frame_reg = 17; | 2377 frame_reg = 17; |
1725 frame_adjust = offset; | 2378 frame_adjust = offset; |
1726 } | 2379 } |
1727 else if ((inst & 0xFF00) == 0xd900) /* sw reg,offset($s1) */ | 2380 else if ((inst & 0xFF00) == 0xd900) /* sw reg,offset($s1) */ |
1728 { | 2381 { |
1729 offset = mips16_get_imm (prev_inst, inst, 5, 4, 0); | 2382 offset = mips16_get_imm (prev_inst, inst, 5, 4, 0); |
1730 » reg = mips16_to_32_reg[(inst & 0xe0) >> 5]; | 2383 » reg = mips_reg3_to_reg[(inst & 0xe0) >> 5]; |
1731 set_reg_offset (gdbarch, this_cache, reg, frame_addr + offset); | 2384 set_reg_offset (gdbarch, this_cache, reg, frame_addr + offset); |
1732 } | 2385 } |
1733 else if ((inst & 0xFF00) == 0x7900) /* sd reg,offset($s1) */ | 2386 else if ((inst & 0xFF00) == 0x7900) /* sd reg,offset($s1) */ |
1734 { | 2387 { |
1735 offset = mips16_get_imm (prev_inst, inst, 5, 8, 0); | 2388 offset = mips16_get_imm (prev_inst, inst, 5, 8, 0); |
1736 » reg = mips16_to_32_reg[(inst & 0xe0) >> 5]; | 2389 » reg = mips_reg3_to_reg[(inst & 0xe0) >> 5]; |
1737 set_reg_offset (gdbarch, this_cache, reg, frame_addr + offset); | 2390 set_reg_offset (gdbarch, this_cache, reg, frame_addr + offset); |
1738 } | 2391 } |
1739 else if ((inst & 0xf81f) == 0xe809 | 2392 else if ((inst & 0xf81f) == 0xe809 |
1740 && (inst & 0x700) != 0x700) /* entry */ | 2393 && (inst & 0x700) != 0x700) /* entry */ |
1741 entry_inst = inst; /* Save for later processing. */ | 2394 entry_inst = inst; /* Save for later processing. */ |
1742 else if ((inst & 0xff80) == 0x6480) /* save */ | 2395 else if ((inst & 0xff80) == 0x6480) /* save */ |
1743 { | 2396 { |
1744 save_inst = inst; /* Save for later processing. */ | 2397 save_inst = inst; /* Save for later processing. */ |
1745 if (prev_extend_bytes) /* extend */ | 2398 if (prev_extend_bytes) /* extend */ |
1746 save_inst |= prev_inst << 16; | 2399 save_inst |= prev_inst << 16; |
(...skipping 232 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... |
1979 { | 2632 { |
1980 struct mips_frame_cache *info = mips_insn16_frame_cache (this_frame, | 2633 struct mips_frame_cache *info = mips_insn16_frame_cache (this_frame, |
1981 this_cache); | 2634 this_cache); |
1982 return trad_frame_get_prev_register (this_frame, info->saved_regs, regnum); | 2635 return trad_frame_get_prev_register (this_frame, info->saved_regs, regnum); |
1983 } | 2636 } |
1984 | 2637 |
1985 static int | 2638 static int |
1986 mips_insn16_frame_sniffer (const struct frame_unwind *self, | 2639 mips_insn16_frame_sniffer (const struct frame_unwind *self, |
1987 struct frame_info *this_frame, void **this_cache) | 2640 struct frame_info *this_frame, void **this_cache) |
1988 { | 2641 { |
| 2642 struct gdbarch *gdbarch = get_frame_arch (this_frame); |
1989 CORE_ADDR pc = get_frame_pc (this_frame); | 2643 CORE_ADDR pc = get_frame_pc (this_frame); |
1990 if (mips_pc_is_mips16 (pc)) | 2644 if (mips_pc_is_mips16 (gdbarch, pc)) |
1991 return 1; | 2645 return 1; |
1992 return 0; | 2646 return 0; |
1993 } | 2647 } |
1994 | 2648 |
1995 static const struct frame_unwind mips_insn16_frame_unwind = | 2649 static const struct frame_unwind mips_insn16_frame_unwind = |
1996 { | 2650 { |
1997 NORMAL_FRAME, | 2651 NORMAL_FRAME, |
1998 default_frame_unwind_stop_reason, | 2652 default_frame_unwind_stop_reason, |
1999 mips_insn16_frame_this_id, | 2653 mips_insn16_frame_this_id, |
2000 mips_insn16_frame_prev_register, | 2654 mips_insn16_frame_prev_register, |
(...skipping 14 matching lines...) Expand all Loading... |
2015 { | 2669 { |
2016 &mips_insn16_frame_unwind, | 2670 &mips_insn16_frame_unwind, |
2017 mips_insn16_frame_base_address, | 2671 mips_insn16_frame_base_address, |
2018 mips_insn16_frame_base_address, | 2672 mips_insn16_frame_base_address, |
2019 mips_insn16_frame_base_address | 2673 mips_insn16_frame_base_address |
2020 }; | 2674 }; |
2021 | 2675 |
2022 static const struct frame_base * | 2676 static const struct frame_base * |
2023 mips_insn16_frame_base_sniffer (struct frame_info *this_frame) | 2677 mips_insn16_frame_base_sniffer (struct frame_info *this_frame) |
2024 { | 2678 { |
| 2679 struct gdbarch *gdbarch = get_frame_arch (this_frame); |
2025 CORE_ADDR pc = get_frame_pc (this_frame); | 2680 CORE_ADDR pc = get_frame_pc (this_frame); |
2026 if (mips_pc_is_mips16 (pc)) | 2681 if (mips_pc_is_mips16 (gdbarch, pc)) |
2027 return &mips_insn16_frame_base; | 2682 return &mips_insn16_frame_base; |
2028 else | 2683 else |
2029 return NULL; | 2684 return NULL; |
2030 } | 2685 } |
| 2686 |
| 2687 /* Decode a 9-bit signed immediate argument of ADDIUSP -- -2 is mapped |
| 2688 to -258, -1 -- to -257, 0 -- to 256, 1 -- to 257 and other values are |
| 2689 interpreted directly, and then multiplied by 4. */ |
| 2690 |
| 2691 static int |
| 2692 micromips_decode_imm9 (int imm) |
| 2693 { |
| 2694 imm = (imm ^ 0x100) - 0x100; |
| 2695 if (imm > -3 && imm < 2) |
| 2696 imm ^= 0x100; |
| 2697 return imm << 2; |
| 2698 } |
| 2699 |
| 2700 /* Analyze the function prologue from START_PC to LIMIT_PC. Return |
| 2701 the address of the first instruction past the prologue. */ |
| 2702 |
| 2703 static CORE_ADDR |
| 2704 micromips_scan_prologue (struct gdbarch *gdbarch, |
| 2705 CORE_ADDR start_pc, CORE_ADDR limit_pc, |
| 2706 struct frame_info *this_frame, |
| 2707 struct mips_frame_cache *this_cache) |
| 2708 { |
| 2709 CORE_ADDR end_prologue_addr = 0; |
| 2710 int prev_non_prologue_insn = 0; |
| 2711 int frame_reg = MIPS_SP_REGNUM; |
| 2712 int this_non_prologue_insn; |
| 2713 int non_prologue_insns = 0; |
| 2714 long frame_offset = 0; /* Size of stack frame. */ |
| 2715 long frame_adjust = 0; /* Offset of FP from SP. */ |
| 2716 CORE_ADDR frame_addr = 0; /* Value of $30, used as frame pointer. */ |
| 2717 CORE_ADDR prev_pc; |
| 2718 CORE_ADDR cur_pc; |
| 2719 ULONGEST insn; /* current instruction */ |
| 2720 CORE_ADDR sp; |
| 2721 long offset; |
| 2722 long sp_adj; |
| 2723 long v1_off = 0; /* The assumption is LUI will replace it. */ |
| 2724 int reglist; |
| 2725 int breg; |
| 2726 int dreg; |
| 2727 int sreg; |
| 2728 int treg; |
| 2729 int loc; |
| 2730 int op; |
| 2731 int s; |
| 2732 int i; |
| 2733 |
| 2734 /* Can be called when there's no process, and hence when there's no |
| 2735 THIS_FRAME. */ |
| 2736 if (this_frame != NULL) |
| 2737 sp = get_frame_register_signed (this_frame, |
| 2738 gdbarch_num_regs (gdbarch) |
| 2739 + MIPS_SP_REGNUM); |
| 2740 else |
| 2741 sp = 0; |
| 2742 |
| 2743 if (limit_pc > start_pc + 200) |
| 2744 limit_pc = start_pc + 200; |
| 2745 prev_pc = start_pc; |
| 2746 |
| 2747 /* Permit at most one non-prologue non-control-transfer instruction |
| 2748 in the middle which may have been reordered by the compiler for |
| 2749 optimisation. */ |
| 2750 for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += loc) |
| 2751 { |
| 2752 this_non_prologue_insn = 0; |
| 2753 sp_adj = 0; |
| 2754 loc = 0; |
| 2755 insn = mips_fetch_instruction (gdbarch, ISA_MICROMIPS, cur_pc, NULL); |
| 2756 loc += MIPS_INSN16_SIZE; |
| 2757 switch (mips_insn_size (ISA_MICROMIPS, insn)) |
| 2758 { |
| 2759 /* 48-bit instructions. */ |
| 2760 case 3 * MIPS_INSN16_SIZE: |
| 2761 /* No prologue instructions in this category. */ |
| 2762 this_non_prologue_insn = 1; |
| 2763 loc += 2 * MIPS_INSN16_SIZE; |
| 2764 break; |
| 2765 |
| 2766 /* 32-bit instructions. */ |
| 2767 case 2 * MIPS_INSN16_SIZE: |
| 2768 insn <<= 16; |
| 2769 insn |= mips_fetch_instruction (gdbarch, |
| 2770 ISA_MICROMIPS, cur_pc + loc, NULL); |
| 2771 loc += MIPS_INSN16_SIZE; |
| 2772 switch (micromips_op (insn >> 16)) |
| 2773 { |
| 2774 /* Record $sp/$fp adjustment. */ |
| 2775 /* Discard (D)ADDU $gp,$jp used for PIC code. */ |
| 2776 case 0x0: /* POOL32A: bits 000000 */ |
| 2777 case 0x16: /* POOL32S: bits 010110 */ |
| 2778 op = b0s11_op (insn); |
| 2779 sreg = b0s5_reg (insn >> 16); |
| 2780 treg = b5s5_reg (insn >> 16); |
| 2781 dreg = b11s5_reg (insn); |
| 2782 if (op == 0x1d0 |
| 2783 /* SUBU: bits 000000 00111010000 */ |
| 2784 /* DSUBU: bits 010110 00111010000 */ |
| 2785 && dreg == MIPS_SP_REGNUM && sreg == MIPS_SP_REGNUM |
| 2786 && treg == 3) |
| 2787 /* (D)SUBU $sp, $v1 */ |
| 2788 sp_adj = v1_off; |
| 2789 else if (op != 0x150 |
| 2790 /* ADDU: bits 000000 00101010000 */ |
| 2791 /* DADDU: bits 010110 00101010000 */ |
| 2792 || dreg != 28 || sreg != 28 || treg != MIPS_T9_REGNUM) |
| 2793 this_non_prologue_insn = 1; |
| 2794 break; |
| 2795 |
| 2796 case 0x8: /* POOL32B: bits 001000 */ |
| 2797 op = b12s4_op (insn); |
| 2798 breg = b0s5_reg (insn >> 16); |
| 2799 reglist = sreg = b5s5_reg (insn >> 16); |
| 2800 offset = (b0s12_imm (insn) ^ 0x800) - 0x800; |
| 2801 if ((op == 0x9 || op == 0xc) |
| 2802 /* SWP: bits 001000 1001 */ |
| 2803 /* SDP: bits 001000 1100 */ |
| 2804 && breg == MIPS_SP_REGNUM && sreg < MIPS_RA_REGNUM) |
| 2805 /* S[DW]P reg,offset($sp) */ |
| 2806 { |
| 2807 s = 4 << ((b12s4_op (insn) & 0x4) == 0x4); |
| 2808 set_reg_offset (gdbarch, this_cache, |
| 2809 sreg, sp + offset); |
| 2810 set_reg_offset (gdbarch, this_cache, |
| 2811 sreg + 1, sp + offset + s); |
| 2812 } |
| 2813 else if ((op == 0xd || op == 0xf) |
| 2814 /* SWM: bits 001000 1101 */ |
| 2815 /* SDM: bits 001000 1111 */ |
| 2816 && breg == MIPS_SP_REGNUM |
| 2817 /* SWM reglist,offset($sp) */ |
| 2818 && ((reglist >= 1 && reglist <= 9) |
| 2819 || (reglist >= 16 && reglist <= 25))) |
| 2820 { |
| 2821 int sreglist = min(reglist & 0xf, 8); |
| 2822 |
| 2823 s = 4 << ((b12s4_op (insn) & 0x2) == 0x2); |
| 2824 for (i = 0; i < sreglist; i++) |
| 2825 set_reg_offset (gdbarch, this_cache, 16 + i, sp + s * i); |
| 2826 if ((reglist & 0xf) > 8) |
| 2827 set_reg_offset (gdbarch, this_cache, 30, sp + s * i++); |
| 2828 if ((reglist & 0x10) == 0x10) |
| 2829 set_reg_offset (gdbarch, this_cache, |
| 2830 MIPS_RA_REGNUM, sp + s * i++); |
| 2831 } |
| 2832 else |
| 2833 this_non_prologue_insn = 1; |
| 2834 break; |
| 2835 |
| 2836 /* Record $sp/$fp adjustment. */ |
| 2837 /* Discard (D)ADDIU $gp used for PIC code. */ |
| 2838 case 0xc: /* ADDIU: bits 001100 */ |
| 2839 case 0x17: /* DADDIU: bits 010111 */ |
| 2840 sreg = b0s5_reg (insn >> 16); |
| 2841 dreg = b5s5_reg (insn >> 16); |
| 2842 offset = (b0s16_imm (insn) ^ 0x8000) - 0x8000; |
| 2843 if (sreg == MIPS_SP_REGNUM && dreg == MIPS_SP_REGNUM) |
| 2844 /* (D)ADDIU $sp, imm */ |
| 2845 sp_adj = offset; |
| 2846 else if (sreg == MIPS_SP_REGNUM && dreg == 30) |
| 2847 /* (D)ADDIU $fp, $sp, imm */ |
| 2848 { |
| 2849 frame_addr = sp + offset; |
| 2850 frame_adjust = offset; |
| 2851 frame_reg = 30; |
| 2852 } |
| 2853 else if (sreg != 28 || dreg != 28) |
| 2854 /* (D)ADDIU $gp, imm */ |
| 2855 this_non_prologue_insn = 1; |
| 2856 break; |
| 2857 |
| 2858 /* LUI $v1 is used for larger $sp adjustments. */ |
| 2859 /* Discard LUI $gp is used for PIC code. */ |
| 2860 case 0x10: /* POOL32I: bits 010000 */ |
| 2861 if (b5s5_op (insn >> 16) == 0xd |
| 2862 /* LUI: bits 010000 001101 */ |
| 2863 && b0s5_reg (insn >> 16) == 3) |
| 2864 /* LUI $v1, imm */ |
| 2865 v1_off = ((b0s16_imm (insn) << 16) ^ 0x80000000) - 0x80000000; |
| 2866 else if (b5s5_op (insn >> 16) != 0xd |
| 2867 /* LUI: bits 010000 001101 */ |
| 2868 || b0s5_reg (insn >> 16) != 28) |
| 2869 /* LUI $gp, imm */ |
| 2870 this_non_prologue_insn = 1; |
| 2871 break; |
| 2872 |
| 2873 /* ORI $v1 is used for larger $sp adjustments. */ |
| 2874 case 0x14: /* ORI: bits 010100 */ |
| 2875 sreg = b0s5_reg (insn >> 16); |
| 2876 dreg = b5s5_reg (insn >> 16); |
| 2877 if (sreg == 3 && dreg == 3) |
| 2878 /* ORI $v1, imm */ |
| 2879 v1_off |= b0s16_imm (insn); |
| 2880 else |
| 2881 this_non_prologue_insn = 1; |
| 2882 break; |
| 2883 |
| 2884 case 0x26: /* SWC1: bits 100110 */ |
| 2885 case 0x2e: /* SDC1: bits 101110 */ |
| 2886 breg = b0s5_reg (insn >> 16); |
| 2887 if (breg != MIPS_SP_REGNUM) |
| 2888 /* S[DW]C1 reg,offset($sp) */ |
| 2889 this_non_prologue_insn = 1; |
| 2890 break; |
| 2891 |
| 2892 case 0x36: /* SD: bits 110110 */ |
| 2893 case 0x3e: /* SW: bits 111110 */ |
| 2894 breg = b0s5_reg (insn >> 16); |
| 2895 sreg = b5s5_reg (insn >> 16); |
| 2896 offset = (b0s16_imm (insn) ^ 0x8000) - 0x8000; |
| 2897 if (breg == MIPS_SP_REGNUM) |
| 2898 /* S[DW] reg,offset($sp) */ |
| 2899 set_reg_offset (gdbarch, this_cache, sreg, sp + offset); |
| 2900 else |
| 2901 this_non_prologue_insn = 1; |
| 2902 break; |
| 2903 |
| 2904 default: |
| 2905 this_non_prologue_insn = 1; |
| 2906 break; |
| 2907 } |
| 2908 break; |
| 2909 |
| 2910 /* 16-bit instructions. */ |
| 2911 case MIPS_INSN16_SIZE: |
| 2912 switch (micromips_op (insn)) |
| 2913 { |
| 2914 case 0x3: /* MOVE: bits 000011 */ |
| 2915 sreg = b0s5_reg (insn); |
| 2916 dreg = b5s5_reg (insn); |
| 2917 if (sreg == MIPS_SP_REGNUM && dreg == 30) |
| 2918 /* MOVE $fp, $sp */ |
| 2919 { |
| 2920 frame_addr = sp; |
| 2921 frame_reg = 30; |
| 2922 } |
| 2923 else if ((sreg & 0x1c) != 0x4) |
| 2924 /* MOVE reg, $a0-$a3 */ |
| 2925 this_non_prologue_insn = 1; |
| 2926 break; |
| 2927 |
| 2928 case 0x11: /* POOL16C: bits 010001 */ |
| 2929 if (b6s4_op (insn) == 0x5) |
| 2930 /* SWM: bits 010001 0101 */ |
| 2931 { |
| 2932 offset = ((b0s4_imm (insn) << 2) ^ 0x20) - 0x20; |
| 2933 reglist = b4s2_regl (insn); |
| 2934 for (i = 0; i <= reglist; i++) |
| 2935 set_reg_offset (gdbarch, this_cache, 16 + i, sp + 4 * i); |
| 2936 set_reg_offset (gdbarch, this_cache, |
| 2937 MIPS_RA_REGNUM, sp + 4 * i++); |
| 2938 } |
| 2939 else |
| 2940 this_non_prologue_insn = 1; |
| 2941 break; |
| 2942 |
| 2943 case 0x13: /* POOL16D: bits 010011 */ |
| 2944 if ((insn & 0x1) == 0x1) |
| 2945 /* ADDIUSP: bits 010011 1 */ |
| 2946 sp_adj = micromips_decode_imm9 (b1s9_imm (insn)); |
| 2947 else if (b5s5_reg (insn) == MIPS_SP_REGNUM) |
| 2948 /* ADDIUS5: bits 010011 0 */ |
| 2949 /* ADDIUS5 $sp, imm */ |
| 2950 sp_adj = (b1s4_imm (insn) ^ 8) - 8; |
| 2951 else |
| 2952 this_non_prologue_insn = 1; |
| 2953 break; |
| 2954 |
| 2955 case 0x32: /* SWSP: bits 110010 */ |
| 2956 offset = b0s5_imm (insn) << 2; |
| 2957 sreg = b5s5_reg (insn); |
| 2958 set_reg_offset (gdbarch, this_cache, sreg, sp + offset); |
| 2959 break; |
| 2960 |
| 2961 default: |
| 2962 this_non_prologue_insn = 1; |
| 2963 break; |
| 2964 } |
| 2965 break; |
| 2966 } |
| 2967 if (sp_adj < 0) |
| 2968 frame_offset -= sp_adj; |
| 2969 |
| 2970 non_prologue_insns += this_non_prologue_insn; |
| 2971 /* Enough non-prologue insns seen or positive stack adjustment? */ |
| 2972 if (end_prologue_addr == 0 && (non_prologue_insns > 1 || sp_adj > 0)) |
| 2973 { |
| 2974 end_prologue_addr = prev_non_prologue_insn ? prev_pc : cur_pc; |
| 2975 break; |
| 2976 } |
| 2977 prev_non_prologue_insn = this_non_prologue_insn; |
| 2978 prev_pc = cur_pc; |
| 2979 } |
| 2980 |
| 2981 if (this_cache != NULL) |
| 2982 { |
| 2983 this_cache->base = |
| 2984 (get_frame_register_signed (this_frame, |
| 2985 gdbarch_num_regs (gdbarch) + frame_reg) |
| 2986 + frame_offset - frame_adjust); |
| 2987 /* FIXME: brobecker/2004-10-10: Just as in the mips32 case, we should |
| 2988 be able to get rid of the assignment below, evetually. But it's |
| 2989 still needed for now. */ |
| 2990 this_cache->saved_regs[gdbarch_num_regs (gdbarch) |
| 2991 + mips_regnum (gdbarch)->pc] |
| 2992 = this_cache->saved_regs[gdbarch_num_regs (gdbarch) + MIPS_RA_REGNUM]; |
| 2993 } |
| 2994 |
| 2995 /* If we didn't reach the end of the prologue when scanning the function |
| 2996 instructions, then set end_prologue_addr to the address of the |
| 2997 instruction immediately after the last one we scanned. Unless the |
| 2998 last one looked like a non-prologue instruction (and we looked ahead), |
| 2999 in which case use its address instead. */ |
| 3000 if (end_prologue_addr == 0) |
| 3001 end_prologue_addr = prev_non_prologue_insn ? prev_pc : cur_pc; |
| 3002 |
| 3003 return end_prologue_addr; |
| 3004 } |
| 3005 |
| 3006 /* Heuristic unwinder for procedures using microMIPS instructions. |
| 3007 Procedures that use the 32-bit instruction set are handled by the |
| 3008 mips_insn32 unwinder. Likewise MIPS16 and the mips_insn16 unwinder. */ |
| 3009 |
| 3010 static struct mips_frame_cache * |
| 3011 mips_micro_frame_cache (struct frame_info *this_frame, void **this_cache) |
| 3012 { |
| 3013 struct gdbarch *gdbarch = get_frame_arch (this_frame); |
| 3014 struct mips_frame_cache *cache; |
| 3015 |
| 3016 if ((*this_cache) != NULL) |
| 3017 return (*this_cache); |
| 3018 |
| 3019 cache = FRAME_OBSTACK_ZALLOC (struct mips_frame_cache); |
| 3020 (*this_cache) = cache; |
| 3021 cache->saved_regs = trad_frame_alloc_saved_regs (this_frame); |
| 3022 |
| 3023 /* Analyze the function prologue. */ |
| 3024 { |
| 3025 const CORE_ADDR pc = get_frame_address_in_block (this_frame); |
| 3026 CORE_ADDR start_addr; |
| 3027 |
| 3028 find_pc_partial_function (pc, NULL, &start_addr, NULL); |
| 3029 if (start_addr == 0) |
| 3030 start_addr = heuristic_proc_start (get_frame_arch (this_frame), pc); |
| 3031 /* We can't analyze the prologue if we couldn't find the begining |
| 3032 of the function. */ |
| 3033 if (start_addr == 0) |
| 3034 return cache; |
| 3035 |
| 3036 micromips_scan_prologue (gdbarch, start_addr, pc, this_frame, *this_cache); |
| 3037 } |
| 3038 |
| 3039 /* gdbarch_sp_regnum contains the value and not the address. */ |
| 3040 trad_frame_set_value (cache->saved_regs, |
| 3041 gdbarch_num_regs (gdbarch) + MIPS_SP_REGNUM, |
| 3042 cache->base); |
| 3043 |
| 3044 return (*this_cache); |
| 3045 } |
| 3046 |
| 3047 static void |
| 3048 mips_micro_frame_this_id (struct frame_info *this_frame, void **this_cache, |
| 3049 struct frame_id *this_id) |
| 3050 { |
| 3051 struct mips_frame_cache *info = mips_micro_frame_cache (this_frame, |
| 3052 this_cache); |
| 3053 /* This marks the outermost frame. */ |
| 3054 if (info->base == 0) |
| 3055 return; |
| 3056 (*this_id) = frame_id_build (info->base, get_frame_func (this_frame)); |
| 3057 } |
| 3058 |
| 3059 static struct value * |
| 3060 mips_micro_frame_prev_register (struct frame_info *this_frame, |
| 3061 void **this_cache, int regnum) |
| 3062 { |
| 3063 struct mips_frame_cache *info = mips_micro_frame_cache (this_frame, |
| 3064 this_cache); |
| 3065 return trad_frame_get_prev_register (this_frame, info->saved_regs, regnum); |
| 3066 } |
| 3067 |
| 3068 static int |
| 3069 mips_micro_frame_sniffer (const struct frame_unwind *self, |
| 3070 struct frame_info *this_frame, void **this_cache) |
| 3071 { |
| 3072 struct gdbarch *gdbarch = get_frame_arch (this_frame); |
| 3073 CORE_ADDR pc = get_frame_pc (this_frame); |
| 3074 |
| 3075 if (mips_pc_is_micromips (gdbarch, pc)) |
| 3076 return 1; |
| 3077 return 0; |
| 3078 } |
| 3079 |
| 3080 static const struct frame_unwind mips_micro_frame_unwind = |
| 3081 { |
| 3082 NORMAL_FRAME, |
| 3083 default_frame_unwind_stop_reason, |
| 3084 mips_micro_frame_this_id, |
| 3085 mips_micro_frame_prev_register, |
| 3086 NULL, |
| 3087 mips_micro_frame_sniffer |
| 3088 }; |
| 3089 |
| 3090 static CORE_ADDR |
| 3091 mips_micro_frame_base_address (struct frame_info *this_frame, |
| 3092 void **this_cache) |
| 3093 { |
| 3094 struct mips_frame_cache *info = mips_micro_frame_cache (this_frame, |
| 3095 this_cache); |
| 3096 return info->base; |
| 3097 } |
| 3098 |
| 3099 static const struct frame_base mips_micro_frame_base = |
| 3100 { |
| 3101 &mips_micro_frame_unwind, |
| 3102 mips_micro_frame_base_address, |
| 3103 mips_micro_frame_base_address, |
| 3104 mips_micro_frame_base_address |
| 3105 }; |
| 3106 |
| 3107 static const struct frame_base * |
| 3108 mips_micro_frame_base_sniffer (struct frame_info *this_frame) |
| 3109 { |
| 3110 struct gdbarch *gdbarch = get_frame_arch (this_frame); |
| 3111 CORE_ADDR pc = get_frame_pc (this_frame); |
| 3112 |
| 3113 if (mips_pc_is_micromips (gdbarch, pc)) |
| 3114 return &mips_micro_frame_base; |
| 3115 else |
| 3116 return NULL; |
| 3117 } |
2031 | 3118 |
2032 /* Mark all the registers as unset in the saved_regs array | 3119 /* Mark all the registers as unset in the saved_regs array |
2033 of THIS_CACHE. Do nothing if THIS_CACHE is null. */ | 3120 of THIS_CACHE. Do nothing if THIS_CACHE is null. */ |
2034 | 3121 |
2035 static void | 3122 static void |
2036 reset_saved_regs (struct gdbarch *gdbarch, struct mips_frame_cache *this_cache) | 3123 reset_saved_regs (struct gdbarch *gdbarch, struct mips_frame_cache *this_cache) |
2037 { | 3124 { |
2038 if (this_cache == NULL || this_cache->saved_regs == NULL) | 3125 if (this_cache == NULL || this_cache->saved_regs == NULL) |
2039 return; | 3126 return; |
2040 | 3127 |
(...skipping 45 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... |
2086 | 3173 |
2087 restart: | 3174 restart: |
2088 | 3175 |
2089 frame_offset = 0; | 3176 frame_offset = 0; |
2090 for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += MIPS_INSN32_SIZE) | 3177 for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += MIPS_INSN32_SIZE) |
2091 { | 3178 { |
2092 unsigned long inst, high_word, low_word; | 3179 unsigned long inst, high_word, low_word; |
2093 int reg; | 3180 int reg; |
2094 | 3181 |
2095 /* Fetch the instruction. */ | 3182 /* Fetch the instruction. */ |
2096 inst = (unsigned long) mips_fetch_instruction (gdbarch, cur_pc); | 3183 inst = (unsigned long) mips_fetch_instruction (gdbarch, ISA_MIPS, |
| 3184 » » » » » » cur_pc, NULL); |
2097 | 3185 |
2098 /* Save some code by pre-extracting some useful fields. */ | 3186 /* Save some code by pre-extracting some useful fields. */ |
2099 high_word = (inst >> 16) & 0xffff; | 3187 high_word = (inst >> 16) & 0xffff; |
2100 low_word = inst & 0xffff; | 3188 low_word = inst & 0xffff; |
2101 reg = high_word & 0x1f; | 3189 reg = high_word & 0x1f; |
2102 | 3190 |
2103 if (high_word == 0x27bd /* addiu $sp,$sp,-i */ | 3191 if (high_word == 0x27bd /* addiu $sp,$sp,-i */ |
2104 || high_word == 0x23bd /* addi $sp,$sp,-i */ | 3192 || high_word == 0x23bd /* addi $sp,$sp,-i */ |
2105 || high_word == 0x67bd) /* daddiu $sp,$sp,-i */ | 3193 || high_word == 0x67bd) /* daddiu $sp,$sp,-i */ |
2106 { | 3194 { |
(...skipping 82 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... |
2189 set_reg_offset (gdbarch, this_cache, reg, frame_addr + low_word); | 3277 set_reg_offset (gdbarch, this_cache, reg, frame_addr + low_word); |
2190 } | 3278 } |
2191 else if ((high_word & 0xFFE0) == 0xE7A0 /* swc1 freg,n($sp) */ | 3279 else if ((high_word & 0xFFE0) == 0xE7A0 /* swc1 freg,n($sp) */ |
2192 || (high_word & 0xF3E0) == 0xA3C0 /* sx reg,n($s8) */ | 3280 || (high_word & 0xF3E0) == 0xA3C0 /* sx reg,n($s8) */ |
2193 || (inst & 0xFF9F07FF) == 0x00800021 /* move reg,$a0-$a3 */ | 3281 || (inst & 0xFF9F07FF) == 0x00800021 /* move reg,$a0-$a3 */ |
2194 || high_word == 0x3c1c /* lui $gp,n */ | 3282 || high_word == 0x3c1c /* lui $gp,n */ |
2195 || high_word == 0x279c /* addiu $gp,$gp,n */ | 3283 || high_word == 0x279c /* addiu $gp,$gp,n */ |
2196 || inst == 0x0399e021 /* addu $gp,$gp,$t9 */ | 3284 || inst == 0x0399e021 /* addu $gp,$gp,$t9 */ |
2197 || inst == 0x033ce021 /* addu $gp,$t9,$gp */ | 3285 || inst == 0x033ce021 /* addu $gp,$t9,$gp */ |
2198 ) | 3286 ) |
2199 { | 3287 » { |
2200 /* These instructions are part of the prologue, but we don't | 3288 » /* These instructions are part of the prologue, but we don't |
2201 need to do anything special to handle them. */ | 3289 » need to do anything special to handle them. */ |
2202 } | 3290 » } |
2203 /* The instructions below load $at or $t0 with an immediate | 3291 /* The instructions below load $at or $t0 with an immediate |
2204 value in preparation for a stack adjustment via | 3292 value in preparation for a stack adjustment via |
2205 subu $sp,$sp,[$at,$t0]. These instructions could also | 3293 subu $sp,$sp,[$at,$t0]. These instructions could also |
2206 initialize a local variable, so we accept them only before | 3294 initialize a local variable, so we accept them only before |
2207 a stack adjustment instruction was seen. */ | 3295 a stack adjustment instruction was seen. */ |
2208 else if (!seen_sp_adjust | 3296 else if (!seen_sp_adjust |
2209 && (high_word == 0x3c01 /* lui $at,n */ | 3297 » && (high_word == 0x3c01 /* lui $at,n */ |
2210 || high_word == 0x3c08 /* lui $t0,n */ | 3298 » » || high_word == 0x3c08 /* lui $t0,n */ |
2211 || high_word == 0x3421 /* ori $at,$at,n */ | 3299 » » || high_word == 0x3421 /* ori $at,$at,n */ |
2212 || high_word == 0x3508 /* ori $t0,$t0,n */ | 3300 » » || high_word == 0x3508 /* ori $t0,$t0,n */ |
2213 || high_word == 0x3401 /* ori $at,$zero,n */ | 3301 » » || high_word == 0x3401 /* ori $at,$zero,n */ |
2214 || high_word == 0x3408 /* ori $t0,$zero,n */ | 3302 » » || high_word == 0x3408 /* ori $t0,$zero,n */ |
2215 )) | 3303 » » )) |
2216 { | 3304 » { |
2217 » if (end_prologue_addr == 0) | 3305 » if (end_prologue_addr == 0) |
2218 » load_immediate_bytes += MIPS_INSN32_SIZE;» » /* FIXME! */ | 3306 » load_immediate_bytes += MIPS_INSN32_SIZE;» » /* FIXME! */ |
2219 } | 3307 » } |
2220 else | 3308 else |
2221 { | 3309 » { |
2222 /* This instruction is not an instruction typically found | 3310 » /* This instruction is not an instruction typically found |
2223 in a prologue, so we must have reached the end of the | 3311 » in a prologue, so we must have reached the end of the |
2224 prologue. */ | 3312 » prologue. */ |
2225 /* FIXME: brobecker/2004-10-10: Can't we just break out of this | 3313 » /* FIXME: brobecker/2004-10-10: Can't we just break out of this |
2226 loop now? Why would we need to continue scanning the function | 3314 » loop now? Why would we need to continue scanning the function |
2227 instructions? */ | 3315 » instructions? */ |
2228 if (end_prologue_addr == 0) | 3316 » if (end_prologue_addr == 0) |
2229 end_prologue_addr = cur_pc; | 3317 » end_prologue_addr = cur_pc; |
2230 | 3318 |
2231 » /* Check for branches and jumps. For now, only jump to | 3319 » /* Check for branches and jumps. For now, only jump to |
2232 » register are caught (i.e. returns). */ | 3320 » register are caught (i.e. returns). */ |
2233 » if ((itype_op (inst) & 0x07) == 0 && rtype_funct (inst) == 8) | 3321 » if ((itype_op (inst) & 0x07) == 0 && rtype_funct (inst) == 8) |
2234 » in_delay_slot = 1; | 3322 » in_delay_slot = 1; |
2235 } | 3323 » } |
2236 | 3324 |
2237 /* If the previous instruction was a jump, we must have reached | 3325 /* If the previous instruction was a jump, we must have reached |
2238 the end of the prologue by now. Stop scanning so that we do | 3326 the end of the prologue by now. Stop scanning so that we do |
2239 not go past the function return. */ | 3327 not go past the function return. */ |
2240 if (in_delay_slot) | 3328 if (in_delay_slot) |
2241 break; | 3329 break; |
2242 } | 3330 } |
2243 | 3331 |
2244 if (this_cache != NULL) | 3332 if (this_cache != NULL) |
2245 { | 3333 { |
(...skipping 24 matching lines...) Expand all Loading... |
2270 if the load immediate was not followed by a stack adjustment. */ | 3358 if the load immediate was not followed by a stack adjustment. */ |
2271 if (load_immediate_bytes && !seen_sp_adjust) | 3359 if (load_immediate_bytes && !seen_sp_adjust) |
2272 end_prologue_addr -= load_immediate_bytes; | 3360 end_prologue_addr -= load_immediate_bytes; |
2273 | 3361 |
2274 return end_prologue_addr; | 3362 return end_prologue_addr; |
2275 } | 3363 } |
2276 | 3364 |
2277 /* Heuristic unwinder for procedures using 32-bit instructions (covers | 3365 /* Heuristic unwinder for procedures using 32-bit instructions (covers |
2278 both 32-bit and 64-bit MIPS ISAs). Procedures using 16-bit | 3366 both 32-bit and 64-bit MIPS ISAs). Procedures using 16-bit |
2279 instructions (a.k.a. MIPS16) are handled by the mips_insn16 | 3367 instructions (a.k.a. MIPS16) are handled by the mips_insn16 |
2280 unwinder. */ | 3368 unwinder. Likewise microMIPS and the mips_micro unwinder. */ |
2281 | 3369 |
2282 static struct mips_frame_cache * | 3370 static struct mips_frame_cache * |
2283 mips_insn32_frame_cache (struct frame_info *this_frame, void **this_cache) | 3371 mips_insn32_frame_cache (struct frame_info *this_frame, void **this_cache) |
2284 { | 3372 { |
2285 struct gdbarch *gdbarch = get_frame_arch (this_frame); | 3373 struct gdbarch *gdbarch = get_frame_arch (this_frame); |
2286 struct mips_frame_cache *cache; | 3374 struct mips_frame_cache *cache; |
2287 | 3375 |
2288 if ((*this_cache) != NULL) | 3376 if ((*this_cache) != NULL) |
2289 return (*this_cache); | 3377 return (*this_cache); |
2290 | 3378 |
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2335 struct mips_frame_cache *info = mips_insn32_frame_cache (this_frame, | 3423 struct mips_frame_cache *info = mips_insn32_frame_cache (this_frame, |
2336 this_cache); | 3424 this_cache); |
2337 return trad_frame_get_prev_register (this_frame, info->saved_regs, regnum); | 3425 return trad_frame_get_prev_register (this_frame, info->saved_regs, regnum); |
2338 } | 3426 } |
2339 | 3427 |
2340 static int | 3428 static int |
2341 mips_insn32_frame_sniffer (const struct frame_unwind *self, | 3429 mips_insn32_frame_sniffer (const struct frame_unwind *self, |
2342 struct frame_info *this_frame, void **this_cache) | 3430 struct frame_info *this_frame, void **this_cache) |
2343 { | 3431 { |
2344 CORE_ADDR pc = get_frame_pc (this_frame); | 3432 CORE_ADDR pc = get_frame_pc (this_frame); |
2345 if (! mips_pc_is_mips16 (pc)) | 3433 if (mips_pc_is_mips (pc)) |
2346 return 1; | 3434 return 1; |
2347 return 0; | 3435 return 0; |
2348 } | 3436 } |
2349 | 3437 |
2350 static const struct frame_unwind mips_insn32_frame_unwind = | 3438 static const struct frame_unwind mips_insn32_frame_unwind = |
2351 { | 3439 { |
2352 NORMAL_FRAME, | 3440 NORMAL_FRAME, |
2353 default_frame_unwind_stop_reason, | 3441 default_frame_unwind_stop_reason, |
2354 mips_insn32_frame_this_id, | 3442 mips_insn32_frame_this_id, |
2355 mips_insn32_frame_prev_register, | 3443 mips_insn32_frame_prev_register, |
(...skipping 15 matching lines...) Expand all Loading... |
2371 &mips_insn32_frame_unwind, | 3459 &mips_insn32_frame_unwind, |
2372 mips_insn32_frame_base_address, | 3460 mips_insn32_frame_base_address, |
2373 mips_insn32_frame_base_address, | 3461 mips_insn32_frame_base_address, |
2374 mips_insn32_frame_base_address | 3462 mips_insn32_frame_base_address |
2375 }; | 3463 }; |
2376 | 3464 |
2377 static const struct frame_base * | 3465 static const struct frame_base * |
2378 mips_insn32_frame_base_sniffer (struct frame_info *this_frame) | 3466 mips_insn32_frame_base_sniffer (struct frame_info *this_frame) |
2379 { | 3467 { |
2380 CORE_ADDR pc = get_frame_pc (this_frame); | 3468 CORE_ADDR pc = get_frame_pc (this_frame); |
2381 if (! mips_pc_is_mips16 (pc)) | 3469 if (mips_pc_is_mips (pc)) |
2382 return &mips_insn32_frame_base; | 3470 return &mips_insn32_frame_base; |
2383 else | 3471 else |
2384 return NULL; | 3472 return NULL; |
2385 } | 3473 } |
2386 | 3474 |
2387 static struct trad_frame_cache * | 3475 static struct trad_frame_cache * |
2388 mips_stub_frame_cache (struct frame_info *this_frame, void **this_cache) | 3476 mips_stub_frame_cache (struct frame_info *this_frame, void **this_cache) |
2389 { | 3477 { |
2390 CORE_ADDR pc; | 3478 CORE_ADDR pc; |
2391 CORE_ADDR start_addr; | 3479 CORE_ADDR start_addr; |
(...skipping 116 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... |
2508 return NULL; | 3596 return NULL; |
2509 } | 3597 } |
2510 | 3598 |
2511 /* mips_addr_bits_remove - remove useless address bits */ | 3599 /* mips_addr_bits_remove - remove useless address bits */ |
2512 | 3600 |
2513 static CORE_ADDR | 3601 static CORE_ADDR |
2514 mips_addr_bits_remove (struct gdbarch *gdbarch, CORE_ADDR addr) | 3602 mips_addr_bits_remove (struct gdbarch *gdbarch, CORE_ADDR addr) |
2515 { | 3603 { |
2516 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | 3604 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
2517 | 3605 |
2518 if (is_mips16_addr (addr)) | 3606 if (is_compact_addr (addr)) |
2519 addr = unmake_mips16_addr (addr); | 3607 addr = unmake_compact_addr (addr); |
2520 | 3608 |
2521 if (mips_mask_address_p (tdep) && (((ULONGEST) addr) >> 32 == 0xffffffffUL)) | 3609 if (mips_mask_address_p (tdep) && (((ULONGEST) addr) >> 32 == 0xffffffffUL)) |
2522 /* This hack is a work-around for existing boards using PMON, the | 3610 /* This hack is a work-around for existing boards using PMON, the |
2523 simulator, and any other 64-bit targets that doesn't have true | 3611 simulator, and any other 64-bit targets that doesn't have true |
2524 64-bit addressing. On these targets, the upper 32 bits of | 3612 64-bit addressing. On these targets, the upper 32 bits of |
2525 addresses are ignored by the hardware. Thus, the PC or SP are | 3613 addresses are ignored by the hardware. Thus, the PC or SP are |
2526 likely to have been sign extended to all 1s by instruction | 3614 likely to have been sign extended to all 1s by instruction |
2527 sequences that load 32-bit addresses. For example, a typical | 3615 sequences that load 32-bit addresses. For example, a typical |
2528 piece of code that loads an address is this: | 3616 piece of code that loads an address is this: |
2529 | 3617 |
2530 lui $r2, <upper 16 bits> | 3618 lui $r2, <upper 16 bits> |
2531 ori $r2, <lower 16 bits> | 3619 ori $r2, <lower 16 bits> |
2532 | 3620 |
2533 But the lui sign-extends the value such that the upper 32 bits | 3621 But the lui sign-extends the value such that the upper 32 bits |
2534 may be all 1s. The workaround is simply to mask off these | 3622 may be all 1s. The workaround is simply to mask off these |
2535 bits. In the future, gcc may be changed to support true 64-bit | 3623 bits. In the future, gcc may be changed to support true 64-bit |
2536 addressing, and this masking will have to be disabled. */ | 3624 addressing, and this masking will have to be disabled. */ |
2537 return addr &= 0xffffffffUL; | 3625 return addr &= 0xffffffffUL; |
2538 else | 3626 else |
2539 return addr; | 3627 return addr; |
2540 } | 3628 } |
2541 | 3629 |
2542 /* Instructions used during single-stepping of atomic sequences. */ | |
2543 #define LL_OPCODE 0x30 | |
2544 #define LLD_OPCODE 0x34 | |
2545 #define SC_OPCODE 0x38 | |
2546 #define SCD_OPCODE 0x3c | |
2547 | 3630 |
2548 /* Checks for an atomic sequence of instructions beginning with a LL/LLD | 3631 /* Checks for an atomic sequence of instructions beginning with a LL/LLD |
2549 instruction and ending with a SC/SCD instruction. If such a sequence | 3632 instruction and ending with a SC/SCD instruction. If such a sequence |
2550 is found, attempt to step through it. A breakpoint is placed at the end of | 3633 is found, attempt to step through it. A breakpoint is placed at the end of |
2551 the sequence. */ | 3634 the sequence. */ |
2552 | 3635 |
| 3636 /* Instructions used during single-stepping of atomic sequences, standard |
| 3637 ISA version. */ |
| 3638 #define LL_OPCODE 0x30 |
| 3639 #define LLD_OPCODE 0x34 |
| 3640 #define SC_OPCODE 0x38 |
| 3641 #define SCD_OPCODE 0x3c |
| 3642 |
2553 static int | 3643 static int |
2554 deal_with_atomic_sequence (struct gdbarch *gdbarch, | 3644 mips_deal_with_atomic_sequence (struct gdbarch *gdbarch, |
2555 » » » struct address_space *aspace, CORE_ADDR pc) | 3645 » » » » struct address_space *aspace, CORE_ADDR pc) |
2556 { | 3646 { |
2557 CORE_ADDR breaks[2] = {-1, -1}; | 3647 CORE_ADDR breaks[2] = {-1, -1}; |
2558 CORE_ADDR loc = pc; | 3648 CORE_ADDR loc = pc; |
2559 CORE_ADDR branch_bp; /* Breakpoint at branch instruction's destination. */ | 3649 CORE_ADDR branch_bp; /* Breakpoint at branch instruction's destination. */ |
2560 unsigned long insn; | 3650 ULONGEST insn; |
2561 int insn_count; | 3651 int insn_count; |
2562 int index; | 3652 int index; |
2563 int last_breakpoint = 0; /* Defaults to 0 (no breakpoints placed). */ | 3653 int last_breakpoint = 0; /* Defaults to 0 (no breakpoints placed). */ |
2564 const int atomic_sequence_length = 16; /* Instruction sequence length. */ | 3654 const int atomic_sequence_length = 16; /* Instruction sequence length. */ |
2565 | 3655 |
2566 if (pc & 0x01) | 3656 insn = mips_fetch_instruction (gdbarch, ISA_MIPS, loc, NULL); |
2567 return 0; | |
2568 | |
2569 insn = mips_fetch_instruction (gdbarch, loc); | |
2570 /* Assume all atomic sequences start with a ll/lld instruction. */ | 3657 /* Assume all atomic sequences start with a ll/lld instruction. */ |
2571 if (itype_op (insn) != LL_OPCODE && itype_op (insn) != LLD_OPCODE) | 3658 if (itype_op (insn) != LL_OPCODE && itype_op (insn) != LLD_OPCODE) |
2572 return 0; | 3659 return 0; |
2573 | 3660 |
2574 /* Assume that no atomic sequence is longer than "atomic_sequence_length" | 3661 /* Assume that no atomic sequence is longer than "atomic_sequence_length" |
2575 instructions. */ | 3662 instructions. */ |
2576 for (insn_count = 0; insn_count < atomic_sequence_length; ++insn_count) | 3663 for (insn_count = 0; insn_count < atomic_sequence_length; ++insn_count) |
2577 { | 3664 { |
2578 int is_branch = 0; | 3665 int is_branch = 0; |
2579 loc += MIPS_INSN32_SIZE; | 3666 loc += MIPS_INSN32_SIZE; |
2580 insn = mips_fetch_instruction (gdbarch, loc); | 3667 insn = mips_fetch_instruction (gdbarch, ISA_MIPS, loc, NULL); |
2581 | 3668 |
2582 /* Assume that there is at most one branch in the atomic | 3669 /* Assume that there is at most one branch in the atomic |
2583 sequence. If a branch is found, put a breakpoint in its | 3670 sequence. If a branch is found, put a breakpoint in its |
2584 destination address. */ | 3671 destination address. */ |
2585 switch (itype_op (insn)) | 3672 switch (itype_op (insn)) |
2586 { | 3673 { |
2587 case 0: /* SPECIAL */ | 3674 case 0: /* SPECIAL */ |
2588 if (rtype_funct (insn) >> 1 == 4) /* JR, JALR */ | 3675 if (rtype_funct (insn) >> 1 == 4) /* JR, JALR */ |
2589 return 0; /* fallback to the standard single-step code. */ | 3676 return 0; /* fallback to the standard single-step code. */ |
2590 break; | 3677 break; |
2591 case 1: /* REGIMM */ | 3678 case 1: /* REGIMM */ |
2592 » is_branch = ((itype_rt (insn) & 0xc) == 0); /* B{LT,GE}Z* */ | 3679 » is_branch = ((itype_rt (insn) & 0xc) == 0 /* B{LT,GE}Z* */ |
| 3680 » » || ((itype_rt (insn) & 0x1e) == 0 |
| 3681 » » » && itype_rs (insn) == 0)); /* BPOSGE* */ |
2593 break; | 3682 break; |
2594 case 2: /* J */ | 3683 case 2: /* J */ |
2595 case 3: /* JAL */ | 3684 case 3: /* JAL */ |
2596 return 0; /* fallback to the standard single-step code. */ | 3685 return 0; /* fallback to the standard single-step code. */ |
2597 case 4: /* BEQ */ | 3686 case 4: /* BEQ */ |
2598 case 5: /* BNE */ | 3687 case 5: /* BNE */ |
2599 case 6: /* BLEZ */ | 3688 case 6: /* BLEZ */ |
2600 case 7: /* BGTZ */ | 3689 case 7: /* BGTZ */ |
2601 case 20: /* BEQL */ | 3690 case 20: /* BEQL */ |
2602 case 21: /* BNEL */ | 3691 case 21: /* BNEL */ |
2603 case 22: /* BLEZL */ | 3692 case 22: /* BLEZL */ |
2604 case 23: /* BGTTL */ | 3693 case 23: /* BGTTL */ |
2605 is_branch = 1; | 3694 is_branch = 1; |
2606 break; | 3695 break; |
2607 case 17: /* COP1 */ | 3696 case 17: /* COP1 */ |
| 3697 is_branch = ((itype_rs (insn) == 9 || itype_rs (insn) == 10) |
| 3698 && (itype_rt (insn) & 0x2) == 0); |
| 3699 if (is_branch) /* BC1ANY2F, BC1ANY2T, BC1ANY4F, BC1ANY4T */ |
| 3700 break; |
| 3701 /* Fall through. */ |
2608 case 18: /* COP2 */ | 3702 case 18: /* COP2 */ |
2609 case 19: /* COP3 */ | 3703 case 19: /* COP3 */ |
2610 is_branch = (itype_rs (insn) == 8); /* BCzF, BCzFL, BCzT, BCzTL */ | 3704 is_branch = (itype_rs (insn) == 8); /* BCzF, BCzFL, BCzT, BCzTL */ |
2611 break; | 3705 break; |
2612 } | 3706 } |
2613 if (is_branch) | 3707 if (is_branch) |
2614 { | 3708 { |
2615 branch_bp = loc + mips32_relative_offset (insn) + 4; | 3709 branch_bp = loc + mips32_relative_offset (insn) + 4; |
2616 if (last_breakpoint >= 1) | 3710 if (last_breakpoint >= 1) |
2617 return 0; /* More than one branch found, fallback to the | 3711 return 0; /* More than one branch found, fallback to the |
(...skipping 20 matching lines...) Expand all Loading... |
2638 if (last_breakpoint && pc <= breaks[1] && breaks[1] <= breaks[0]) | 3732 if (last_breakpoint && pc <= breaks[1] && breaks[1] <= breaks[0]) |
2639 last_breakpoint = 0; | 3733 last_breakpoint = 0; |
2640 | 3734 |
2641 /* Effectively inserts the breakpoints. */ | 3735 /* Effectively inserts the breakpoints. */ |
2642 for (index = 0; index <= last_breakpoint; index++) | 3736 for (index = 0; index <= last_breakpoint; index++) |
2643 insert_single_step_breakpoint (gdbarch, aspace, breaks[index]); | 3737 insert_single_step_breakpoint (gdbarch, aspace, breaks[index]); |
2644 | 3738 |
2645 return 1; | 3739 return 1; |
2646 } | 3740 } |
2647 | 3741 |
| 3742 static int |
| 3743 micromips_deal_with_atomic_sequence (struct gdbarch *gdbarch, |
| 3744 struct address_space *aspace, |
| 3745 CORE_ADDR pc) |
| 3746 { |
| 3747 const int atomic_sequence_length = 16; /* Instruction sequence length. */ |
| 3748 int last_breakpoint = 0; /* Defaults to 0 (no breakpoints placed). */ |
| 3749 CORE_ADDR breaks[2] = {-1, -1}; |
| 3750 CORE_ADDR branch_bp; /* Breakpoint at branch instruction's destination. */ |
| 3751 CORE_ADDR loc = pc; |
| 3752 int sc_found = 0; |
| 3753 ULONGEST insn; |
| 3754 int insn_count; |
| 3755 int index; |
| 3756 |
| 3757 /* Assume all atomic sequences start with a ll/lld instruction. */ |
| 3758 insn = mips_fetch_instruction (gdbarch, ISA_MICROMIPS, loc, NULL); |
| 3759 if (micromips_op (insn) != 0x18) /* POOL32C: bits 011000 */ |
| 3760 return 0; |
| 3761 loc += MIPS_INSN16_SIZE; |
| 3762 insn <<= 16; |
| 3763 insn |= mips_fetch_instruction (gdbarch, ISA_MICROMIPS, loc, NULL); |
| 3764 if ((b12s4_op (insn) & 0xb) != 0x3) /* LL, LLD: bits 011000 0x11 */ |
| 3765 return 0; |
| 3766 loc += MIPS_INSN16_SIZE; |
| 3767 |
| 3768 /* Assume all atomic sequences end with an sc/scd instruction. Assume |
| 3769 that no atomic sequence is longer than "atomic_sequence_length" |
| 3770 instructions. */ |
| 3771 for (insn_count = 0; |
| 3772 !sc_found && insn_count < atomic_sequence_length; |
| 3773 ++insn_count) |
| 3774 { |
| 3775 int is_branch = 0; |
| 3776 |
| 3777 insn = mips_fetch_instruction (gdbarch, ISA_MICROMIPS, loc, NULL); |
| 3778 loc += MIPS_INSN16_SIZE; |
| 3779 |
| 3780 /* Assume that there is at most one conditional branch in the |
| 3781 atomic sequence. If a branch is found, put a breakpoint in |
| 3782 its destination address. */ |
| 3783 switch (mips_insn_size (ISA_MICROMIPS, insn)) |
| 3784 { |
| 3785 /* 48-bit instructions. */ |
| 3786 case 3 * MIPS_INSN16_SIZE: /* POOL48A: bits 011111 */ |
| 3787 loc += 2 * MIPS_INSN16_SIZE; |
| 3788 break; |
| 3789 |
| 3790 /* 32-bit instructions. */ |
| 3791 case 2 * MIPS_INSN16_SIZE: |
| 3792 switch (micromips_op (insn)) |
| 3793 { |
| 3794 case 0x10: /* POOL32I: bits 010000 */ |
| 3795 if ((b5s5_op (insn) & 0x18) != 0x0 |
| 3796 /* BLTZ, BLTZAL, BGEZ, BGEZAL: 010000 000xx */ |
| 3797 /* BLEZ, BNEZC, BGTZ, BEQZC: 010000 001xx */ |
| 3798 && (b5s5_op (insn) & 0x1d) != 0x11 |
| 3799 /* BLTZALS, BGEZALS: bits 010000 100x1 */ |
| 3800 && ((b5s5_op (insn) & 0x1e) != 0x14 |
| 3801 || (insn & 0x3) != 0x0) |
| 3802 /* BC2F, BC2T: bits 010000 1010x xxx00 */ |
| 3803 && (b5s5_op (insn) & 0x1e) != 0x1a |
| 3804 /* BPOSGE64, BPOSGE32: bits 010000 1101x */ |
| 3805 && ((b5s5_op (insn) & 0x1e) != 0x1c |
| 3806 || (insn & 0x3) != 0x0) |
| 3807 /* BC1F, BC1T: bits 010000 1110x xxx00 */ |
| 3808 && ((b5s5_op (insn) & 0x1c) != 0x1c |
| 3809 || (insn & 0x3) != 0x1)) |
| 3810 /* BC1ANY*: bits 010000 111xx xxx01 */ |
| 3811 break; |
| 3812 /* Fall through. */ |
| 3813 |
| 3814 case 0x25: /* BEQ: bits 100101 */ |
| 3815 case 0x2d: /* BNE: bits 101101 */ |
| 3816 insn <<= 16; |
| 3817 insn |= mips_fetch_instruction (gdbarch, |
| 3818 ISA_MICROMIPS, loc, NULL); |
| 3819 branch_bp = (loc + MIPS_INSN16_SIZE |
| 3820 + micromips_relative_offset16 (insn)); |
| 3821 is_branch = 1; |
| 3822 break; |
| 3823 |
| 3824 case 0x00: /* POOL32A: bits 000000 */ |
| 3825 insn <<= 16; |
| 3826 insn |= mips_fetch_instruction (gdbarch, |
| 3827 ISA_MICROMIPS, loc, NULL); |
| 3828 if (b0s6_op (insn) != 0x3c |
| 3829 /* POOL32Axf: bits 000000 ... 111100 */ |
| 3830 || (b6s10_ext (insn) & 0x2bf) != 0x3c) |
| 3831 /* JALR, JALR.HB: 000000 000x111100 111100 */ |
| 3832 /* JALRS, JALRS.HB: 000000 010x111100 111100 */ |
| 3833 break; |
| 3834 /* Fall through. */ |
| 3835 |
| 3836 case 0x1d: /* JALS: bits 011101 */ |
| 3837 case 0x35: /* J: bits 110101 */ |
| 3838 case 0x3d: /* JAL: bits 111101 */ |
| 3839 case 0x3c: /* JALX: bits 111100 */ |
| 3840 return 0; /* Fall back to the standard single-step code. */ |
| 3841 |
| 3842 case 0x18: /* POOL32C: bits 011000 */ |
| 3843 if ((b12s4_op (insn) & 0xb) == 0xb) |
| 3844 /* SC, SCD: bits 011000 1x11 */ |
| 3845 sc_found = 1; |
| 3846 break; |
| 3847 } |
| 3848 loc += MIPS_INSN16_SIZE; |
| 3849 break; |
| 3850 |
| 3851 /* 16-bit instructions. */ |
| 3852 case MIPS_INSN16_SIZE: |
| 3853 switch (micromips_op (insn)) |
| 3854 { |
| 3855 case 0x23: /* BEQZ16: bits 100011 */ |
| 3856 case 0x2b: /* BNEZ16: bits 101011 */ |
| 3857 branch_bp = loc + micromips_relative_offset7 (insn); |
| 3858 is_branch = 1; |
| 3859 break; |
| 3860 |
| 3861 case 0x11: /* POOL16C: bits 010001 */ |
| 3862 if ((b5s5_op (insn) & 0x1c) != 0xc |
| 3863 /* JR16, JRC, JALR16, JALRS16: 010001 011xx */ |
| 3864 && b5s5_op (insn) != 0x18) |
| 3865 /* JRADDIUSP: bits 010001 11000 */ |
| 3866 break; |
| 3867 return 0; /* Fall back to the standard single-step code. */ |
| 3868 |
| 3869 case 0x33: /* B16: bits 110011 */ |
| 3870 return 0; /* Fall back to the standard single-step code. */ |
| 3871 } |
| 3872 break; |
| 3873 } |
| 3874 if (is_branch) |
| 3875 { |
| 3876 if (last_breakpoint >= 1) |
| 3877 return 0; /* More than one branch found, fallback to the |
| 3878 standard single-step code. */ |
| 3879 breaks[1] = branch_bp; |
| 3880 last_breakpoint++; |
| 3881 } |
| 3882 } |
| 3883 if (!sc_found) |
| 3884 return 0; |
| 3885 |
| 3886 /* Insert a breakpoint right after the end of the atomic sequence. */ |
| 3887 breaks[0] = loc; |
| 3888 |
| 3889 /* Check for duplicated breakpoints. Check also for a breakpoint |
| 3890 placed (branch instruction's destination) in the atomic sequence */ |
| 3891 if (last_breakpoint && pc <= breaks[1] && breaks[1] <= breaks[0]) |
| 3892 last_breakpoint = 0; |
| 3893 |
| 3894 /* Effectively inserts the breakpoints. */ |
| 3895 for (index = 0; index <= last_breakpoint; index++) |
| 3896 insert_single_step_breakpoint (gdbarch, aspace, breaks[index]); |
| 3897 |
| 3898 return 1; |
| 3899 } |
| 3900 |
| 3901 static int |
| 3902 deal_with_atomic_sequence (struct gdbarch *gdbarch, |
| 3903 struct address_space *aspace, CORE_ADDR pc) |
| 3904 { |
| 3905 if (mips_pc_is_mips (pc)) |
| 3906 return mips_deal_with_atomic_sequence (gdbarch, aspace, pc); |
| 3907 else if (mips_pc_is_micromips (gdbarch, pc)) |
| 3908 return micromips_deal_with_atomic_sequence (gdbarch, aspace, pc); |
| 3909 else |
| 3910 return 0; |
| 3911 } |
| 3912 |
2648 /* mips_software_single_step() is called just before we want to resume | 3913 /* mips_software_single_step() is called just before we want to resume |
2649 the inferior, if we want to single-step it but there is no hardware | 3914 the inferior, if we want to single-step it but there is no hardware |
2650 or kernel single-step support (MIPS on GNU/Linux for example). We find | 3915 or kernel single-step support (MIPS on GNU/Linux for example). We find |
2651 the target of the coming instruction and breakpoint it. */ | 3916 the target of the coming instruction and breakpoint it. */ |
2652 | 3917 |
2653 int | 3918 int |
2654 mips_software_single_step (struct frame_info *frame) | 3919 mips_software_single_step (struct frame_info *frame) |
2655 { | 3920 { |
2656 struct gdbarch *gdbarch = get_frame_arch (frame); | 3921 struct gdbarch *gdbarch = get_frame_arch (frame); |
2657 struct address_space *aspace = get_frame_address_space (frame); | 3922 struct address_space *aspace = get_frame_address_space (frame); |
2658 CORE_ADDR pc, next_pc; | 3923 CORE_ADDR pc, next_pc; |
2659 | 3924 |
2660 pc = get_frame_pc (frame); | 3925 pc = get_frame_pc (frame); |
2661 if (deal_with_atomic_sequence (gdbarch, aspace, pc)) | 3926 if (deal_with_atomic_sequence (gdbarch, aspace, pc)) |
2662 return 1; | 3927 return 1; |
2663 | 3928 |
2664 next_pc = mips_next_pc (frame, pc); | 3929 next_pc = mips_next_pc (frame, pc); |
2665 | 3930 |
2666 insert_single_step_breakpoint (gdbarch, aspace, next_pc); | 3931 insert_single_step_breakpoint (gdbarch, aspace, next_pc); |
2667 return 1; | 3932 return 1; |
2668 } | 3933 } |
2669 | 3934 |
2670 /* Test whether the PC points to the return instruction at the | 3935 /* Test whether the PC points to the return instruction at the |
2671 end of a function. */ | 3936 end of a function. */ |
2672 | 3937 |
2673 static int | 3938 static int |
2674 mips_about_to_return (struct gdbarch *gdbarch, CORE_ADDR pc) | 3939 mips_about_to_return (struct gdbarch *gdbarch, CORE_ADDR pc) |
2675 { | 3940 { |
2676 if (mips_pc_is_mips16 (pc)) | 3941 ULONGEST insn; |
2677 /* This mips16 case isn't necessarily reliable. Sometimes the compiler | 3942 ULONGEST hint; |
2678 generates a "jr $ra"; other times it generates code to load | 3943 |
2679 the return address from the stack to an accessible register (such | 3944 /* This used to check for MIPS16, but this piece of code is never |
2680 as $a3), then a "jr" using that register. This second case | 3945 called for MIPS16 functions. And likewise microMIPS ones. */ |
2681 is almost impossible to distinguish from an indirect jump | 3946 gdb_assert (mips_pc_is_mips (pc)); |
2682 used for switch statements, so we don't even try. */ | 3947 |
2683 return mips_fetch_instruction (gdbarch, pc) == 0xe820;» /* jr $ra */ | 3948 insn = mips_fetch_instruction (gdbarch, ISA_MIPS, pc, NULL); |
2684 else | 3949 hint = 0x7c0; |
2685 return mips_fetch_instruction (gdbarch, pc) == 0x3e00008;» /* jr $ra */ | 3950 return (insn & ~hint) == 0x3e00008;» » » /* jr(.hb) $ra */ |
2686 } | 3951 } |
2687 | 3952 |
2688 | 3953 |
2689 /* This fencepost looks highly suspicious to me. Removing it also | 3954 /* This fencepost looks highly suspicious to me. Removing it also |
2690 seems suspicious as it could affect remote debugging across serial | 3955 seems suspicious as it could affect remote debugging across serial |
2691 lines. */ | 3956 lines. */ |
2692 | 3957 |
2693 static CORE_ADDR | 3958 static CORE_ADDR |
2694 heuristic_proc_start (struct gdbarch *gdbarch, CORE_ADDR pc) | 3959 heuristic_proc_start (struct gdbarch *gdbarch, CORE_ADDR pc) |
2695 { | 3960 { |
2696 CORE_ADDR start_pc; | 3961 CORE_ADDR start_pc; |
2697 CORE_ADDR fence; | 3962 CORE_ADDR fence; |
2698 int instlen; | 3963 int instlen; |
2699 int seen_adjsp = 0; | 3964 int seen_adjsp = 0; |
2700 struct inferior *inf; | 3965 struct inferior *inf; |
2701 | 3966 |
2702 pc = gdbarch_addr_bits_remove (gdbarch, pc); | 3967 pc = gdbarch_addr_bits_remove (gdbarch, pc); |
2703 start_pc = pc; | 3968 start_pc = pc; |
2704 fence = start_pc - heuristic_fence_post; | 3969 fence = start_pc - heuristic_fence_post; |
2705 if (start_pc == 0) | 3970 if (start_pc == 0) |
2706 return 0; | 3971 return 0; |
2707 | 3972 |
2708 if (heuristic_fence_post == UINT_MAX || fence < VM_MIN_ADDRESS) | 3973 if (heuristic_fence_post == UINT_MAX || fence < VM_MIN_ADDRESS) |
2709 fence = VM_MIN_ADDRESS; | 3974 fence = VM_MIN_ADDRESS; |
2710 | 3975 |
2711 instlen = mips_pc_is_mips16 (pc) ? MIPS_INSN16_SIZE : MIPS_INSN32_SIZE; | 3976 instlen = mips_pc_is_mips (pc) ? MIPS_INSN32_SIZE : MIPS_INSN16_SIZE; |
2712 | 3977 |
2713 inf = current_inferior (); | 3978 inf = current_inferior (); |
2714 | 3979 |
2715 /* Search back for previous return. */ | 3980 /* Search back for previous return. */ |
2716 for (start_pc -= instlen;; start_pc -= instlen) | 3981 for (start_pc -= instlen;; start_pc -= instlen) |
2717 if (start_pc < fence) | 3982 if (start_pc < fence) |
2718 { | 3983 { |
2719 /* It's not clear to me why we reach this point when | 3984 /* It's not clear to me why we reach this point when |
2720 stop_soon, but with this test, at least we | 3985 stop_soon, but with this test, at least we |
2721 don't print out warnings for every child forked (eg, on | 3986 don't print out warnings for every child forked (eg, on |
(...skipping 24 matching lines...) Expand all Loading... |
2746 from %s for code which looks like the beginning of a\n\ | 4011 from %s for code which looks like the beginning of a\n\ |
2747 function, you can increase the range of the search using the `set\n\ | 4012 function, you can increase the range of the search using the `set\n\ |
2748 heuristic-fence-post' command.\n", | 4013 heuristic-fence-post' command.\n", |
2749 paddress (gdbarch, pc), paddress (gdbarch, pc)); | 4014 paddress (gdbarch, pc), paddress (gdbarch, pc)); |
2750 blurb_printed = 1; | 4015 blurb_printed = 1; |
2751 } | 4016 } |
2752 } | 4017 } |
2753 | 4018 |
2754 return 0; | 4019 return 0; |
2755 } | 4020 } |
2756 else if (mips_pc_is_mips16 (start_pc)) | 4021 else if (mips_pc_is_mips16 (gdbarch, start_pc)) |
2757 { | 4022 { |
2758 unsigned short inst; | 4023 unsigned short inst; |
2759 | 4024 |
2760 /* On MIPS16, any one of the following is likely to be the | 4025 /* On MIPS16, any one of the following is likely to be the |
2761 start of a function: | 4026 start of a function: |
2762 extend save | 4027 extend save |
2763 save | 4028 save |
2764 entry | 4029 entry |
2765 addiu sp,-n | 4030 addiu sp,-n |
2766 daddiu sp,-n | 4031 daddiu sp,-n |
2767 extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n'. */ | 4032 extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n'. */ |
2768 » inst = mips_fetch_instruction (gdbarch, start_pc); | 4033 » inst = mips_fetch_instruction (gdbarch, ISA_MIPS16, start_pc, NULL); |
2769 if ((inst & 0xff80) == 0x6480) /* save */ | 4034 if ((inst & 0xff80) == 0x6480) /* save */ |
2770 { | 4035 { |
2771 if (start_pc - instlen >= fence) | 4036 if (start_pc - instlen >= fence) |
2772 { | 4037 { |
2773 » » inst = mips_fetch_instruction (gdbarch, start_pc - instlen); | 4038 » » inst = mips_fetch_instruction (gdbarch, ISA_MIPS16, |
| 4039 » » » » » start_pc - instlen, NULL); |
2774 if ((inst & 0xf800) == 0xf000) /* extend */ | 4040 if ((inst & 0xf800) == 0xf000) /* extend */ |
2775 start_pc -= instlen; | 4041 start_pc -= instlen; |
2776 } | 4042 } |
2777 break; | 4043 break; |
2778 } | 4044 } |
2779 else if (((inst & 0xf81f) == 0xe809 | 4045 else if (((inst & 0xf81f) == 0xe809 |
2780 && (inst & 0x700) != 0x700) /* entry */ | 4046 && (inst & 0x700) != 0x700) /* entry */ |
2781 || (inst & 0xff80) == 0x6380 /* addiu sp,-n */ | 4047 || (inst & 0xff80) == 0x6380 /* addiu sp,-n */ |
2782 || (inst & 0xff80) == 0xfb80 /* daddiu sp,-n */ | 4048 || (inst & 0xff80) == 0xfb80 /* daddiu sp,-n */ |
2783 || ((inst & 0xf810) == 0xf010 && seen_adjsp)) /* extend -n */ | 4049 || ((inst & 0xf810) == 0xf010 && seen_adjsp)) /* extend -n */ |
2784 break; | 4050 break; |
2785 else if ((inst & 0xff00) == 0x6300 /* addiu sp */ | 4051 else if ((inst & 0xff00) == 0x6300 /* addiu sp */ |
2786 || (inst & 0xff00) == 0xfb00) /* daddiu sp */ | 4052 || (inst & 0xff00) == 0xfb00) /* daddiu sp */ |
2787 seen_adjsp = 1; | 4053 seen_adjsp = 1; |
2788 else | 4054 else |
2789 seen_adjsp = 0; | 4055 seen_adjsp = 0; |
2790 } | 4056 } |
| 4057 else if (mips_pc_is_micromips (gdbarch, start_pc)) |
| 4058 { |
| 4059 ULONGEST insn; |
| 4060 int stop = 0; |
| 4061 long offset; |
| 4062 int dreg; |
| 4063 int sreg; |
| 4064 |
| 4065 /* On microMIPS, any one of the following is likely to be the |
| 4066 start of a function: |
| 4067 ADDIUSP -imm |
| 4068 (D)ADDIU $sp, -imm |
| 4069 LUI $gp, imm */ |
| 4070 insn = mips_fetch_instruction (gdbarch, ISA_MICROMIPS, pc, NULL); |
| 4071 switch (micromips_op (insn)) |
| 4072 { |
| 4073 case 0xc: /* ADDIU: bits 001100 */ |
| 4074 case 0x17: /* DADDIU: bits 010111 */ |
| 4075 sreg = b0s5_reg (insn); |
| 4076 dreg = b5s5_reg (insn); |
| 4077 insn <<= 16; |
| 4078 insn |= mips_fetch_instruction (gdbarch, ISA_MICROMIPS, |
| 4079 pc + MIPS_INSN16_SIZE, NULL); |
| 4080 offset = (b0s16_imm (insn) ^ 0x8000) - 0x8000; |
| 4081 if (sreg == MIPS_SP_REGNUM && dreg == MIPS_SP_REGNUM |
| 4082 /* (D)ADDIU $sp, imm */ |
| 4083 && offset < 0) |
| 4084 stop = 1; |
| 4085 break; |
| 4086 |
| 4087 case 0x10: /* POOL32I: bits 010000 */ |
| 4088 if (b5s5_op (insn) == 0xd |
| 4089 /* LUI: bits 010000 001101 */ |
| 4090 && b0s5_reg (insn >> 16) == 28) |
| 4091 /* LUI $gp, imm */ |
| 4092 stop = 1; |
| 4093 break; |
| 4094 |
| 4095 case 0x13: /* POOL16D: bits 010011 */ |
| 4096 if ((insn & 0x1) == 0x1) |
| 4097 /* ADDIUSP: bits 010011 1 */ |
| 4098 { |
| 4099 offset = micromips_decode_imm9 (b1s9_imm (insn)); |
| 4100 if (offset < 0) |
| 4101 /* ADDIUSP -imm */ |
| 4102 stop = 1; |
| 4103 } |
| 4104 else |
| 4105 /* ADDIUS5: bits 010011 0 */ |
| 4106 { |
| 4107 dreg = b5s5_reg (insn); |
| 4108 offset = (b1s4_imm (insn) ^ 8) - 8; |
| 4109 if (dreg == MIPS_SP_REGNUM && offset < 0) |
| 4110 /* ADDIUS5 $sp, -imm */ |
| 4111 stop = 1; |
| 4112 } |
| 4113 break; |
| 4114 } |
| 4115 if (stop) |
| 4116 break; |
| 4117 } |
2791 else if (mips_about_to_return (gdbarch, start_pc)) | 4118 else if (mips_about_to_return (gdbarch, start_pc)) |
2792 { | 4119 { |
2793 /* Skip return and its delay slot. */ | 4120 /* Skip return and its delay slot. */ |
2794 start_pc += 2 * MIPS_INSN32_SIZE; | 4121 start_pc += 2 * MIPS_INSN32_SIZE; |
2795 break; | 4122 break; |
2796 } | 4123 } |
2797 | 4124 |
2798 return start_pc; | 4125 return start_pc; |
2799 } | 4126 } |
2800 | 4127 |
(...skipping 53 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... |
2854 } | 4181 } |
2855 | 4182 |
2856 /* Adjust the address downward (direction of stack growth) so that it | 4183 /* Adjust the address downward (direction of stack growth) so that it |
2857 is correctly aligned for a new stack frame. */ | 4184 is correctly aligned for a new stack frame. */ |
2858 static CORE_ADDR | 4185 static CORE_ADDR |
2859 mips_frame_align (struct gdbarch *gdbarch, CORE_ADDR addr) | 4186 mips_frame_align (struct gdbarch *gdbarch, CORE_ADDR addr) |
2860 { | 4187 { |
2861 return align_down (addr, 16); | 4188 return align_down (addr, 16); |
2862 } | 4189 } |
2863 | 4190 |
| 4191 /* Implement the "push_dummy_code" gdbarch method. */ |
| 4192 |
| 4193 static CORE_ADDR |
| 4194 mips_push_dummy_code (struct gdbarch *gdbarch, CORE_ADDR sp, |
| 4195 CORE_ADDR funaddr, struct value **args, |
| 4196 int nargs, struct type *value_type, |
| 4197 CORE_ADDR *real_pc, CORE_ADDR *bp_addr, |
| 4198 struct regcache *regcache) |
| 4199 { |
| 4200 static gdb_byte nop_insn[] = { 0, 0, 0, 0 }; |
| 4201 CORE_ADDR nop_addr; |
| 4202 CORE_ADDR bp_slot; |
| 4203 |
| 4204 /* Reserve enough room on the stack for our breakpoint instruction. */ |
| 4205 bp_slot = sp - sizeof (nop_insn); |
| 4206 |
| 4207 /* Return to microMIPS mode if calling microMIPS code to avoid |
| 4208 triggering an address error exception on processors that only |
| 4209 support microMIPS execution. */ |
| 4210 *bp_addr = (mips_pc_is_micromips (gdbarch, funaddr) |
| 4211 ? make_compact_addr (bp_slot) : bp_slot); |
| 4212 |
| 4213 /* The breakpoint layer automatically adjusts the address of |
| 4214 breakpoints inserted in a branch delay slot. With enough |
| 4215 bad luck, the 4 bytes located just before our breakpoint |
| 4216 instruction could look like a branch instruction, and thus |
| 4217 trigger the adjustement, and break the function call entirely. |
| 4218 So, we reserve those 4 bytes and write a nop instruction |
| 4219 to prevent that from happening. */ |
| 4220 nop_addr = bp_slot - sizeof (nop_insn); |
| 4221 write_memory (nop_addr, nop_insn, sizeof (nop_insn)); |
| 4222 sp = mips_frame_align (gdbarch, nop_addr); |
| 4223 |
| 4224 /* Inferior resumes at the function entry point. */ |
| 4225 *real_pc = funaddr; |
| 4226 |
| 4227 return sp; |
| 4228 } |
| 4229 |
2864 static CORE_ADDR | 4230 static CORE_ADDR |
2865 mips_eabi_push_dummy_call (struct gdbarch *gdbarch, struct value *function, | 4231 mips_eabi_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
2866 struct regcache *regcache, CORE_ADDR bp_addr, | 4232 struct regcache *regcache, CORE_ADDR bp_addr, |
2867 int nargs, struct value **args, CORE_ADDR sp, | 4233 int nargs, struct value **args, CORE_ADDR sp, |
2868 int struct_return, CORE_ADDR struct_addr) | 4234 int struct_return, CORE_ADDR struct_addr) |
2869 { | 4235 { |
2870 int argreg; | 4236 int argreg; |
2871 int float_argreg; | 4237 int float_argreg; |
2872 int argnum; | 4238 int argnum; |
2873 int len = 0; | 4239 int len = 0; |
2874 int stack_offset = 0; | 4240 int stack_offset = 0; |
2875 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
2876 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | 4241 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
2877 CORE_ADDR func_addr = find_function_addr (function, NULL); | 4242 CORE_ADDR func_addr = find_function_addr (function, NULL); |
2878 int regsize = mips_abi_regsize (gdbarch); | 4243 int regsize = mips_abi_regsize (gdbarch); |
2879 | 4244 |
2880 /* For shared libraries, "t9" needs to point at the function | 4245 /* For shared libraries, "t9" needs to point at the function |
2881 address. */ | 4246 address. */ |
2882 regcache_cooked_write_signed (regcache, MIPS_T9_REGNUM, func_addr); | 4247 regcache_cooked_write_signed (regcache, MIPS_T9_REGNUM, func_addr); |
2883 | 4248 |
2884 /* Set the return address register to point to the entry point of | 4249 /* Set the return address register to point to the entry point of |
2885 the program, where a breakpoint lies in wait. */ | 4250 the program, where a breakpoint lies in wait. */ |
(...skipping 52 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... |
2938 "mips_eabi_push_dummy_call: %d len=%d type=%d", | 4303 "mips_eabi_push_dummy_call: %d len=%d type=%d", |
2939 argnum + 1, len, (int) typecode); | 4304 argnum + 1, len, (int) typecode); |
2940 | 4305 |
2941 /* Function pointer arguments to mips16 code need to be made into | 4306 /* Function pointer arguments to mips16 code need to be made into |
2942 mips16 pointers. */ | 4307 mips16 pointers. */ |
2943 if (typecode == TYPE_CODE_PTR | 4308 if (typecode == TYPE_CODE_PTR |
2944 && TYPE_CODE (TYPE_TARGET_TYPE (arg_type)) == TYPE_CODE_FUNC) | 4309 && TYPE_CODE (TYPE_TARGET_TYPE (arg_type)) == TYPE_CODE_FUNC) |
2945 { | 4310 { |
2946 CORE_ADDR addr = extract_signed_integer (value_contents (arg), | 4311 CORE_ADDR addr = extract_signed_integer (value_contents (arg), |
2947 len, byte_order); | 4312 len, byte_order); |
2948 » if (mips_pc_is_mips16 (addr)) | 4313 » if (mips_pc_is_mips (addr)) |
| 4314 » val = value_contents (arg); |
| 4315 » else |
2949 { | 4316 { |
2950 store_signed_integer (valbuf, len, byte_order, | 4317 store_signed_integer (valbuf, len, byte_order, |
2951 » » » » make_mips16_addr (addr)); | 4318 » » » » make_compact_addr (addr)); |
2952 val = valbuf; | 4319 val = valbuf; |
2953 } | 4320 } |
2954 else | |
2955 val = value_contents (arg); | |
2956 } | 4321 } |
2957 /* The EABI passes structures that do not fit in a register by | 4322 /* The EABI passes structures that do not fit in a register by |
2958 reference. */ | 4323 reference. */ |
2959 else if (len > regsize | 4324 else if (len > regsize |
2960 && (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION)) | 4325 && (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION)) |
2961 { | 4326 { |
2962 store_unsigned_integer (valbuf, regsize, byte_order, | 4327 store_unsigned_integer (valbuf, regsize, byte_order, |
2963 value_address (arg)); | 4328 value_address (arg)); |
2964 typecode = TYPE_CODE_PTR; | 4329 typecode = TYPE_CODE_PTR; |
2965 len = regsize; | 4330 len = regsize; |
(...skipping 179 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... |
3145 | 4510 |
3146 regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp); | 4511 regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp); |
3147 | 4512 |
3148 /* Return adjusted stack pointer. */ | 4513 /* Return adjusted stack pointer. */ |
3149 return sp; | 4514 return sp; |
3150 } | 4515 } |
3151 | 4516 |
3152 /* Determine the return value convention being used. */ | 4517 /* Determine the return value convention being used. */ |
3153 | 4518 |
3154 static enum return_value_convention | 4519 static enum return_value_convention |
3155 mips_eabi_return_value (struct gdbarch *gdbarch, struct type *func_type, | 4520 mips_eabi_return_value (struct gdbarch *gdbarch, struct value *function, |
3156 struct type *type, struct regcache *regcache, | 4521 struct type *type, struct regcache *regcache, |
3157 gdb_byte *readbuf, const gdb_byte *writebuf) | 4522 gdb_byte *readbuf, const gdb_byte *writebuf) |
3158 { | 4523 { |
3159 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | 4524 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
3160 int fp_return_type = 0; | 4525 int fp_return_type = 0; |
3161 int offset, regnum, xfer; | 4526 int offset, regnum, xfer; |
3162 | 4527 |
3163 if (TYPE_LENGTH (type) > 2 * mips_abi_regsize (gdbarch)) | 4528 if (TYPE_LENGTH (type) > 2 * mips_abi_regsize (gdbarch)) |
3164 return RETURN_VALUE_STRUCT_CONVENTION; | 4529 return RETURN_VALUE_STRUCT_CONVENTION; |
3165 | 4530 |
(...skipping 107 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... |
3273 mips_n32n64_push_dummy_call (struct gdbarch *gdbarch, struct value *function, | 4638 mips_n32n64_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
3274 struct regcache *regcache, CORE_ADDR bp_addr, | 4639 struct regcache *regcache, CORE_ADDR bp_addr, |
3275 int nargs, struct value **args, CORE_ADDR sp, | 4640 int nargs, struct value **args, CORE_ADDR sp, |
3276 int struct_return, CORE_ADDR struct_addr) | 4641 int struct_return, CORE_ADDR struct_addr) |
3277 { | 4642 { |
3278 int argreg; | 4643 int argreg; |
3279 int float_argreg; | 4644 int float_argreg; |
3280 int argnum; | 4645 int argnum; |
3281 int len = 0; | 4646 int len = 0; |
3282 int stack_offset = 0; | 4647 int stack_offset = 0; |
3283 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
3284 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | 4648 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
3285 CORE_ADDR func_addr = find_function_addr (function, NULL); | 4649 CORE_ADDR func_addr = find_function_addr (function, NULL); |
3286 | 4650 |
3287 /* For shared libraries, "t9" needs to point at the function | 4651 /* For shared libraries, "t9" needs to point at the function |
3288 address. */ | 4652 address. */ |
3289 regcache_cooked_write_signed (regcache, MIPS_T9_REGNUM, func_addr); | 4653 regcache_cooked_write_signed (regcache, MIPS_T9_REGNUM, func_addr); |
3290 | 4654 |
3291 /* Set the return address register to point to the entry point of | 4655 /* Set the return address register to point to the entry point of |
3292 the program, where a breakpoint lies in wait. */ | 4656 the program, where a breakpoint lies in wait. */ |
3293 regcache_cooked_write_signed (regcache, MIPS_RA_REGNUM, bp_addr); | 4657 regcache_cooked_write_signed (regcache, MIPS_RA_REGNUM, bp_addr); |
(...skipping 241 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... |
3535 fprintf_unfiltered (gdb_stdlog, "\n"); | 4899 fprintf_unfiltered (gdb_stdlog, "\n"); |
3536 } | 4900 } |
3537 | 4901 |
3538 regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp); | 4902 regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp); |
3539 | 4903 |
3540 /* Return adjusted stack pointer. */ | 4904 /* Return adjusted stack pointer. */ |
3541 return sp; | 4905 return sp; |
3542 } | 4906 } |
3543 | 4907 |
3544 static enum return_value_convention | 4908 static enum return_value_convention |
3545 mips_n32n64_return_value (struct gdbarch *gdbarch, struct type *func_type, | 4909 mips_n32n64_return_value (struct gdbarch *gdbarch, struct value *function, |
3546 struct type *type, struct regcache *regcache, | 4910 struct type *type, struct regcache *regcache, |
3547 gdb_byte *readbuf, const gdb_byte *writebuf) | 4911 gdb_byte *readbuf, const gdb_byte *writebuf) |
3548 { | 4912 { |
3549 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | 4913 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
3550 | 4914 |
3551 /* From MIPSpro N32 ABI Handbook, Document Number: 007-2816-004 | 4915 /* From MIPSpro N32 ABI Handbook, Document Number: 007-2816-004 |
3552 | 4916 |
3553 Function results are returned in $2 (and $3 if needed), or $f0 (and $f2 | 4917 Function results are returned in $2 (and $3 if needed), or $f0 (and $f2 |
3554 if needed), as appropriate for the type. Composite results (struct, | 4918 if needed), as appropriate for the type. Composite results (struct, |
3555 union, or array) are returned in $2/$f0 and $3/$f2 according to the | 4919 union, or array) are returned in $2/$f0 and $3/$f2 according to the |
(...skipping 19 matching lines...) Expand all Loading... |
3575 else if (TYPE_CODE (type) == TYPE_CODE_FLT | 4939 else if (TYPE_CODE (type) == TYPE_CODE_FLT |
3576 && TYPE_LENGTH (type) == 16 | 4940 && TYPE_LENGTH (type) == 16 |
3577 && tdep->mips_fpu_type != MIPS_FPU_NONE) | 4941 && tdep->mips_fpu_type != MIPS_FPU_NONE) |
3578 { | 4942 { |
3579 /* A 128-bit floating-point value fills both $f0 and $f2. The | 4943 /* A 128-bit floating-point value fills both $f0 and $f2. The |
3580 two registers are used in the same as memory order, so the | 4944 two registers are used in the same as memory order, so the |
3581 eight bytes with the lower memory address are in $f0. */ | 4945 eight bytes with the lower memory address are in $f0. */ |
3582 if (mips_debug) | 4946 if (mips_debug) |
3583 fprintf_unfiltered (gdb_stderr, "Return float in $f0 and $f2\n"); | 4947 fprintf_unfiltered (gdb_stderr, "Return float in $f0 and $f2\n"); |
3584 mips_xfer_register (gdbarch, regcache, | 4948 mips_xfer_register (gdbarch, regcache, |
3585 » » » gdbarch_num_regs (gdbarch) | 4949 » » » (gdbarch_num_regs (gdbarch) |
3586 » » » + mips_regnum (gdbarch)->fp0, | 4950 » » » + mips_regnum (gdbarch)->fp0), |
3587 8, gdbarch_byte_order (gdbarch), | 4951 8, gdbarch_byte_order (gdbarch), |
3588 readbuf, writebuf, 0); | 4952 readbuf, writebuf, 0); |
3589 mips_xfer_register (gdbarch, regcache, | 4953 mips_xfer_register (gdbarch, regcache, |
3590 » » » gdbarch_num_regs (gdbarch) | 4954 » » » (gdbarch_num_regs (gdbarch) |
3591 » » » + mips_regnum (gdbarch)->fp0 + 2, | 4955 » » » + mips_regnum (gdbarch)->fp0 + 2), |
3592 8, gdbarch_byte_order (gdbarch), | 4956 8, gdbarch_byte_order (gdbarch), |
3593 readbuf ? readbuf + 8 : readbuf, | 4957 readbuf ? readbuf + 8 : readbuf, |
3594 writebuf ? writebuf + 8 : writebuf, 0); | 4958 writebuf ? writebuf + 8 : writebuf, 0); |
3595 return RETURN_VALUE_REGISTER_CONVENTION; | 4959 return RETURN_VALUE_REGISTER_CONVENTION; |
3596 } | 4960 } |
3597 else if (TYPE_CODE (type) == TYPE_CODE_FLT | 4961 else if (TYPE_CODE (type) == TYPE_CODE_FLT |
3598 && tdep->mips_fpu_type != MIPS_FPU_NONE) | 4962 && tdep->mips_fpu_type != MIPS_FPU_NONE) |
3599 { | 4963 { |
3600 /* A single or double floating-point value that fits in FP0. */ | 4964 /* A single or double floating-point value that fits in FP0. */ |
3601 if (mips_debug) | 4965 if (mips_debug) |
3602 fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n"); | 4966 fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n"); |
3603 mips_xfer_register (gdbarch, regcache, | 4967 mips_xfer_register (gdbarch, regcache, |
3604 » » » gdbarch_num_regs (gdbarch) | 4968 » » » (gdbarch_num_regs (gdbarch) |
3605 » » » + mips_regnum (gdbarch)->fp0, | 4969 » » » + mips_regnum (gdbarch)->fp0), |
3606 TYPE_LENGTH (type), | 4970 TYPE_LENGTH (type), |
3607 gdbarch_byte_order (gdbarch), | 4971 gdbarch_byte_order (gdbarch), |
3608 readbuf, writebuf, 0); | 4972 readbuf, writebuf, 0); |
3609 return RETURN_VALUE_REGISTER_CONVENTION; | 4973 return RETURN_VALUE_REGISTER_CONVENTION; |
3610 } | 4974 } |
3611 else if (TYPE_CODE (type) == TYPE_CODE_STRUCT | 4975 else if (TYPE_CODE (type) == TYPE_CODE_STRUCT |
3612 && TYPE_NFIELDS (type) <= 2 | 4976 && TYPE_NFIELDS (type) <= 2 |
3613 && TYPE_NFIELDS (type) >= 1 | 4977 && TYPE_NFIELDS (type) >= 1 |
3614 && ((TYPE_NFIELDS (type) == 1 | 4978 && ((TYPE_NFIELDS (type) == 1 |
3615 && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type, 0))) | 4979 && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type, 0))) |
(...skipping 87 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... |
3703 offset, xfer, regnum); | 5067 offset, xfer, regnum); |
3704 mips_xfer_register (gdbarch, regcache, | 5068 mips_xfer_register (gdbarch, regcache, |
3705 gdbarch_num_regs (gdbarch) + regnum, | 5069 gdbarch_num_regs (gdbarch) + regnum, |
3706 xfer, gdbarch_byte_order (gdbarch), | 5070 xfer, gdbarch_byte_order (gdbarch), |
3707 readbuf, writebuf, offset); | 5071 readbuf, writebuf, offset); |
3708 } | 5072 } |
3709 return RETURN_VALUE_REGISTER_CONVENTION; | 5073 return RETURN_VALUE_REGISTER_CONVENTION; |
3710 } | 5074 } |
3711 } | 5075 } |
3712 | 5076 |
| 5077 /* Which registers to use for passing floating-point values between |
| 5078 function calls, one of floating-point, general and both kinds of |
| 5079 registers. O32 and O64 use different register kinds for standard |
| 5080 MIPS and MIPS16 code; to make the handling of cases where we may |
| 5081 not know what kind of code is being used (e.g. no debug information) |
| 5082 easier we sometimes use both kinds. */ |
| 5083 |
| 5084 enum mips_fval_reg |
| 5085 { |
| 5086 mips_fval_fpr, |
| 5087 mips_fval_gpr, |
| 5088 mips_fval_both |
| 5089 }; |
| 5090 |
3713 /* O32 ABI stuff. */ | 5091 /* O32 ABI stuff. */ |
3714 | 5092 |
3715 static CORE_ADDR | 5093 static CORE_ADDR |
3716 mips_o32_push_dummy_call (struct gdbarch *gdbarch, struct value *function, | 5094 mips_o32_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
3717 struct regcache *regcache, CORE_ADDR bp_addr, | 5095 struct regcache *regcache, CORE_ADDR bp_addr, |
3718 int nargs, struct value **args, CORE_ADDR sp, | 5096 int nargs, struct value **args, CORE_ADDR sp, |
3719 int struct_return, CORE_ADDR struct_addr) | 5097 int struct_return, CORE_ADDR struct_addr) |
3720 { | 5098 { |
3721 int argreg; | 5099 int argreg; |
3722 int float_argreg; | 5100 int float_argreg; |
3723 int argnum; | 5101 int argnum; |
3724 int len = 0; | 5102 int len = 0; |
3725 int stack_offset = 0; | 5103 int stack_offset = 0; |
3726 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
3727 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | 5104 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
3728 CORE_ADDR func_addr = find_function_addr (function, NULL); | 5105 CORE_ADDR func_addr = find_function_addr (function, NULL); |
3729 | 5106 |
3730 /* For shared libraries, "t9" needs to point at the function | 5107 /* For shared libraries, "t9" needs to point at the function |
3731 address. */ | 5108 address. */ |
3732 regcache_cooked_write_signed (regcache, MIPS_T9_REGNUM, func_addr); | 5109 regcache_cooked_write_signed (regcache, MIPS_T9_REGNUM, func_addr); |
3733 | 5110 |
3734 /* Set the return address register to point to the entry point of | 5111 /* Set the return address register to point to the entry point of |
3735 the program, where a breakpoint lies in wait. */ | 5112 the program, where a breakpoint lies in wait. */ |
3736 regcache_cooked_write_signed (regcache, MIPS_RA_REGNUM, bp_addr); | 5113 regcache_cooked_write_signed (regcache, MIPS_RA_REGNUM, bp_addr); |
(...skipping 56 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... |
3793 if (mips_debug) | 5170 if (mips_debug) |
3794 fprintf_unfiltered (gdb_stdlog, | 5171 fprintf_unfiltered (gdb_stdlog, |
3795 "mips_o32_push_dummy_call: %d len=%d type=%d", | 5172 "mips_o32_push_dummy_call: %d len=%d type=%d", |
3796 argnum + 1, len, (int) typecode); | 5173 argnum + 1, len, (int) typecode); |
3797 | 5174 |
3798 val = value_contents (arg); | 5175 val = value_contents (arg); |
3799 | 5176 |
3800 /* 32-bit ABIs always start floating point arguments in an | 5177 /* 32-bit ABIs always start floating point arguments in an |
3801 even-numbered floating point register. Round the FP register | 5178 even-numbered floating point register. Round the FP register |
3802 up before the check to see if there are any FP registers | 5179 up before the check to see if there are any FP registers |
3803 left. O32/O64 targets also pass the FP in the integer | 5180 left. O32 targets also pass the FP in the integer registers |
3804 registers so also round up normal registers. */ | 5181 so also round up normal registers. */ |
3805 if (fp_register_arg_p (gdbarch, typecode, arg_type)) | 5182 if (fp_register_arg_p (gdbarch, typecode, arg_type)) |
3806 { | 5183 { |
3807 if ((float_argreg & 1)) | 5184 if ((float_argreg & 1)) |
3808 float_argreg++; | 5185 float_argreg++; |
3809 } | 5186 } |
3810 | 5187 |
3811 /* Floating point arguments passed in registers have to be | 5188 /* Floating point arguments passed in registers have to be |
3812 treated specially. On 32-bit architectures, doubles | 5189 treated specially. On 32-bit architectures, doubles are |
3813 are passed in register pairs; the even register gets | 5190 passed in register pairs; the even FP register gets the |
3814 the low word, and the odd register gets the high word. | 5191 low word, and the odd FP register gets the high word. |
3815 On O32/O64, the first two floating point arguments are | 5192 On O32, the first two floating point arguments are also |
3816 also copied to general registers, because MIPS16 functions | 5193 copied to general registers, following their memory order, |
3817 don't use float registers for arguments. This duplication of | 5194 because MIPS16 functions don't use float registers for |
3818 arguments in general registers can't hurt non-MIPS16 functions | 5195 arguments. This duplication of arguments in general |
3819 because those registers are normally skipped. */ | 5196 registers can't hurt non-MIPS16 functions, because those |
| 5197 registers are normally skipped. */ |
3820 | 5198 |
3821 if (fp_register_arg_p (gdbarch, typecode, arg_type) | 5199 if (fp_register_arg_p (gdbarch, typecode, arg_type) |
3822 && float_argreg <= MIPS_LAST_FP_ARG_REGNUM (gdbarch)) | 5200 && float_argreg <= MIPS_LAST_FP_ARG_REGNUM (gdbarch)) |
3823 { | 5201 { |
3824 if (register_size (gdbarch, float_argreg) < 8 && len == 8) | 5202 if (register_size (gdbarch, float_argreg) < 8 && len == 8) |
3825 { | 5203 { |
3826 » int low_offset = gdbarch_byte_order (gdbarch) | 5204 » int freg_offset = gdbarch_byte_order (gdbarch) |
3827 » » » == BFD_ENDIAN_BIG ? 4 : 0; | 5205 » » » » == BFD_ENDIAN_BIG ? 1 : 0; |
3828 unsigned long regval; | 5206 unsigned long regval; |
3829 | 5207 |
3830 » /* Write the low word of the double to the even register(s). */ | 5208 » /* First word. */ |
3831 » regval = extract_unsigned_integer (val + low_offset, | 5209 » regval = extract_unsigned_integer (val, 4, byte_order); |
3832 » » » » » » 4, byte_order); | |
3833 if (mips_debug) | 5210 if (mips_debug) |
3834 fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | 5211 fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", |
3835 » » » » float_argreg, phex (regval, 4)); | 5212 » » » » float_argreg + freg_offset, |
| 5213 » » » » phex (regval, 4)); |
3836 regcache_cooked_write_unsigned (regcache, | 5214 regcache_cooked_write_unsigned (regcache, |
3837 » » » » » float_argreg++, regval); | 5215 » » » » » float_argreg++ + freg_offset, |
| 5216 » » » » » regval); |
3838 if (mips_debug) | 5217 if (mips_debug) |
3839 fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | 5218 fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", |
3840 argreg, phex (regval, 4)); | 5219 argreg, phex (regval, 4)); |
3841 regcache_cooked_write_unsigned (regcache, argreg++, regval); | 5220 regcache_cooked_write_unsigned (regcache, argreg++, regval); |
3842 | 5221 |
3843 » /* Write the high word of the double to the odd register(s). */ | 5222 » /* Second word. */ |
3844 » regval = extract_unsigned_integer (val + 4 - low_offset, | 5223 » regval = extract_unsigned_integer (val + 4, 4, byte_order); |
3845 » » » » » » 4, byte_order); | |
3846 if (mips_debug) | 5224 if (mips_debug) |
3847 fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | 5225 fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", |
3848 » » » » float_argreg, phex (regval, 4)); | 5226 » » » » float_argreg - freg_offset, |
| 5227 » » » » phex (regval, 4)); |
3849 regcache_cooked_write_unsigned (regcache, | 5228 regcache_cooked_write_unsigned (regcache, |
3850 » » » » » float_argreg++, regval); | 5229 » » » » » float_argreg++ - freg_offset, |
3851 | 5230 » » » » » regval); |
3852 if (mips_debug) | 5231 if (mips_debug) |
3853 fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", | 5232 fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", |
3854 argreg, phex (regval, 4)); | 5233 argreg, phex (regval, 4)); |
3855 regcache_cooked_write_unsigned (regcache, argreg++, regval); | 5234 regcache_cooked_write_unsigned (regcache, argreg++, regval); |
3856 } | 5235 } |
3857 else | 5236 else |
3858 { | 5237 { |
3859 /* This is a floating point value that fits entirely | 5238 /* This is a floating point value that fits entirely |
3860 in a single register. */ | 5239 in a single register. */ |
3861 /* On 32 bit ABI's the float_argreg is further adjusted | 5240 /* On 32 bit ABI's the float_argreg is further adjusted |
(...skipping 154 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... |
4016 fprintf_unfiltered (gdb_stdlog, "\n"); | 5395 fprintf_unfiltered (gdb_stdlog, "\n"); |
4017 } | 5396 } |
4018 | 5397 |
4019 regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp); | 5398 regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp); |
4020 | 5399 |
4021 /* Return adjusted stack pointer. */ | 5400 /* Return adjusted stack pointer. */ |
4022 return sp; | 5401 return sp; |
4023 } | 5402 } |
4024 | 5403 |
4025 static enum return_value_convention | 5404 static enum return_value_convention |
4026 mips_o32_return_value (struct gdbarch *gdbarch, struct type *func_type, | 5405 mips_o32_return_value (struct gdbarch *gdbarch, struct value *function, |
4027 struct type *type, struct regcache *regcache, | 5406 struct type *type, struct regcache *regcache, |
4028 gdb_byte *readbuf, const gdb_byte *writebuf) | 5407 gdb_byte *readbuf, const gdb_byte *writebuf) |
4029 { | 5408 { |
| 5409 CORE_ADDR func_addr = function ? find_function_addr (function, NULL) : 0; |
| 5410 int mips16 = mips_pc_is_mips16 (gdbarch, func_addr); |
4030 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | 5411 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
| 5412 enum mips_fval_reg fval_reg; |
4031 | 5413 |
| 5414 fval_reg = readbuf ? mips16 ? mips_fval_gpr : mips_fval_fpr : mips_fval_both; |
4032 if (TYPE_CODE (type) == TYPE_CODE_STRUCT | 5415 if (TYPE_CODE (type) == TYPE_CODE_STRUCT |
4033 || TYPE_CODE (type) == TYPE_CODE_UNION | 5416 || TYPE_CODE (type) == TYPE_CODE_UNION |
4034 || TYPE_CODE (type) == TYPE_CODE_ARRAY) | 5417 || TYPE_CODE (type) == TYPE_CODE_ARRAY) |
4035 return RETURN_VALUE_STRUCT_CONVENTION; | 5418 return RETURN_VALUE_STRUCT_CONVENTION; |
4036 else if (TYPE_CODE (type) == TYPE_CODE_FLT | 5419 else if (TYPE_CODE (type) == TYPE_CODE_FLT |
4037 && TYPE_LENGTH (type) == 4 && tdep->mips_fpu_type != MIPS_FPU_NONE) | 5420 && TYPE_LENGTH (type) == 4 && tdep->mips_fpu_type != MIPS_FPU_NONE) |
4038 { | 5421 { |
4039 /* A single-precision floating-point value. It fits in the | 5422 /* A single-precision floating-point value. If reading in or copying, |
4040 least significant part of FP0. */ | 5423 then we get it from/put it to FP0 for standard MIPS code or GPR2 |
| 5424 for MIPS16 code. If writing out only, then we put it to both FP0 |
| 5425 and GPR2. We do not support reading in with no function known, if |
| 5426 this safety check ever triggers, then we'll have to try harder. */ |
| 5427 gdb_assert (function || !readbuf); |
4041 if (mips_debug) | 5428 if (mips_debug) |
4042 » fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n"); | 5429 » switch (fval_reg) |
4043 mips_xfer_register (gdbarch, regcache, | 5430 » { |
4044 » » » gdbarch_num_regs (gdbarch) | 5431 » case mips_fval_fpr: |
4045 » » » + mips_regnum (gdbarch)->fp0, | 5432 » fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n"); |
4046 » » » TYPE_LENGTH (type), | 5433 » break; |
4047 » » » gdbarch_byte_order (gdbarch), | 5434 » case mips_fval_gpr: |
4048 » » » readbuf, writebuf, 0); | 5435 » fprintf_unfiltered (gdb_stderr, "Return float in $2\n"); |
| 5436 » break; |
| 5437 » case mips_fval_both: |
| 5438 » fprintf_unfiltered (gdb_stderr, "Return float in $fp0 and $2\n"); |
| 5439 » break; |
| 5440 » } |
| 5441 if (fval_reg != mips_fval_gpr) |
| 5442 » mips_xfer_register (gdbarch, regcache, |
| 5443 » » » (gdbarch_num_regs (gdbarch) |
| 5444 » » » + mips_regnum (gdbarch)->fp0), |
| 5445 » » » TYPE_LENGTH (type), |
| 5446 » » » gdbarch_byte_order (gdbarch), |
| 5447 » » » readbuf, writebuf, 0); |
| 5448 if (fval_reg != mips_fval_fpr) |
| 5449 » mips_xfer_register (gdbarch, regcache, |
| 5450 » » » gdbarch_num_regs (gdbarch) + 2, |
| 5451 » » » TYPE_LENGTH (type), |
| 5452 » » » gdbarch_byte_order (gdbarch), |
| 5453 » » » readbuf, writebuf, 0); |
4049 return RETURN_VALUE_REGISTER_CONVENTION; | 5454 return RETURN_VALUE_REGISTER_CONVENTION; |
4050 } | 5455 } |
4051 else if (TYPE_CODE (type) == TYPE_CODE_FLT | 5456 else if (TYPE_CODE (type) == TYPE_CODE_FLT |
4052 && TYPE_LENGTH (type) == 8 && tdep->mips_fpu_type != MIPS_FPU_NONE) | 5457 && TYPE_LENGTH (type) == 8 && tdep->mips_fpu_type != MIPS_FPU_NONE) |
4053 { | 5458 { |
4054 /* A double-precision floating-point value. The most | 5459 /* A double-precision floating-point value. If reading in or copying, |
4055 significant part goes in FP1, and the least significant in | 5460 then we get it from/put it to FP1 and FP0 for standard MIPS code or |
4056 FP0. */ | 5461 GPR2 and GPR3 for MIPS16 code. If writing out only, then we put it |
| 5462 to both FP1/FP0 and GPR2/GPR3. We do not support reading in with |
| 5463 no function known, if this safety check ever triggers, then we'll |
| 5464 have to try harder. */ |
| 5465 gdb_assert (function || !readbuf); |
4057 if (mips_debug) | 5466 if (mips_debug) |
4058 » fprintf_unfiltered (gdb_stderr, "Return float in $fp1/$fp0\n"); | 5467 » switch (fval_reg) |
4059 switch (gdbarch_byte_order (gdbarch)) | 5468 » { |
| 5469 » case mips_fval_fpr: |
| 5470 » fprintf_unfiltered (gdb_stderr, "Return float in $fp1/$fp0\n"); |
| 5471 » break; |
| 5472 » case mips_fval_gpr: |
| 5473 » fprintf_unfiltered (gdb_stderr, "Return float in $2/$3\n"); |
| 5474 » break; |
| 5475 » case mips_fval_both: |
| 5476 » fprintf_unfiltered (gdb_stderr, |
| 5477 » » » » "Return float in $fp1/$fp0 and $2/$3\n"); |
| 5478 » break; |
| 5479 » } |
| 5480 if (fval_reg != mips_fval_gpr) |
4060 { | 5481 { |
4061 » case BFD_ENDIAN_LITTLE: | 5482 » /* The most significant part goes in FP1, and the least significant |
| 5483 » in FP0. */ |
| 5484 » switch (gdbarch_byte_order (gdbarch)) |
| 5485 » { |
| 5486 » case BFD_ENDIAN_LITTLE: |
| 5487 » mips_xfer_register (gdbarch, regcache, |
| 5488 » » » » (gdbarch_num_regs (gdbarch) |
| 5489 » » » » + mips_regnum (gdbarch)->fp0 + 0), |
| 5490 » » » » 4, gdbarch_byte_order (gdbarch), |
| 5491 » » » » readbuf, writebuf, 0); |
| 5492 » mips_xfer_register (gdbarch, regcache, |
| 5493 » » » » (gdbarch_num_regs (gdbarch) |
| 5494 » » » » + mips_regnum (gdbarch)->fp0 + 1), |
| 5495 » » » » 4, gdbarch_byte_order (gdbarch), |
| 5496 » » » » readbuf, writebuf, 4); |
| 5497 » break; |
| 5498 » case BFD_ENDIAN_BIG: |
| 5499 » mips_xfer_register (gdbarch, regcache, |
| 5500 » » » » (gdbarch_num_regs (gdbarch) |
| 5501 » » » » + mips_regnum (gdbarch)->fp0 + 1), |
| 5502 » » » » 4, gdbarch_byte_order (gdbarch), |
| 5503 » » » » readbuf, writebuf, 0); |
| 5504 » mips_xfer_register (gdbarch, regcache, |
| 5505 » » » » (gdbarch_num_regs (gdbarch) |
| 5506 » » » » + mips_regnum (gdbarch)->fp0 + 0), |
| 5507 » » » » 4, gdbarch_byte_order (gdbarch), |
| 5508 » » » » readbuf, writebuf, 4); |
| 5509 » break; |
| 5510 » default: |
| 5511 » internal_error (__FILE__, __LINE__, _("bad switch")); |
| 5512 » } |
| 5513 » } |
| 5514 if (fval_reg != mips_fval_fpr) |
| 5515 » { |
| 5516 » /* The two 32-bit parts are always placed in GPR2 and GPR3 |
| 5517 » following these registers' memory order. */ |
4062 mips_xfer_register (gdbarch, regcache, | 5518 mips_xfer_register (gdbarch, regcache, |
4063 » » » gdbarch_num_regs (gdbarch) | 5519 » » » gdbarch_num_regs (gdbarch) + 2, |
4064 » » » » + mips_regnum (gdbarch)->fp0 + | |
4065 » » » 0, 4, gdbarch_byte_order (gdbarch), | |
4066 » » » readbuf, writebuf, 0); | |
4067 » mips_xfer_register (gdbarch, regcache, | |
4068 » » » gdbarch_num_regs (gdbarch) | |
4069 » » » » + mips_regnum (gdbarch)->fp0 + 1, | |
4070 » » » 4, gdbarch_byte_order (gdbarch), | |
4071 » » » readbuf, writebuf, 4); | |
4072 » break; | |
4073 » case BFD_ENDIAN_BIG: | |
4074 » mips_xfer_register (gdbarch, regcache, | |
4075 » » » gdbarch_num_regs (gdbarch) | |
4076 » » » » + mips_regnum (gdbarch)->fp0 + 1, | |
4077 4, gdbarch_byte_order (gdbarch), | 5520 4, gdbarch_byte_order (gdbarch), |
4078 readbuf, writebuf, 0); | 5521 readbuf, writebuf, 0); |
4079 mips_xfer_register (gdbarch, regcache, | 5522 mips_xfer_register (gdbarch, regcache, |
4080 » » » gdbarch_num_regs (gdbarch) | 5523 » » » gdbarch_num_regs (gdbarch) + 3, |
4081 » » » » + mips_regnum (gdbarch)->fp0 + 0, | |
4082 4, gdbarch_byte_order (gdbarch), | 5524 4, gdbarch_byte_order (gdbarch), |
4083 readbuf, writebuf, 4); | 5525 readbuf, writebuf, 4); |
4084 break; | |
4085 default: | |
4086 internal_error (__FILE__, __LINE__, _("bad switch")); | |
4087 } | 5526 } |
4088 return RETURN_VALUE_REGISTER_CONVENTION; | 5527 return RETURN_VALUE_REGISTER_CONVENTION; |
4089 } | 5528 } |
4090 #if 0 | 5529 #if 0 |
4091 else if (TYPE_CODE (type) == TYPE_CODE_STRUCT | 5530 else if (TYPE_CODE (type) == TYPE_CODE_STRUCT |
4092 && TYPE_NFIELDS (type) <= 2 | 5531 && TYPE_NFIELDS (type) <= 2 |
4093 && TYPE_NFIELDS (type) >= 1 | 5532 && TYPE_NFIELDS (type) >= 1 |
4094 && ((TYPE_NFIELDS (type) == 1 | 5533 && ((TYPE_NFIELDS (type) == 1 |
4095 && (TYPE_CODE (TYPE_FIELD_TYPE (type, 0)) | 5534 && (TYPE_CODE (TYPE_FIELD_TYPE (type, 0)) |
4096 == TYPE_CODE_FLT)) | 5535 == TYPE_CODE_FLT)) |
(...skipping 87 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... |
4184 struct regcache *regcache, CORE_ADDR bp_addr, | 5623 struct regcache *regcache, CORE_ADDR bp_addr, |
4185 int nargs, | 5624 int nargs, |
4186 struct value **args, CORE_ADDR sp, | 5625 struct value **args, CORE_ADDR sp, |
4187 int struct_return, CORE_ADDR struct_addr) | 5626 int struct_return, CORE_ADDR struct_addr) |
4188 { | 5627 { |
4189 int argreg; | 5628 int argreg; |
4190 int float_argreg; | 5629 int float_argreg; |
4191 int argnum; | 5630 int argnum; |
4192 int len = 0; | 5631 int len = 0; |
4193 int stack_offset = 0; | 5632 int stack_offset = 0; |
4194 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
4195 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | 5633 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
4196 CORE_ADDR func_addr = find_function_addr (function, NULL); | 5634 CORE_ADDR func_addr = find_function_addr (function, NULL); |
4197 | 5635 |
4198 /* For shared libraries, "t9" needs to point at the function | 5636 /* For shared libraries, "t9" needs to point at the function |
4199 address. */ | 5637 address. */ |
4200 regcache_cooked_write_signed (regcache, MIPS_T9_REGNUM, func_addr); | 5638 regcache_cooked_write_signed (regcache, MIPS_T9_REGNUM, func_addr); |
4201 | 5639 |
4202 /* Set the return address register to point to the entry point of | 5640 /* Set the return address register to point to the entry point of |
4203 the program, where a breakpoint lies in wait. */ | 5641 the program, where a breakpoint lies in wait. */ |
4204 regcache_cooked_write_signed (regcache, MIPS_RA_REGNUM, bp_addr); | 5642 regcache_cooked_write_signed (regcache, MIPS_RA_REGNUM, bp_addr); |
(...skipping 58 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... |
4263 | 5701 |
4264 val = value_contents (arg); | 5702 val = value_contents (arg); |
4265 | 5703 |
4266 /* Function pointer arguments to mips16 code need to be made into | 5704 /* Function pointer arguments to mips16 code need to be made into |
4267 mips16 pointers. */ | 5705 mips16 pointers. */ |
4268 if (typecode == TYPE_CODE_PTR | 5706 if (typecode == TYPE_CODE_PTR |
4269 && TYPE_CODE (TYPE_TARGET_TYPE (arg_type)) == TYPE_CODE_FUNC) | 5707 && TYPE_CODE (TYPE_TARGET_TYPE (arg_type)) == TYPE_CODE_FUNC) |
4270 { | 5708 { |
4271 CORE_ADDR addr = extract_signed_integer (value_contents (arg), | 5709 CORE_ADDR addr = extract_signed_integer (value_contents (arg), |
4272 len, byte_order); | 5710 len, byte_order); |
4273 » if (mips_pc_is_mips16 (addr)) | 5711 » if (!mips_pc_is_mips (addr)) |
4274 { | 5712 { |
4275 store_signed_integer (valbuf, len, byte_order, | 5713 store_signed_integer (valbuf, len, byte_order, |
4276 » » » » make_mips16_addr (addr)); | 5714 » » » » make_compact_addr (addr)); |
4277 val = valbuf; | 5715 val = valbuf; |
4278 } | 5716 } |
4279 } | 5717 } |
4280 | 5718 |
4281 /* Floating point arguments passed in registers have to be | 5719 /* Floating point arguments passed in registers have to be |
4282 treated specially. On 32-bit architectures, doubles | 5720 treated specially. On 32-bit architectures, doubles are |
4283 are passed in register pairs; the even register gets | 5721 passed in register pairs; the even FP register gets the |
4284 the low word, and the odd register gets the high word. | 5722 low word, and the odd FP register gets the high word. |
4285 On O32/O64, the first two floating point arguments are | 5723 On O64, the first two floating point arguments are also |
4286 also copied to general registers, because MIPS16 functions | 5724 copied to general registers, because MIPS16 functions |
4287 don't use float registers for arguments. This duplication of | 5725 don't use float registers for arguments. This duplication |
4288 arguments in general registers can't hurt non-MIPS16 functions | 5726 of arguments in general registers can't hurt non-MIPS16 |
4289 because those registers are normally skipped. */ | 5727 functions because those registers are normally skipped. */ |
4290 | 5728 |
4291 if (fp_register_arg_p (gdbarch, typecode, arg_type) | 5729 if (fp_register_arg_p (gdbarch, typecode, arg_type) |
4292 && float_argreg <= MIPS_LAST_FP_ARG_REGNUM (gdbarch)) | 5730 && float_argreg <= MIPS_LAST_FP_ARG_REGNUM (gdbarch)) |
4293 { | 5731 { |
4294 LONGEST regval = extract_unsigned_integer (val, len, byte_order); | 5732 LONGEST regval = extract_unsigned_integer (val, len, byte_order); |
4295 if (mips_debug) | 5733 if (mips_debug) |
4296 fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", | 5734 fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", |
4297 float_argreg, phex (regval, len)); | 5735 float_argreg, phex (regval, len)); |
4298 regcache_cooked_write_unsigned (regcache, float_argreg++, regval); | 5736 regcache_cooked_write_unsigned (regcache, float_argreg++, regval); |
4299 if (mips_debug) | 5737 if (mips_debug) |
(...skipping 124 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... |
4424 fprintf_unfiltered (gdb_stdlog, "\n"); | 5862 fprintf_unfiltered (gdb_stdlog, "\n"); |
4425 } | 5863 } |
4426 | 5864 |
4427 regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp); | 5865 regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp); |
4428 | 5866 |
4429 /* Return adjusted stack pointer. */ | 5867 /* Return adjusted stack pointer. */ |
4430 return sp; | 5868 return sp; |
4431 } | 5869 } |
4432 | 5870 |
4433 static enum return_value_convention | 5871 static enum return_value_convention |
4434 mips_o64_return_value (struct gdbarch *gdbarch, struct type *func_type, | 5872 mips_o64_return_value (struct gdbarch *gdbarch, struct value *function, |
4435 struct type *type, struct regcache *regcache, | 5873 struct type *type, struct regcache *regcache, |
4436 gdb_byte *readbuf, const gdb_byte *writebuf) | 5874 gdb_byte *readbuf, const gdb_byte *writebuf) |
4437 { | 5875 { |
| 5876 CORE_ADDR func_addr = function ? find_function_addr (function, NULL) : 0; |
| 5877 int mips16 = mips_pc_is_mips16 (gdbarch, func_addr); |
4438 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | 5878 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
| 5879 enum mips_fval_reg fval_reg; |
4439 | 5880 |
| 5881 fval_reg = readbuf ? mips16 ? mips_fval_gpr : mips_fval_fpr : mips_fval_both; |
4440 if (TYPE_CODE (type) == TYPE_CODE_STRUCT | 5882 if (TYPE_CODE (type) == TYPE_CODE_STRUCT |
4441 || TYPE_CODE (type) == TYPE_CODE_UNION | 5883 || TYPE_CODE (type) == TYPE_CODE_UNION |
4442 || TYPE_CODE (type) == TYPE_CODE_ARRAY) | 5884 || TYPE_CODE (type) == TYPE_CODE_ARRAY) |
4443 return RETURN_VALUE_STRUCT_CONVENTION; | 5885 return RETURN_VALUE_STRUCT_CONVENTION; |
4444 else if (fp_register_arg_p (gdbarch, TYPE_CODE (type), type)) | 5886 else if (fp_register_arg_p (gdbarch, TYPE_CODE (type), type)) |
4445 { | 5887 { |
4446 /* A floating-point value. It fits in the least significant | 5888 /* A floating-point value. If reading in or copying, then we get it |
4447 part of FP0. */ | 5889 from/put it to FP0 for standard MIPS code or GPR2 for MIPS16 code. |
| 5890 If writing out only, then we put it to both FP0 and GPR2. We do |
| 5891 not support reading in with no function known, if this safety |
| 5892 check ever triggers, then we'll have to try harder. */ |
| 5893 gdb_assert (function || !readbuf); |
4448 if (mips_debug) | 5894 if (mips_debug) |
4449 » fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n"); | 5895 » switch (fval_reg) |
4450 mips_xfer_register (gdbarch, regcache, | 5896 » { |
4451 » » » gdbarch_num_regs (gdbarch) | 5897 » case mips_fval_fpr: |
4452 » » » + mips_regnum (gdbarch)->fp0, | 5898 » fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n"); |
4453 » » » TYPE_LENGTH (type), | 5899 » break; |
4454 » » » gdbarch_byte_order (gdbarch), | 5900 » case mips_fval_gpr: |
4455 » » » readbuf, writebuf, 0); | 5901 » fprintf_unfiltered (gdb_stderr, "Return float in $2\n"); |
| 5902 » break; |
| 5903 » case mips_fval_both: |
| 5904 » fprintf_unfiltered (gdb_stderr, "Return float in $fp0 and $2\n"); |
| 5905 » break; |
| 5906 » } |
| 5907 if (fval_reg != mips_fval_gpr) |
| 5908 » mips_xfer_register (gdbarch, regcache, |
| 5909 » » » (gdbarch_num_regs (gdbarch) |
| 5910 » » » + mips_regnum (gdbarch)->fp0), |
| 5911 » » » TYPE_LENGTH (type), |
| 5912 » » » gdbarch_byte_order (gdbarch), |
| 5913 » » » readbuf, writebuf, 0); |
| 5914 if (fval_reg != mips_fval_fpr) |
| 5915 » mips_xfer_register (gdbarch, regcache, |
| 5916 » » » gdbarch_num_regs (gdbarch) + 2, |
| 5917 » » » TYPE_LENGTH (type), |
| 5918 » » » gdbarch_byte_order (gdbarch), |
| 5919 » » » readbuf, writebuf, 0); |
4456 return RETURN_VALUE_REGISTER_CONVENTION; | 5920 return RETURN_VALUE_REGISTER_CONVENTION; |
4457 } | 5921 } |
4458 else | 5922 else |
4459 { | 5923 { |
4460 /* A scalar extract each part but least-significant-byte | 5924 /* A scalar extract each part but least-significant-byte |
4461 justified. */ | 5925 justified. */ |
4462 int offset; | 5926 int offset; |
4463 int regnum; | 5927 int regnum; |
4464 for (offset = 0, regnum = MIPS_V0_REGNUM; | 5928 for (offset = 0, regnum = MIPS_V0_REGNUM; |
4465 offset < TYPE_LENGTH (type); | 5929 offset < TYPE_LENGTH (type); |
(...skipping 201 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... |
4667 else | 6131 else |
4668 fprintf_filtered (file, "%-24.17g", doub); | 6132 fprintf_filtered (file, "%-24.17g", doub); |
4669 } | 6133 } |
4670 } | 6134 } |
4671 | 6135 |
4672 static void | 6136 static void |
4673 mips_print_register (struct ui_file *file, struct frame_info *frame, | 6137 mips_print_register (struct ui_file *file, struct frame_info *frame, |
4674 int regnum) | 6138 int regnum) |
4675 { | 6139 { |
4676 struct gdbarch *gdbarch = get_frame_arch (frame); | 6140 struct gdbarch *gdbarch = get_frame_arch (frame); |
4677 int offset; | |
4678 struct value_print_options opts; | 6141 struct value_print_options opts; |
4679 struct value *val; | 6142 struct value *val; |
4680 | 6143 |
4681 if (TYPE_CODE (register_type (gdbarch, regnum)) == TYPE_CODE_FLT) | 6144 if (mips_float_register_p (gdbarch, regnum)) |
4682 { | 6145 { |
4683 mips_print_fp_register (file, frame, regnum); | 6146 mips_print_fp_register (file, frame, regnum); |
4684 return; | 6147 return; |
4685 } | 6148 } |
4686 | 6149 |
4687 val = get_frame_register_value (frame, regnum); | 6150 val = get_frame_register_value (frame, regnum); |
4688 if (value_optimized_out (val)) | 6151 if (value_optimized_out (val)) |
4689 { | 6152 { |
4690 fprintf_filtered (file, "%s: [Invalid]", | 6153 fprintf_filtered (file, "%s: [Invalid]", |
4691 gdbarch_register_name (gdbarch, regnum)); | 6154 gdbarch_register_name (gdbarch, regnum)); |
(...skipping 48 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... |
4740 int regnum; | 6203 int regnum; |
4741 | 6204 |
4742 /* For GP registers, we print a separate row of names above the vals. */ | 6205 /* For GP registers, we print a separate row of names above the vals. */ |
4743 for (col = 0, regnum = start_regnum; | 6206 for (col = 0, regnum = start_regnum; |
4744 col < ncols && regnum < gdbarch_num_regs (gdbarch) | 6207 col < ncols && regnum < gdbarch_num_regs (gdbarch) |
4745 + gdbarch_num_pseudo_regs (gdbarch); | 6208 + gdbarch_num_pseudo_regs (gdbarch); |
4746 regnum++) | 6209 regnum++) |
4747 { | 6210 { |
4748 if (*gdbarch_register_name (gdbarch, regnum) == '\0') | 6211 if (*gdbarch_register_name (gdbarch, regnum) == '\0') |
4749 continue; /* unused register */ | 6212 continue; /* unused register */ |
4750 if (TYPE_CODE (register_type (gdbarch, regnum)) == | 6213 if (mips_float_register_p (gdbarch, regnum)) |
4751 » TYPE_CODE_FLT) | |
4752 break; /* End the row: reached FP register. */ | 6214 break; /* End the row: reached FP register. */ |
4753 /* Large registers are handled separately. */ | 6215 /* Large registers are handled separately. */ |
4754 if (register_size (gdbarch, regnum) > mips_abi_regsize (gdbarch)) | 6216 if (register_size (gdbarch, regnum) > mips_abi_regsize (gdbarch)) |
4755 { | 6217 { |
4756 if (col > 0) | 6218 if (col > 0) |
4757 break; /* End the row before this register. */ | 6219 break; /* End the row before this register. */ |
4758 | 6220 |
4759 /* Print this register on a row by itself. */ | 6221 /* Print this register on a row by itself. */ |
4760 mips_print_register (file, frame, regnum); | 6222 mips_print_register (file, frame, regnum); |
4761 fprintf_filtered (file, "\n"); | 6223 fprintf_filtered (file, "\n"); |
(...skipping 18 matching lines...) Expand all Loading... |
4780 fprintf_filtered (file, "\n "); | 6242 fprintf_filtered (file, "\n "); |
4781 | 6243 |
4782 /* Now print the values in hex, 4 or 8 to the row. */ | 6244 /* Now print the values in hex, 4 or 8 to the row. */ |
4783 for (col = 0, regnum = start_regnum; | 6245 for (col = 0, regnum = start_regnum; |
4784 col < ncols && regnum < gdbarch_num_regs (gdbarch) | 6246 col < ncols && regnum < gdbarch_num_regs (gdbarch) |
4785 + gdbarch_num_pseudo_regs (gdbarch); | 6247 + gdbarch_num_pseudo_regs (gdbarch); |
4786 regnum++) | 6248 regnum++) |
4787 { | 6249 { |
4788 if (*gdbarch_register_name (gdbarch, regnum) == '\0') | 6250 if (*gdbarch_register_name (gdbarch, regnum) == '\0') |
4789 continue; /* unused register */ | 6251 continue; /* unused register */ |
4790 if (TYPE_CODE (register_type (gdbarch, regnum)) == | 6252 if (mips_float_register_p (gdbarch, regnum)) |
4791 » TYPE_CODE_FLT) | |
4792 break; /* End row: reached FP register. */ | 6253 break; /* End row: reached FP register. */ |
4793 if (register_size (gdbarch, regnum) > mips_abi_regsize (gdbarch)) | 6254 if (register_size (gdbarch, regnum) > mips_abi_regsize (gdbarch)) |
4794 break; /* End row: large register. */ | 6255 break; /* End row: large register. */ |
4795 | 6256 |
4796 /* OK: get the data in raw format. */ | 6257 /* OK: get the data in raw format. */ |
4797 if (!frame_register_read (frame, regnum, raw_buffer)) | 6258 if (!frame_register_read (frame, regnum, raw_buffer)) |
4798 error (_("can't read register %d (%s)"), | 6259 error (_("can't read register %d (%s)"), |
4799 regnum, gdbarch_register_name (gdbarch, regnum)); | 6260 regnum, gdbarch_register_name (gdbarch, regnum)); |
4800 /* pad small registers */ | 6261 /* pad small registers */ |
4801 for (byte = 0; | 6262 for (byte = 0; |
(...skipping 34 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... |
4836 mips_print_register (file, frame, regnum); | 6297 mips_print_register (file, frame, regnum); |
4837 fprintf_filtered (file, "\n"); | 6298 fprintf_filtered (file, "\n"); |
4838 } | 6299 } |
4839 else | 6300 else |
4840 /* Do all (or most) registers. */ | 6301 /* Do all (or most) registers. */ |
4841 { | 6302 { |
4842 regnum = gdbarch_num_regs (gdbarch); | 6303 regnum = gdbarch_num_regs (gdbarch); |
4843 while (regnum < gdbarch_num_regs (gdbarch) | 6304 while (regnum < gdbarch_num_regs (gdbarch) |
4844 + gdbarch_num_pseudo_regs (gdbarch)) | 6305 + gdbarch_num_pseudo_regs (gdbarch)) |
4845 { | 6306 { |
4846 » if (TYPE_CODE (register_type (gdbarch, regnum)) == | 6307 » if (mips_float_register_p (gdbarch, regnum)) |
4847 » TYPE_CODE_FLT) | |
4848 { | 6308 { |
4849 if (all) /* True for "INFO ALL-REGISTERS" command. */ | 6309 if (all) /* True for "INFO ALL-REGISTERS" command. */ |
4850 regnum = print_fp_register_row (file, frame, regnum); | 6310 regnum = print_fp_register_row (file, frame, regnum); |
4851 else | 6311 else |
4852 regnum += MIPS_NUMREGS; /* Skip floating point regs. */ | 6312 regnum += MIPS_NUMREGS; /* Skip floating point regs. */ |
4853 } | 6313 } |
4854 else | 6314 else |
4855 regnum = print_gp_register_row (file, frame, regnum); | 6315 regnum = print_gp_register_row (file, frame, regnum); |
4856 } | 6316 } |
4857 } | 6317 } |
4858 } | 6318 } |
4859 | 6319 |
4860 /* Is this a branch with a delay slot? */ | |
4861 | |
4862 static int | |
4863 is_delayed (unsigned long insn) | |
4864 { | |
4865 int i; | |
4866 for (i = 0; i < NUMOPCODES; ++i) | |
4867 if (mips_opcodes[i].pinfo != INSN_MACRO | |
4868 && (insn & mips_opcodes[i].mask) == mips_opcodes[i].match) | |
4869 break; | |
4870 return (i < NUMOPCODES | |
4871 && (mips_opcodes[i].pinfo & (INSN_UNCOND_BRANCH_DELAY | |
4872 | INSN_COND_BRANCH_DELAY | |
4873 | INSN_COND_BRANCH_LIKELY))); | |
4874 } | |
4875 | |
4876 static int | 6320 static int |
4877 mips_single_step_through_delay (struct gdbarch *gdbarch, | 6321 mips_single_step_through_delay (struct gdbarch *gdbarch, |
4878 struct frame_info *frame) | 6322 struct frame_info *frame) |
4879 { | 6323 { |
4880 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | 6324 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
4881 CORE_ADDR pc = get_frame_pc (frame); | 6325 CORE_ADDR pc = get_frame_pc (frame); |
4882 gdb_byte buf[MIPS_INSN32_SIZE]; | 6326 struct address_space *aspace; |
| 6327 enum mips_isa isa; |
| 6328 ULONGEST insn; |
| 6329 int status; |
| 6330 int size; |
4883 | 6331 |
4884 /* There is no branch delay slot on MIPS16. */ | 6332 if ((mips_pc_is_mips (pc) |
4885 if (mips_pc_is_mips16 (pc)) | 6333 && !mips32_instruction_has_delay_slot (gdbarch, pc)) |
| 6334 || (mips_pc_is_micromips (gdbarch, pc) |
| 6335 » && !micromips_instruction_has_delay_slot (gdbarch, pc, 0)) |
| 6336 || (mips_pc_is_mips16 (gdbarch, pc) |
| 6337 » && !mips16_instruction_has_delay_slot (gdbarch, pc, 0))) |
4886 return 0; | 6338 return 0; |
4887 | 6339 |
4888 if (!breakpoint_here_p (get_frame_address_space (frame), pc + 4)) | 6340 isa = mips_pc_isa (gdbarch, pc); |
4889 return 0; | 6341 /* _has_delay_slot above will have validated the read. */ |
4890 | 6342 insn = mips_fetch_instruction (gdbarch, isa, pc, NULL); |
4891 if (!safe_frame_unwind_memory (frame, pc, buf, sizeof buf)) | 6343 size = mips_insn_size (isa, insn); |
4892 /* If error reading memory, guess that it is not a delayed | 6344 aspace = get_frame_address_space (frame); |
4893 branch. */ | 6345 return breakpoint_here_p (aspace, pc + size) != no_breakpoint_here; |
4894 return 0; | |
4895 return is_delayed (extract_unsigned_integer (buf, sizeof buf, byte_order)); | |
4896 } | 6346 } |
4897 | 6347 |
4898 /* To skip prologues, I use this predicate. Returns either PC itself | 6348 /* To skip prologues, I use this predicate. Returns either PC itself |
4899 if the code at PC does not look like a function prologue; otherwise | 6349 if the code at PC does not look like a function prologue; otherwise |
4900 returns an address that (if we're lucky) follows the prologue. If | 6350 returns an address that (if we're lucky) follows the prologue. If |
4901 LENIENT, then we must skip everything which is involved in setting | 6351 LENIENT, then we must skip everything which is involved in setting |
4902 up the frame (it's OK to skip more, just so long as we don't skip | 6352 up the frame (it's OK to skip more, just so long as we don't skip |
4903 anything which might clobber the registers which are being saved. | 6353 anything which might clobber the registers which are being saved. |
4904 We must skip more in the case where part of the prologue is in the | 6354 We must skip more in the case where part of the prologue is in the |
4905 delay slot of a non-prologue instruction). */ | 6355 delay slot of a non-prologue instruction). */ |
(...skipping 18 matching lines...) Expand all Loading... |
4924 /* Can't determine prologue from the symbol table, need to examine | 6374 /* Can't determine prologue from the symbol table, need to examine |
4925 instructions. */ | 6375 instructions. */ |
4926 | 6376 |
4927 /* Find an upper limit on the function prologue using the debug | 6377 /* Find an upper limit on the function prologue using the debug |
4928 information. If the debug information could not be used to provide | 6378 information. If the debug information could not be used to provide |
4929 that bound, then use an arbitrary large number as the upper bound. */ | 6379 that bound, then use an arbitrary large number as the upper bound. */ |
4930 limit_pc = skip_prologue_using_sal (gdbarch, pc); | 6380 limit_pc = skip_prologue_using_sal (gdbarch, pc); |
4931 if (limit_pc == 0) | 6381 if (limit_pc == 0) |
4932 limit_pc = pc + 100; /* Magic. */ | 6382 limit_pc = pc + 100; /* Magic. */ |
4933 | 6383 |
4934 if (mips_pc_is_mips16 (pc)) | 6384 if (mips_pc_is_mips16 (gdbarch, pc)) |
4935 return mips16_scan_prologue (gdbarch, pc, limit_pc, NULL, NULL); | 6385 return mips16_scan_prologue (gdbarch, pc, limit_pc, NULL, NULL); |
| 6386 else if (mips_pc_is_micromips (gdbarch, pc)) |
| 6387 return micromips_scan_prologue (gdbarch, pc, limit_pc, NULL, NULL); |
4936 else | 6388 else |
4937 return mips32_scan_prologue (gdbarch, pc, limit_pc, NULL, NULL); | 6389 return mips32_scan_prologue (gdbarch, pc, limit_pc, NULL, NULL); |
4938 } | 6390 } |
4939 | 6391 |
4940 /* Check whether the PC is in a function epilogue (32-bit version). | 6392 /* Check whether the PC is in a function epilogue (32-bit version). |
4941 This is a helper function for mips_in_function_epilogue_p. */ | 6393 This is a helper function for mips_in_function_epilogue_p. */ |
4942 static int | 6394 static int |
4943 mips32_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc) | 6395 mips32_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc) |
4944 { | 6396 { |
4945 CORE_ADDR func_addr = 0, func_end = 0; | 6397 CORE_ADDR func_addr = 0, func_end = 0; |
4946 | 6398 |
4947 if (find_pc_partial_function (pc, NULL, &func_addr, &func_end)) | 6399 if (find_pc_partial_function (pc, NULL, &func_addr, &func_end)) |
4948 { | 6400 { |
4949 /* The MIPS epilogue is max. 12 bytes long. */ | 6401 /* The MIPS epilogue is max. 12 bytes long. */ |
4950 CORE_ADDR addr = func_end - 12; | 6402 CORE_ADDR addr = func_end - 12; |
4951 | 6403 |
4952 if (addr < func_addr + 4) | 6404 if (addr < func_addr + 4) |
4953 addr = func_addr + 4; | 6405 addr = func_addr + 4; |
4954 if (pc < addr) | 6406 if (pc < addr) |
4955 return 0; | 6407 return 0; |
4956 | 6408 |
4957 for (; pc < func_end; pc += MIPS_INSN32_SIZE) | 6409 for (; pc < func_end; pc += MIPS_INSN32_SIZE) |
4958 { | 6410 { |
4959 unsigned long high_word; | 6411 unsigned long high_word; |
4960 unsigned long inst; | 6412 unsigned long inst; |
4961 | 6413 |
4962 » inst = mips_fetch_instruction (gdbarch, pc); | 6414 » inst = mips_fetch_instruction (gdbarch, ISA_MIPS, pc, NULL); |
4963 high_word = (inst >> 16) & 0xffff; | 6415 high_word = (inst >> 16) & 0xffff; |
4964 | 6416 |
4965 if (high_word != 0x27bd /* addiu $sp,$sp,offset */ | 6417 if (high_word != 0x27bd /* addiu $sp,$sp,offset */ |
4966 && high_word != 0x67bd /* daddiu $sp,$sp,offset */ | 6418 && high_word != 0x67bd /* daddiu $sp,$sp,offset */ |
4967 && inst != 0x03e00008 /* jr $ra */ | 6419 && inst != 0x03e00008 /* jr $ra */ |
4968 && inst != 0x00000000) /* nop */ | 6420 && inst != 0x00000000) /* nop */ |
4969 return 0; | 6421 return 0; |
4970 } | 6422 } |
4971 | 6423 |
4972 return 1; | 6424 return 1; |
4973 } | 6425 } |
4974 | 6426 |
4975 return 0; | 6427 return 0; |
4976 } | 6428 } |
4977 | 6429 |
| 6430 /* Check whether the PC is in a function epilogue (microMIPS version). |
| 6431 This is a helper function for mips_in_function_epilogue_p. */ |
| 6432 |
| 6433 static int |
| 6434 micromips_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc) |
| 6435 { |
| 6436 CORE_ADDR func_addr = 0; |
| 6437 CORE_ADDR func_end = 0; |
| 6438 CORE_ADDR addr; |
| 6439 ULONGEST insn; |
| 6440 long offset; |
| 6441 int dreg; |
| 6442 int sreg; |
| 6443 int loc; |
| 6444 |
| 6445 if (!find_pc_partial_function (pc, NULL, &func_addr, &func_end)) |
| 6446 return 0; |
| 6447 |
| 6448 /* The microMIPS epilogue is max. 12 bytes long. */ |
| 6449 addr = func_end - 12; |
| 6450 |
| 6451 if (addr < func_addr + 2) |
| 6452 addr = func_addr + 2; |
| 6453 if (pc < addr) |
| 6454 return 0; |
| 6455 |
| 6456 for (; pc < func_end; pc += loc) |
| 6457 { |
| 6458 loc = 0; |
| 6459 insn = mips_fetch_instruction (gdbarch, ISA_MICROMIPS, pc, NULL); |
| 6460 loc += MIPS_INSN16_SIZE; |
| 6461 switch (mips_insn_size (ISA_MICROMIPS, insn)) |
| 6462 { |
| 6463 /* 48-bit instructions. */ |
| 6464 case 3 * MIPS_INSN16_SIZE: |
| 6465 /* No epilogue instructions in this category. */ |
| 6466 return 0; |
| 6467 |
| 6468 /* 32-bit instructions. */ |
| 6469 case 2 * MIPS_INSN16_SIZE: |
| 6470 insn <<= 16; |
| 6471 insn |= mips_fetch_instruction (gdbarch, |
| 6472 ISA_MICROMIPS, pc + loc, NULL); |
| 6473 loc += MIPS_INSN16_SIZE; |
| 6474 switch (micromips_op (insn >> 16)) |
| 6475 { |
| 6476 case 0xc: /* ADDIU: bits 001100 */ |
| 6477 case 0x17: /* DADDIU: bits 010111 */ |
| 6478 sreg = b0s5_reg (insn >> 16); |
| 6479 dreg = b5s5_reg (insn >> 16); |
| 6480 offset = (b0s16_imm (insn) ^ 0x8000) - 0x8000; |
| 6481 if (sreg == MIPS_SP_REGNUM && dreg == MIPS_SP_REGNUM |
| 6482 /* (D)ADDIU $sp, imm */ |
| 6483 && offset >= 0) |
| 6484 break; |
| 6485 return 0; |
| 6486 |
| 6487 default: |
| 6488 return 0; |
| 6489 } |
| 6490 break; |
| 6491 |
| 6492 /* 16-bit instructions. */ |
| 6493 case MIPS_INSN16_SIZE: |
| 6494 switch (micromips_op (insn)) |
| 6495 { |
| 6496 case 0x3: /* MOVE: bits 000011 */ |
| 6497 sreg = b0s5_reg (insn); |
| 6498 dreg = b5s5_reg (insn); |
| 6499 if (sreg == 0 && dreg == 0) |
| 6500 /* MOVE $zero, $zero aka NOP */ |
| 6501 break; |
| 6502 return 0; |
| 6503 |
| 6504 case 0x11: /* POOL16C: bits 010001 */ |
| 6505 if (b5s5_op (insn) == 0x18 |
| 6506 /* JRADDIUSP: bits 010011 11000 */ |
| 6507 || (b5s5_op (insn) == 0xd |
| 6508 /* JRC: bits 010011 01101 */ |
| 6509 && b0s5_reg (insn) == MIPS_RA_REGNUM)) |
| 6510 /* JRC $ra */ |
| 6511 break; |
| 6512 return 0; |
| 6513 |
| 6514 case 0x13: /* POOL16D: bits 010011 */ |
| 6515 offset = micromips_decode_imm9 (b1s9_imm (insn)); |
| 6516 if ((insn & 0x1) == 0x1 |
| 6517 /* ADDIUSP: bits 010011 1 */ |
| 6518 && offset > 0) |
| 6519 break; |
| 6520 return 0; |
| 6521 |
| 6522 default: |
| 6523 return 0; |
| 6524 } |
| 6525 } |
| 6526 } |
| 6527 |
| 6528 return 1; |
| 6529 } |
| 6530 |
4978 /* Check whether the PC is in a function epilogue (16-bit version). | 6531 /* Check whether the PC is in a function epilogue (16-bit version). |
4979 This is a helper function for mips_in_function_epilogue_p. */ | 6532 This is a helper function for mips_in_function_epilogue_p. */ |
4980 static int | 6533 static int |
4981 mips16_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc) | 6534 mips16_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc) |
4982 { | 6535 { |
4983 CORE_ADDR func_addr = 0, func_end = 0; | 6536 CORE_ADDR func_addr = 0, func_end = 0; |
4984 | 6537 |
4985 if (find_pc_partial_function (pc, NULL, &func_addr, &func_end)) | 6538 if (find_pc_partial_function (pc, NULL, &func_addr, &func_end)) |
4986 { | 6539 { |
4987 /* The MIPS epilogue is max. 12 bytes long. */ | 6540 /* The MIPS epilogue is max. 12 bytes long. */ |
4988 CORE_ADDR addr = func_end - 12; | 6541 CORE_ADDR addr = func_end - 12; |
4989 | 6542 |
4990 if (addr < func_addr + 4) | 6543 if (addr < func_addr + 4) |
4991 addr = func_addr + 4; | 6544 addr = func_addr + 4; |
4992 if (pc < addr) | 6545 if (pc < addr) |
4993 return 0; | 6546 return 0; |
4994 | 6547 |
4995 for (; pc < func_end; pc += MIPS_INSN16_SIZE) | 6548 for (; pc < func_end; pc += MIPS_INSN16_SIZE) |
4996 { | 6549 { |
4997 unsigned short inst; | 6550 unsigned short inst; |
4998 | 6551 |
4999 » inst = mips_fetch_instruction (gdbarch, pc); | 6552 » inst = mips_fetch_instruction (gdbarch, ISA_MIPS16, pc, NULL); |
5000 | 6553 |
5001 if ((inst & 0xf800) == 0xf000) /* extend */ | 6554 if ((inst & 0xf800) == 0xf000) /* extend */ |
5002 continue; | 6555 continue; |
5003 | 6556 |
5004 if (inst != 0x6300 /* addiu $sp,offset */ | 6557 if (inst != 0x6300 /* addiu $sp,offset */ |
5005 && inst != 0xfb00 /* daddiu $sp,$sp,offset */ | 6558 && inst != 0xfb00 /* daddiu $sp,$sp,offset */ |
5006 && inst != 0xe820 /* jr $ra */ | 6559 && inst != 0xe820 /* jr $ra */ |
5007 && inst != 0xe8a0 /* jrc $ra */ | 6560 && inst != 0xe8a0 /* jrc $ra */ |
5008 && inst != 0x6500) /* nop */ | 6561 && inst != 0x6500) /* nop */ |
5009 return 0; | 6562 return 0; |
5010 } | 6563 } |
5011 | 6564 |
5012 return 1; | 6565 return 1; |
5013 } | 6566 } |
5014 | 6567 |
5015 return 0; | 6568 return 0; |
5016 } | 6569 } |
5017 | 6570 |
5018 /* The epilogue is defined here as the area at the end of a function, | 6571 /* The epilogue is defined here as the area at the end of a function, |
5019 after an instruction which destroys the function's stack frame. */ | 6572 after an instruction which destroys the function's stack frame. */ |
5020 static int | 6573 static int |
5021 mips_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc) | 6574 mips_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc) |
5022 { | 6575 { |
5023 if (mips_pc_is_mips16 (pc)) | 6576 if (mips_pc_is_mips16 (gdbarch, pc)) |
5024 return mips16_in_function_epilogue_p (gdbarch, pc); | 6577 return mips16_in_function_epilogue_p (gdbarch, pc); |
| 6578 else if (mips_pc_is_micromips (gdbarch, pc)) |
| 6579 return micromips_in_function_epilogue_p (gdbarch, pc); |
5025 else | 6580 else |
5026 return mips32_in_function_epilogue_p (gdbarch, pc); | 6581 return mips32_in_function_epilogue_p (gdbarch, pc); |
5027 } | 6582 } |
5028 | 6583 |
5029 /* Root of all "set mips "/"show mips " commands. This will eventually be | 6584 /* Root of all "set mips "/"show mips " commands. This will eventually be |
5030 used for all MIPS-specific commands. */ | 6585 used for all MIPS-specific commands. */ |
5031 | 6586 |
5032 static void | 6587 static void |
5033 show_mips_command (char *args, int from_tty) | 6588 show_mips_command (char *args, int from_tty) |
5034 { | 6589 { |
(...skipping 128 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... |
5163 static void | 6718 static void |
5164 reinit_frame_cache_sfunc (char *args, int from_tty, | 6719 reinit_frame_cache_sfunc (char *args, int from_tty, |
5165 struct cmd_list_element *c) | 6720 struct cmd_list_element *c) |
5166 { | 6721 { |
5167 reinit_frame_cache (); | 6722 reinit_frame_cache (); |
5168 } | 6723 } |
5169 | 6724 |
5170 static int | 6725 static int |
5171 gdb_print_insn_mips (bfd_vma memaddr, struct disassemble_info *info) | 6726 gdb_print_insn_mips (bfd_vma memaddr, struct disassemble_info *info) |
5172 { | 6727 { |
| 6728 struct gdbarch *gdbarch = info->application_data; |
| 6729 |
5173 /* FIXME: cagney/2003-06-26: Is this even necessary? The | 6730 /* FIXME: cagney/2003-06-26: Is this even necessary? The |
5174 disassembler needs to be able to locally determine the ISA, and | 6731 disassembler needs to be able to locally determine the ISA, and |
5175 not rely on GDB. Otherwize the stand-alone 'objdump -d' will not | 6732 not rely on GDB. Otherwize the stand-alone 'objdump -d' will not |
5176 work. */ | 6733 work. */ |
5177 if (mips_pc_is_mips16 (memaddr)) | 6734 if (mips_pc_is_mips16 (gdbarch, memaddr)) |
5178 info->mach = bfd_mach_mips16; | 6735 info->mach = bfd_mach_mips16; |
| 6736 else if (mips_pc_is_micromips (gdbarch, memaddr)) |
| 6737 info->mach = bfd_mach_mips_micromips; |
5179 | 6738 |
5180 /* Round down the instruction address to the appropriate boundary. */ | 6739 /* Round down the instruction address to the appropriate boundary. */ |
5181 memaddr &= (info->mach == bfd_mach_mips16 ? ~1 : ~3); | 6740 memaddr &= (info->mach == bfd_mach_mips16 |
| 6741 » || info->mach == bfd_mach_mips_micromips) ? ~1 : ~3; |
5182 | 6742 |
5183 /* Set the disassembler options. */ | 6743 /* Set the disassembler options. */ |
5184 if (!info->disassembler_options) | 6744 if (!info->disassembler_options) |
5185 /* This string is not recognized explicitly by the disassembler, | 6745 /* This string is not recognized explicitly by the disassembler, |
5186 but it tells the disassembler to not try to guess the ABI from | 6746 but it tells the disassembler to not try to guess the ABI from |
5187 the bfd elf headers, such that, if the user overrides the ABI | 6747 the bfd elf headers, such that, if the user overrides the ABI |
5188 of a program linked as NewABI, the disassembly will follow the | 6748 of a program linked as NewABI, the disassembly will follow the |
5189 register naming conventions specified by the user. */ | 6749 register naming conventions specified by the user. */ |
5190 info->disassembler_options = "gpr-names=32"; | 6750 info->disassembler_options = "gpr-names=32"; |
5191 | 6751 |
(...skipping 30 matching lines...) Expand all Loading... |
5222 program counter value to determine whether a 16- or 32-bit breakpoint | 6782 program counter value to determine whether a 16- or 32-bit breakpoint |
5223 should be used. It returns a pointer to a string of bytes that encode a | 6783 should be used. It returns a pointer to a string of bytes that encode a |
5224 breakpoint instruction, stores the length of the string to *lenptr, and | 6784 breakpoint instruction, stores the length of the string to *lenptr, and |
5225 adjusts pc (if necessary) to point to the actual memory location where | 6785 adjusts pc (if necessary) to point to the actual memory location where |
5226 the breakpoint should be inserted. */ | 6786 the breakpoint should be inserted. */ |
5227 | 6787 |
5228 static const gdb_byte * | 6788 static const gdb_byte * |
5229 mips_breakpoint_from_pc (struct gdbarch *gdbarch, | 6789 mips_breakpoint_from_pc (struct gdbarch *gdbarch, |
5230 CORE_ADDR *pcptr, int *lenptr) | 6790 CORE_ADDR *pcptr, int *lenptr) |
5231 { | 6791 { |
| 6792 CORE_ADDR pc = *pcptr; |
| 6793 |
5232 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) | 6794 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) |
5233 { | 6795 { |
5234 if (mips_pc_is_mips16 (*pcptr)) | 6796 if (mips_pc_is_mips16 (gdbarch, pc)) |
5235 { | 6797 { |
5236 static gdb_byte mips16_big_breakpoint[] = { 0xe8, 0xa5 }; | 6798 static gdb_byte mips16_big_breakpoint[] = { 0xe8, 0xa5 }; |
5237 » *pcptr = unmake_mips16_addr (*pcptr); | 6799 » *pcptr = unmake_compact_addr (pc); |
5238 *lenptr = sizeof (mips16_big_breakpoint); | 6800 *lenptr = sizeof (mips16_big_breakpoint); |
5239 return mips16_big_breakpoint; | 6801 return mips16_big_breakpoint; |
5240 } | 6802 } |
| 6803 else if (mips_pc_is_micromips (gdbarch, pc)) |
| 6804 { |
| 6805 static gdb_byte micromips16_big_breakpoint[] = { 0x46, 0x85 }; |
| 6806 static gdb_byte micromips32_big_breakpoint[] = { 0, 0x5, 0, 0x7 }; |
| 6807 ULONGEST insn; |
| 6808 int status; |
| 6809 int size; |
| 6810 |
| 6811 insn = mips_fetch_instruction (gdbarch, ISA_MICROMIPS, pc, &status); |
| 6812 size = status ? 2 |
| 6813 : mips_insn_size (ISA_MICROMIPS, insn) == 2 ? 2 : 4; |
| 6814 *pcptr = unmake_compact_addr (pc); |
| 6815 *lenptr = size; |
| 6816 return (size == 2) ? micromips16_big_breakpoint |
| 6817 : micromips32_big_breakpoint; |
| 6818 } |
5241 else | 6819 else |
5242 { | 6820 { |
5243 /* The IDT board uses an unusual breakpoint value, and | 6821 /* The IDT board uses an unusual breakpoint value, and |
5244 sometimes gets confused when it sees the usual MIPS | 6822 sometimes gets confused when it sees the usual MIPS |
5245 breakpoint instruction. */ | 6823 breakpoint instruction. */ |
5246 static gdb_byte big_breakpoint[] = { 0, 0x5, 0, 0xd }; | 6824 static gdb_byte big_breakpoint[] = { 0, 0x5, 0, 0xd }; |
5247 static gdb_byte pmon_big_breakpoint[] = { 0, 0, 0, 0xd }; | 6825 static gdb_byte pmon_big_breakpoint[] = { 0, 0, 0, 0xd }; |
5248 static gdb_byte idt_big_breakpoint[] = { 0, 0, 0x0a, 0xd }; | 6826 static gdb_byte idt_big_breakpoint[] = { 0, 0, 0x0a, 0xd }; |
5249 /* Likewise, IRIX appears to expect a different breakpoint, | 6827 /* Likewise, IRIX appears to expect a different breakpoint, |
5250 although this is not apparent until you try to use pthreads. */ | 6828 although this is not apparent until you try to use pthreads. */ |
5251 static gdb_byte irix_big_breakpoint[] = { 0, 0, 0, 0xd }; | 6829 static gdb_byte irix_big_breakpoint[] = { 0, 0, 0, 0xd }; |
5252 | 6830 |
5253 *lenptr = sizeof (big_breakpoint); | 6831 *lenptr = sizeof (big_breakpoint); |
5254 | 6832 |
5255 if (strcmp (target_shortname, "mips") == 0) | 6833 if (strcmp (target_shortname, "mips") == 0) |
5256 return idt_big_breakpoint; | 6834 return idt_big_breakpoint; |
5257 else if (strcmp (target_shortname, "ddb") == 0 | 6835 else if (strcmp (target_shortname, "ddb") == 0 |
5258 || strcmp (target_shortname, "pmon") == 0 | 6836 || strcmp (target_shortname, "pmon") == 0 |
5259 || strcmp (target_shortname, "lsi") == 0) | 6837 || strcmp (target_shortname, "lsi") == 0) |
5260 return pmon_big_breakpoint; | 6838 return pmon_big_breakpoint; |
5261 else if (gdbarch_osabi (gdbarch) == GDB_OSABI_IRIX) | 6839 else if (gdbarch_osabi (gdbarch) == GDB_OSABI_IRIX) |
5262 return irix_big_breakpoint; | 6840 return irix_big_breakpoint; |
5263 else | 6841 else |
5264 return big_breakpoint; | 6842 return big_breakpoint; |
5265 } | 6843 } |
5266 } | 6844 } |
5267 else | 6845 else |
5268 { | 6846 { |
5269 if (mips_pc_is_mips16 (*pcptr)) | 6847 if (mips_pc_is_mips16 (gdbarch, pc)) |
5270 { | 6848 { |
5271 static gdb_byte mips16_little_breakpoint[] = { 0xa5, 0xe8 }; | 6849 static gdb_byte mips16_little_breakpoint[] = { 0xa5, 0xe8 }; |
5272 » *pcptr = unmake_mips16_addr (*pcptr); | 6850 » *pcptr = unmake_compact_addr (pc); |
5273 *lenptr = sizeof (mips16_little_breakpoint); | 6851 *lenptr = sizeof (mips16_little_breakpoint); |
5274 return mips16_little_breakpoint; | 6852 return mips16_little_breakpoint; |
5275 } | 6853 } |
| 6854 else if (mips_pc_is_micromips (gdbarch, pc)) |
| 6855 { |
| 6856 static gdb_byte micromips16_little_breakpoint[] = { 0x85, 0x46 }; |
| 6857 static gdb_byte micromips32_little_breakpoint[] = { 0x5, 0, 0x7, 0 }; |
| 6858 ULONGEST insn; |
| 6859 int status; |
| 6860 int size; |
| 6861 |
| 6862 insn = mips_fetch_instruction (gdbarch, ISA_MICROMIPS, pc, &status); |
| 6863 size = status ? 2 |
| 6864 : mips_insn_size (ISA_MICROMIPS, insn) == 2 ? 2 : 4; |
| 6865 *pcptr = unmake_compact_addr (pc); |
| 6866 *lenptr = size; |
| 6867 return (size == 2) ? micromips16_little_breakpoint |
| 6868 : micromips32_little_breakpoint; |
| 6869 } |
5276 else | 6870 else |
5277 { | 6871 { |
5278 static gdb_byte little_breakpoint[] = { 0xd, 0, 0x5, 0 }; | 6872 static gdb_byte little_breakpoint[] = { 0xd, 0, 0x5, 0 }; |
5279 static gdb_byte pmon_little_breakpoint[] = { 0xd, 0, 0, 0 }; | 6873 static gdb_byte pmon_little_breakpoint[] = { 0xd, 0, 0, 0 }; |
5280 static gdb_byte idt_little_breakpoint[] = { 0xd, 0x0a, 0, 0 }; | 6874 static gdb_byte idt_little_breakpoint[] = { 0xd, 0x0a, 0, 0 }; |
5281 | 6875 |
5282 *lenptr = sizeof (little_breakpoint); | 6876 *lenptr = sizeof (little_breakpoint); |
5283 | 6877 |
5284 if (strcmp (target_shortname, "mips") == 0) | 6878 if (strcmp (target_shortname, "mips") == 0) |
5285 return idt_little_breakpoint; | 6879 return idt_little_breakpoint; |
5286 else if (strcmp (target_shortname, "ddb") == 0 | 6880 else if (strcmp (target_shortname, "ddb") == 0 |
5287 || strcmp (target_shortname, "pmon") == 0 | 6881 || strcmp (target_shortname, "pmon") == 0 |
5288 || strcmp (target_shortname, "lsi") == 0) | 6882 || strcmp (target_shortname, "lsi") == 0) |
5289 return pmon_little_breakpoint; | 6883 return pmon_little_breakpoint; |
5290 else | 6884 else |
5291 return little_breakpoint; | 6885 return little_breakpoint; |
5292 } | 6886 } |
5293 } | 6887 } |
5294 } | 6888 } |
5295 | 6889 |
5296 /* If PC is in a mips16 call or return stub, return the address of the target | 6890 /* Determine the remote breakpoint kind suitable for the PC. The following |
5297 PC, which is either the callee or the caller. There are several | 6891 kinds are used: |
| 6892 |
| 6893 * 2 -- 16-bit MIPS16 mode breakpoint, |
| 6894 |
| 6895 * 3 -- 16-bit microMIPS mode breakpoint, |
| 6896 |
| 6897 * 4 -- 32-bit standard MIPS mode breakpoint, |
| 6898 |
| 6899 * 5 -- 32-bit microMIPS mode breakpoint. */ |
| 6900 |
| 6901 static void |
| 6902 mips_remote_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr, |
| 6903 int *kindptr) |
| 6904 { |
| 6905 CORE_ADDR pc = *pcptr; |
| 6906 |
| 6907 if (mips_pc_is_mips16 (gdbarch, pc)) |
| 6908 { |
| 6909 *pcptr = unmake_compact_addr (pc); |
| 6910 *kindptr = 2; |
| 6911 } |
| 6912 else if (mips_pc_is_micromips (gdbarch, pc)) |
| 6913 { |
| 6914 ULONGEST insn; |
| 6915 int status; |
| 6916 int size; |
| 6917 |
| 6918 insn = mips_fetch_instruction (gdbarch, ISA_MICROMIPS, pc, &status); |
| 6919 size = status ? 2 : mips_insn_size (ISA_MICROMIPS, insn) == 2 ? 2 : 4; |
| 6920 *pcptr = unmake_compact_addr (pc); |
| 6921 *kindptr = size | 1; |
| 6922 } |
| 6923 else |
| 6924 *kindptr = 4; |
| 6925 } |
| 6926 |
| 6927 /* Return non-zero if the ADDR instruction has a branch delay slot |
| 6928 (i.e. it is a jump or branch instruction). This function is based |
| 6929 on mips32_next_pc. */ |
| 6930 |
| 6931 static int |
| 6932 mips32_instruction_has_delay_slot (struct gdbarch *gdbarch, CORE_ADDR addr) |
| 6933 { |
| 6934 unsigned long inst; |
| 6935 int status; |
| 6936 int op; |
| 6937 int rs; |
| 6938 int rt; |
| 6939 |
| 6940 inst = mips_fetch_instruction (gdbarch, ISA_MIPS, addr, &status); |
| 6941 if (status) |
| 6942 return 0; |
| 6943 |
| 6944 op = itype_op (inst); |
| 6945 if ((inst & 0xe0000000) != 0) |
| 6946 { |
| 6947 rs = itype_rs (inst); |
| 6948 rt = itype_rt (inst); |
| 6949 return (op >> 2 == 5 /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */ |
| 6950 || op == 29 /* JALX: bits 011101 */ |
| 6951 || (op == 17 |
| 6952 && (rs == 8 |
| 6953 /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */ |
| 6954 || (rs == 9 && (rt & 0x2) == 0) |
| 6955 /* BC1ANY2F, BC1ANY2T: bits 010001 01001 */ |
| 6956 || (rs == 10 && (rt & 0x2) == 0)))); |
| 6957 /* BC1ANY4F, BC1ANY4T: bits 010001 01010 */ |
| 6958 } |
| 6959 else |
| 6960 switch (op & 0x07) /* extract bits 28,27,26 */ |
| 6961 { |
| 6962 case 0: /* SPECIAL */ |
| 6963 op = rtype_funct (inst); |
| 6964 return (op == 8 /* JR */ |
| 6965 || op == 9); /* JALR */ |
| 6966 break; /* end SPECIAL */ |
| 6967 case 1: /* REGIMM */ |
| 6968 rs = itype_rs (inst); |
| 6969 rt = itype_rt (inst); /* branch condition */ |
| 6970 return ((rt & 0xc) == 0 |
| 6971 /* BLTZ, BLTZL, BGEZ, BGEZL: bits 000xx */ |
| 6972 /* BLTZAL, BLTZALL, BGEZAL, BGEZALL: 100xx */ |
| 6973 || ((rt & 0x1e) == 0x1c && rs == 0)); |
| 6974 /* BPOSGE32, BPOSGE64: bits 1110x */ |
| 6975 break; /* end REGIMM */ |
| 6976 default: /* J, JAL, BEQ, BNE, BLEZ, BGTZ */ |
| 6977 return 1; |
| 6978 break; |
| 6979 } |
| 6980 } |
| 6981 |
| 6982 /* Return non-zero if the ADDR instruction, which must be a 32-bit |
| 6983 instruction if MUSTBE32 is set or can be any instruction otherwise, |
| 6984 has a branch delay slot (i.e. it is a non-compact jump instruction). */ |
| 6985 |
| 6986 static int |
| 6987 micromips_instruction_has_delay_slot (struct gdbarch *gdbarch, |
| 6988 CORE_ADDR addr, int mustbe32) |
| 6989 { |
| 6990 ULONGEST insn; |
| 6991 int status; |
| 6992 |
| 6993 insn = mips_fetch_instruction (gdbarch, ISA_MICROMIPS, addr, &status); |
| 6994 if (status) |
| 6995 return 0; |
| 6996 |
| 6997 if (!mustbe32) /* 16-bit instructions. */ |
| 6998 return (micromips_op (insn) == 0x11 |
| 6999 /* POOL16C: bits 010001 */ |
| 7000 && (b5s5_op (insn) == 0xc |
| 7001 /* JR16: bits 010001 01100 */ |
| 7002 || (b5s5_op (insn) & 0x1e) == 0xe)) |
| 7003 /* JALR16, JALRS16: bits 010001 0111x */ |
| 7004 || (micromips_op (insn) & 0x37) == 0x23 |
| 7005 /* BEQZ16, BNEZ16: bits 10x011 */ |
| 7006 || micromips_op (insn) == 0x33; |
| 7007 /* B16: bits 110011 */ |
| 7008 |
| 7009 /* 32-bit instructions. */ |
| 7010 if (micromips_op (insn) == 0x0) |
| 7011 /* POOL32A: bits 000000 */ |
| 7012 { |
| 7013 insn <<= 16; |
| 7014 insn |= mips_fetch_instruction (gdbarch, ISA_MICROMIPS, addr, &status); |
| 7015 if (status) |
| 7016 return 0; |
| 7017 return b0s6_op (insn) == 0x3c |
| 7018 /* POOL32Axf: bits 000000 ... 111100 */ |
| 7019 && (b6s10_ext (insn) & 0x2bf) == 0x3c; |
| 7020 /* JALR, JALR.HB: 000000 000x111100 111100 */ |
| 7021 /* JALRS, JALRS.HB: 000000 010x111100 111100 */ |
| 7022 } |
| 7023 |
| 7024 return (micromips_op (insn) == 0x10 |
| 7025 /* POOL32I: bits 010000 */ |
| 7026 && ((b5s5_op (insn) & 0x1c) == 0x0 |
| 7027 /* BLTZ, BLTZAL, BGEZ, BGEZAL: 010000 000xx */ |
| 7028 || (b5s5_op (insn) & 0x1d) == 0x4 |
| 7029 /* BLEZ, BGTZ: bits 010000 001x0 */ |
| 7030 || (b5s5_op (insn) & 0x1d) == 0x11 |
| 7031 /* BLTZALS, BGEZALS: bits 010000 100x1 */ |
| 7032 || ((b5s5_op (insn) & 0x1e) == 0x14 |
| 7033 && (insn & 0x3) == 0x0) |
| 7034 /* BC2F, BC2T: bits 010000 1010x xxx00 */ |
| 7035 || (b5s5_op (insn) & 0x1e) == 0x1a |
| 7036 /* BPOSGE64, BPOSGE32: bits 010000 1101x */ |
| 7037 || ((b5s5_op (insn) & 0x1e) == 0x1c |
| 7038 && (insn & 0x3) == 0x0) |
| 7039 /* BC1F, BC1T: bits 010000 1110x xxx00 */ |
| 7040 || ((b5s5_op (insn) & 0x1c) == 0x1c |
| 7041 && (insn & 0x3) == 0x1))) |
| 7042 /* BC1ANY*: bits 010000 111xx xxx01 */ |
| 7043 || (micromips_op (insn) & 0x1f) == 0x1d |
| 7044 /* JALS, JAL: bits x11101 */ |
| 7045 || (micromips_op (insn) & 0x37) == 0x25 |
| 7046 /* BEQ, BNE: bits 10x101 */ |
| 7047 || micromips_op (insn) == 0x35 |
| 7048 /* J: bits 110101 */ |
| 7049 || micromips_op (insn) == 0x3c; |
| 7050 /* JALX: bits 111100 */ |
| 7051 } |
| 7052 |
| 7053 static int |
| 7054 mips16_instruction_has_delay_slot (struct gdbarch *gdbarch, CORE_ADDR addr, |
| 7055 int mustbe32) |
| 7056 { |
| 7057 unsigned short inst; |
| 7058 int status; |
| 7059 |
| 7060 inst = mips_fetch_instruction (gdbarch, ISA_MIPS16, addr, &status); |
| 7061 if (status) |
| 7062 return 0; |
| 7063 |
| 7064 if (!mustbe32) |
| 7065 return (inst & 0xf89f) == 0xe800; /* JR/JALR (16-bit instruction) */ |
| 7066 return (inst & 0xf800) == 0x1800; /* JAL/JALX (32-bit instruction) */ |
| 7067 } |
| 7068 |
| 7069 /* Calculate the starting address of the MIPS memory segment BPADDR is in. |
| 7070 This assumes KSSEG exists. */ |
| 7071 |
| 7072 static CORE_ADDR |
| 7073 mips_segment_boundary (CORE_ADDR bpaddr) |
| 7074 { |
| 7075 CORE_ADDR mask = CORE_ADDR_MAX; |
| 7076 int segsize; |
| 7077 |
| 7078 if (sizeof (CORE_ADDR) == 8) |
| 7079 /* Get the topmost two bits of bpaddr in a 32-bit safe manner (avoid |
| 7080 a compiler warning produced where CORE_ADDR is a 32-bit type even |
| 7081 though in that case this is dead code). */ |
| 7082 switch (bpaddr >> ((sizeof (CORE_ADDR) << 3) - 2) & 3) |
| 7083 { |
| 7084 case 3: |
| 7085 if (bpaddr == (bfd_signed_vma) (int32_t) bpaddr) |
| 7086 segsize = 29; /* 32-bit compatibility segment */ |
| 7087 else |
| 7088 segsize = 62; /* xkseg */ |
| 7089 break; |
| 7090 case 2: /* xkphys */ |
| 7091 segsize = 59; |
| 7092 break; |
| 7093 default: /* xksseg (1), xkuseg/kuseg (0) */ |
| 7094 segsize = 62; |
| 7095 break; |
| 7096 } |
| 7097 else if (bpaddr & 0x80000000) /* kernel segment */ |
| 7098 segsize = 29; |
| 7099 else |
| 7100 segsize = 31; /* user segment */ |
| 7101 mask <<= segsize; |
| 7102 return bpaddr & mask; |
| 7103 } |
| 7104 |
| 7105 /* Move the breakpoint at BPADDR out of any branch delay slot by shifting |
| 7106 it backwards if necessary. Return the address of the new location. */ |
| 7107 |
| 7108 static CORE_ADDR |
| 7109 mips_adjust_breakpoint_address (struct gdbarch *gdbarch, CORE_ADDR bpaddr) |
| 7110 { |
| 7111 CORE_ADDR prev_addr; |
| 7112 CORE_ADDR boundary; |
| 7113 CORE_ADDR func_addr; |
| 7114 |
| 7115 /* If a breakpoint is set on the instruction in a branch delay slot, |
| 7116 GDB gets confused. When the breakpoint is hit, the PC isn't on |
| 7117 the instruction in the branch delay slot, the PC will point to |
| 7118 the branch instruction. Since the PC doesn't match any known |
| 7119 breakpoints, GDB reports a trap exception. |
| 7120 |
| 7121 There are two possible fixes for this problem. |
| 7122 |
| 7123 1) When the breakpoint gets hit, see if the BD bit is set in the |
| 7124 Cause register (which indicates the last exception occurred in a |
| 7125 branch delay slot). If the BD bit is set, fix the PC to point to |
| 7126 the instruction in the branch delay slot. |
| 7127 |
| 7128 2) When the user sets the breakpoint, don't allow him to set the |
| 7129 breakpoint on the instruction in the branch delay slot. Instead |
| 7130 move the breakpoint to the branch instruction (which will have |
| 7131 the same result). |
| 7132 |
| 7133 The problem with the first solution is that if the user then |
| 7134 single-steps the processor, the branch instruction will get |
| 7135 skipped (since GDB thinks the PC is on the instruction in the |
| 7136 branch delay slot). |
| 7137 |
| 7138 So, we'll use the second solution. To do this we need to know if |
| 7139 the instruction we're trying to set the breakpoint on is in the |
| 7140 branch delay slot. */ |
| 7141 |
| 7142 boundary = mips_segment_boundary (bpaddr); |
| 7143 |
| 7144 /* Make sure we don't scan back before the beginning of the current |
| 7145 function, since we may fetch constant data or insns that look like |
| 7146 a jump. Of course we might do that anyway if the compiler has |
| 7147 moved constants inline. :-( */ |
| 7148 if (find_pc_partial_function (bpaddr, NULL, &func_addr, NULL) |
| 7149 && func_addr > boundary && func_addr <= bpaddr) |
| 7150 boundary = func_addr; |
| 7151 |
| 7152 if (mips_pc_is_mips (bpaddr)) |
| 7153 { |
| 7154 if (bpaddr == boundary) |
| 7155 return bpaddr; |
| 7156 |
| 7157 /* If the previous instruction has a branch delay slot, we have |
| 7158 to move the breakpoint to the branch instruction. */ |
| 7159 prev_addr = bpaddr - 4; |
| 7160 if (mips32_instruction_has_delay_slot (gdbarch, prev_addr)) |
| 7161 bpaddr = prev_addr; |
| 7162 } |
| 7163 else |
| 7164 { |
| 7165 int (*instruction_has_delay_slot) (struct gdbarch *, CORE_ADDR, int); |
| 7166 CORE_ADDR addr, jmpaddr; |
| 7167 int i; |
| 7168 |
| 7169 boundary = unmake_compact_addr (boundary); |
| 7170 |
| 7171 /* The only MIPS16 instructions with delay slots are JAL, JALX, |
| 7172 JALR and JR. An absolute JAL/JALX is always 4 bytes long, |
| 7173 so try for that first, then try the 2 byte JALR/JR. |
| 7174 The microMIPS ASE has a whole range of jumps and branches |
| 7175 with delay slots, some of which take 4 bytes and some take |
| 7176 2 bytes, so the idea is the same. |
| 7177 FIXME: We have to assume that bpaddr is not the second half |
| 7178 of an extended instruction. */ |
| 7179 instruction_has_delay_slot = (mips_pc_is_micromips (gdbarch, bpaddr) |
| 7180 ? micromips_instruction_has_delay_slot |
| 7181 : mips16_instruction_has_delay_slot); |
| 7182 |
| 7183 jmpaddr = 0; |
| 7184 addr = bpaddr; |
| 7185 for (i = 1; i < 4; i++) |
| 7186 { |
| 7187 if (unmake_compact_addr (addr) == boundary) |
| 7188 break; |
| 7189 addr -= MIPS_INSN16_SIZE; |
| 7190 if (i == 1 && instruction_has_delay_slot (gdbarch, addr, 0)) |
| 7191 /* Looks like a JR/JALR at [target-1], but it could be |
| 7192 the second word of a previous JAL/JALX, so record it |
| 7193 and check back one more. */ |
| 7194 jmpaddr = addr; |
| 7195 else if (i > 1 && instruction_has_delay_slot (gdbarch, addr, 1)) |
| 7196 { |
| 7197 if (i == 2) |
| 7198 /* Looks like a JAL/JALX at [target-2], but it could also |
| 7199 be the second word of a previous JAL/JALX, record it, |
| 7200 and check back one more. */ |
| 7201 jmpaddr = addr; |
| 7202 else |
| 7203 /* Looks like a JAL/JALX at [target-3], so any previously |
| 7204 recorded JAL/JALX or JR/JALR must be wrong, because: |
| 7205 |
| 7206 >-3: JAL |
| 7207 -2: JAL-ext (can't be JAL/JALX) |
| 7208 -1: bdslot (can't be JR/JALR) |
| 7209 0: target insn |
| 7210 |
| 7211 Of course it could be another JAL-ext which looks |
| 7212 like a JAL, but in that case we'd have broken out |
| 7213 of this loop at [target-2]: |
| 7214 |
| 7215 -4: JAL |
| 7216 >-3: JAL-ext |
| 7217 -2: bdslot (can't be jmp) |
| 7218 -1: JR/JALR |
| 7219 0: target insn */ |
| 7220 jmpaddr = 0; |
| 7221 } |
| 7222 else |
| 7223 { |
| 7224 /* Not a jump instruction: if we're at [target-1] this |
| 7225 could be the second word of a JAL/JALX, so continue; |
| 7226 otherwise we're done. */ |
| 7227 if (i > 1) |
| 7228 break; |
| 7229 } |
| 7230 } |
| 7231 |
| 7232 if (jmpaddr) |
| 7233 bpaddr = jmpaddr; |
| 7234 } |
| 7235 |
| 7236 return bpaddr; |
| 7237 } |
| 7238 |
| 7239 /* Return non-zero if SUFFIX is one of the numeric suffixes used for MIPS16 |
| 7240 call stubs, one of 1, 2, 5, 6, 9, 10, or, if ZERO is non-zero, also 0. */ |
| 7241 |
| 7242 static int |
| 7243 mips_is_stub_suffix (const char *suffix, int zero) |
| 7244 { |
| 7245 switch (suffix[0]) |
| 7246 { |
| 7247 case '0': |
| 7248 return zero && suffix[1] == '\0'; |
| 7249 case '1': |
| 7250 return suffix[1] == '\0' || (suffix[1] == '0' && suffix[2] == '\0'); |
| 7251 case '2': |
| 7252 case '5': |
| 7253 case '6': |
| 7254 case '9': |
| 7255 return suffix[1] == '\0'; |
| 7256 default: |
| 7257 return 0; |
| 7258 } |
| 7259 } |
| 7260 |
| 7261 /* Return non-zero if MODE is one of the mode infixes used for MIPS16 |
| 7262 call stubs, one of sf, df, sc, or dc. */ |
| 7263 |
| 7264 static int |
| 7265 mips_is_stub_mode (const char *mode) |
| 7266 { |
| 7267 return ((mode[0] == 's' || mode[0] == 'd') |
| 7268 && (mode[1] == 'f' || mode[1] == 'c')); |
| 7269 } |
| 7270 |
| 7271 /* Code at PC is a compiler-generated stub. Such a stub for a function |
| 7272 bar might have a name like __fn_stub_bar, and might look like this: |
| 7273 |
| 7274 mfc1 $4, $f13 |
| 7275 mfc1 $5, $f12 |
| 7276 mfc1 $6, $f15 |
| 7277 mfc1 $7, $f14 |
| 7278 |
| 7279 followed by (or interspersed with): |
| 7280 |
| 7281 j bar |
| 7282 |
| 7283 or: |
| 7284 |
| 7285 lui $25, %hi(bar) |
| 7286 addiu $25, $25, %lo(bar) |
| 7287 jr $25 |
| 7288 |
| 7289 ($1 may be used in old code; for robustness we accept any register) |
| 7290 or, in PIC code: |
| 7291 |
| 7292 lui $28, %hi(_gp_disp) |
| 7293 addiu $28, $28, %lo(_gp_disp) |
| 7294 addu $28, $28, $25 |
| 7295 lw $25, %got(bar) |
| 7296 addiu $25, $25, %lo(bar) |
| 7297 jr $25 |
| 7298 |
| 7299 In the case of a __call_stub_bar stub, the sequence to set up |
| 7300 arguments might look like this: |
| 7301 |
| 7302 mtc1 $4, $f13 |
| 7303 mtc1 $5, $f12 |
| 7304 mtc1 $6, $f15 |
| 7305 mtc1 $7, $f14 |
| 7306 |
| 7307 followed by (or interspersed with) one of the jump sequences above. |
| 7308 |
| 7309 In the case of a __call_stub_fp_bar stub, JAL or JALR is used instead |
| 7310 of J or JR, respectively, followed by: |
| 7311 |
| 7312 mfc1 $2, $f0 |
| 7313 mfc1 $3, $f1 |
| 7314 jr $18 |
| 7315 |
| 7316 We are at the beginning of the stub here, and scan down and extract |
| 7317 the target address from the jump immediate instruction or, if a jump |
| 7318 register instruction is used, from the register referred. Return |
| 7319 the value of PC calculated or 0 if inconclusive. |
| 7320 |
| 7321 The limit on the search is arbitrarily set to 20 instructions. FIXME. */ |
| 7322 |
| 7323 static CORE_ADDR |
| 7324 mips_get_mips16_fn_stub_pc (struct frame_info *frame, CORE_ADDR pc) |
| 7325 { |
| 7326 struct gdbarch *gdbarch = get_frame_arch (frame); |
| 7327 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
| 7328 int addrreg = MIPS_ZERO_REGNUM; |
| 7329 CORE_ADDR start_pc = pc; |
| 7330 CORE_ADDR target_pc = 0; |
| 7331 CORE_ADDR addr = 0; |
| 7332 CORE_ADDR gp = 0; |
| 7333 int status = 0; |
| 7334 int i; |
| 7335 |
| 7336 for (i = 0; |
| 7337 status == 0 && target_pc == 0 && i < 20; |
| 7338 i++, pc += MIPS_INSN32_SIZE) |
| 7339 { |
| 7340 ULONGEST inst = mips_fetch_instruction (gdbarch, ISA_MIPS, pc, NULL); |
| 7341 CORE_ADDR imm; |
| 7342 int rt; |
| 7343 int rs; |
| 7344 int rd; |
| 7345 |
| 7346 switch (itype_op (inst)) |
| 7347 { |
| 7348 case 0: /* SPECIAL */ |
| 7349 switch (rtype_funct (inst)) |
| 7350 { |
| 7351 case 8: /* JR */ |
| 7352 case 9: /* JALR */ |
| 7353 rs = rtype_rs (inst); |
| 7354 if (rs == MIPS_GP_REGNUM) |
| 7355 target_pc = gp; /* Hmm... */ |
| 7356 else if (rs == addrreg) |
| 7357 target_pc = addr; |
| 7358 break; |
| 7359 |
| 7360 case 0x21: /* ADDU */ |
| 7361 rt = rtype_rt (inst); |
| 7362 rs = rtype_rs (inst); |
| 7363 rd = rtype_rd (inst); |
| 7364 if (rd == MIPS_GP_REGNUM |
| 7365 && ((rs == MIPS_GP_REGNUM && rt == MIPS_T9_REGNUM) |
| 7366 || (rs == MIPS_T9_REGNUM && rt == MIPS_GP_REGNUM))) |
| 7367 gp += start_pc; |
| 7368 break; |
| 7369 } |
| 7370 break; |
| 7371 |
| 7372 case 2: /* J */ |
| 7373 case 3: /* JAL */ |
| 7374 target_pc = jtype_target (inst) << 2; |
| 7375 target_pc += ((pc + 4) & ~(CORE_ADDR) 0x0fffffff); |
| 7376 break; |
| 7377 |
| 7378 case 9: /* ADDIU */ |
| 7379 rt = itype_rt (inst); |
| 7380 rs = itype_rs (inst); |
| 7381 if (rt == rs) |
| 7382 { |
| 7383 imm = (itype_immediate (inst) ^ 0x8000) - 0x8000; |
| 7384 if (rt == MIPS_GP_REGNUM) |
| 7385 gp += imm; |
| 7386 else if (rt == addrreg) |
| 7387 addr += imm; |
| 7388 } |
| 7389 break; |
| 7390 |
| 7391 case 0xf: /* LUI */ |
| 7392 rt = itype_rt (inst); |
| 7393 imm = ((itype_immediate (inst) ^ 0x8000) - 0x8000) << 16; |
| 7394 if (rt == MIPS_GP_REGNUM) |
| 7395 gp = imm; |
| 7396 else if (rt != MIPS_ZERO_REGNUM) |
| 7397 { |
| 7398 addrreg = rt; |
| 7399 addr = imm; |
| 7400 } |
| 7401 break; |
| 7402 |
| 7403 case 0x23: /* LW */ |
| 7404 rt = itype_rt (inst); |
| 7405 rs = itype_rs (inst); |
| 7406 imm = (itype_immediate (inst) ^ 0x8000) - 0x8000; |
| 7407 if (gp != 0 && rs == MIPS_GP_REGNUM) |
| 7408 { |
| 7409 gdb_byte buf[4]; |
| 7410 |
| 7411 memset (buf, 0, sizeof (buf)); |
| 7412 status = target_read_memory (gp + imm, buf, sizeof (buf)); |
| 7413 addrreg = rt; |
| 7414 addr = extract_signed_integer (buf, sizeof (buf), byte_order); |
| 7415 } |
| 7416 break; |
| 7417 } |
| 7418 } |
| 7419 |
| 7420 return target_pc; |
| 7421 } |
| 7422 |
| 7423 /* If PC is in a MIPS16 call or return stub, return the address of the |
| 7424 target PC, which is either the callee or the caller. There are several |
5298 cases which must be handled: | 7425 cases which must be handled: |
5299 | 7426 |
5300 * If the PC is in __mips16_ret_{d,s}f, this is a return stub and the | 7427 * If the PC is in __mips16_ret_{d,s}{f,c}, this is a return stub |
5301 target PC is in $31 ($ra). | 7428 and the target PC is in $31 ($ra). |
5302 * If the PC is in __mips16_call_stub_{1..10}, this is a call stub | 7429 * If the PC is in __mips16_call_stub_{1..10}, this is a call stub |
5303 and the target PC is in $2. | 7430 and the target PC is in $2. |
5304 * If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e. | 7431 * If the PC at the start of __mips16_call_stub_{s,d}{f,c}_{0..10}, |
5305 before the jal instruction, this is effectively a call stub | 7432 i.e. before the JALR instruction, this is effectively a call stub |
5306 and the target PC is in $2. Otherwise this is effectively | 7433 and the target PC is in $2. Otherwise this is effectively |
5307 a return stub and the target PC is in $18. | 7434 a return stub and the target PC is in $18. |
5308 | 7435 * If the PC is at the start of __call_stub_fp_*, i.e. before the |
5309 See the source code for the stubs in gcc/config/mips/mips16.S for | 7436 JAL or JALR instruction, this is effectively a call stub and the |
| 7437 target PC is buried in the instruction stream. Otherwise this |
| 7438 is effectively a return stub and the target PC is in $18. |
| 7439 * If the PC is in __call_stub_* or in __fn_stub_*, this is a call |
| 7440 stub and the target PC is buried in the instruction stream. |
| 7441 |
| 7442 See the source code for the stubs in gcc/config/mips/mips16.S, or the |
| 7443 stub builder in gcc/config/mips/mips.c (mips16_build_call_stub) for the |
5310 gory details. */ | 7444 gory details. */ |
5311 | 7445 |
5312 static CORE_ADDR | 7446 static CORE_ADDR |
5313 mips_skip_mips16_trampoline_code (struct frame_info *frame, CORE_ADDR pc) | 7447 mips_skip_mips16_trampoline_code (struct frame_info *frame, CORE_ADDR pc) |
5314 { | 7448 { |
5315 struct gdbarch *gdbarch = get_frame_arch (frame); | 7449 struct gdbarch *gdbarch = get_frame_arch (frame); |
5316 char *name; | |
5317 CORE_ADDR start_addr; | 7450 CORE_ADDR start_addr; |
| 7451 const char *name; |
| 7452 size_t prefixlen; |
5318 | 7453 |
5319 /* Find the starting address and name of the function containing the PC. */ | 7454 /* Find the starting address and name of the function containing the PC. */ |
5320 if (find_pc_partial_function (pc, &name, &start_addr, NULL) == 0) | 7455 if (find_pc_partial_function (pc, &name, &start_addr, NULL) == 0) |
5321 return 0; | 7456 return 0; |
5322 | 7457 |
5323 /* If the PC is in __mips16_ret_{d,s}f, this is a return stub and the | 7458 /* If the PC is in __mips16_ret_{d,s}{f,c}, this is a return stub |
5324 target PC is in $31 ($ra). */ | 7459 and the target PC is in $31 ($ra). */ |
5325 if (strcmp (name, "__mips16_ret_sf") == 0 | 7460 prefixlen = strlen (mips_str_mips16_ret_stub); |
5326 || strcmp (name, "__mips16_ret_df") == 0) | 7461 if (strncmp (name, mips_str_mips16_ret_stub, prefixlen) == 0 |
5327 return get_frame_register_signed (frame, MIPS_RA_REGNUM); | 7462 && mips_is_stub_mode (name + prefixlen) |
5328 | 7463 && name[prefixlen + 2] == '\0') |
5329 if (strncmp (name, "__mips16_call_stub_", 19) == 0) | 7464 return get_frame_register_signed |
| 7465 » (frame, gdbarch_num_regs (gdbarch) + MIPS_RA_REGNUM); |
| 7466 |
| 7467 /* If the PC is in __mips16_call_stub_*, this is one of the call |
| 7468 call/return stubs. */ |
| 7469 prefixlen = strlen (mips_str_mips16_call_stub); |
| 7470 if (strncmp (name, mips_str_mips16_call_stub, prefixlen) == 0) |
5330 { | 7471 { |
5331 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub | 7472 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub |
5332 and the target PC is in $2. */ | 7473 and the target PC is in $2. */ |
5333 if (name[19] >= '0' && name[19] <= '9') | 7474 if (mips_is_stub_suffix (name + prefixlen, 0)) |
5334 » return get_frame_register_signed (frame, 2); | 7475 » return get_frame_register_signed |
5335 | 7476 » » (frame, gdbarch_num_regs (gdbarch) + MIPS_V0_REGNUM); |
5336 /* If the PC at the start of __mips16_call_stub_{s,d}f_{0..10}, i.e. | 7477 |
5337 before the jal instruction, this is effectively a call stub | 7478 /* If the PC at the start of __mips16_call_stub_{s,d}{f,c}_{0..10}, |
| 7479 i.e. before the JALR instruction, this is effectively a call stub |
5338 and the target PC is in $2. Otherwise this is effectively | 7480 and the target PC is in $2. Otherwise this is effectively |
5339 a return stub and the target PC is in $18. */ | 7481 a return stub and the target PC is in $18. */ |
5340 else if (name[19] == 's' || name[19] == 'd') | 7482 else if (mips_is_stub_mode (name + prefixlen) |
| 7483 » && name[prefixlen + 2] == '_' |
| 7484 » && mips_is_stub_suffix (name + prefixlen + 3, 0)) |
5341 { | 7485 { |
5342 if (pc == start_addr) | 7486 if (pc == start_addr) |
5343 » { | 7487 » /* This is the 'call' part of a call stub. The return |
5344 » /* Check if the target of the stub is a compiler-generated | 7488 » address is in $2. */ |
5345 » stub. Such a stub for a function bar might have a name | 7489 » return get_frame_register_signed |
5346 » like __fn_stub_bar, and might look like this: | 7490 » » (frame, gdbarch_num_regs (gdbarch) + MIPS_V0_REGNUM); |
5347 » mfc1 $4,$f13 | |
5348 » mfc1 $5,$f12 | |
5349 » mfc1 $6,$f15 | |
5350 » mfc1 $7,$f14 | |
5351 » la $1,bar (becomes a lui/addiu pair) | |
5352 » jr $1 | |
5353 » So scan down to the lui/addi and extract the target | |
5354 » address from those two instructions. */ | |
5355 | |
5356 » CORE_ADDR target_pc = get_frame_register_signed (frame, 2); | |
5357 » int i; | |
5358 | |
5359 » /* See if the name of the target function is __fn_stub_*. */ | |
5360 » if (find_pc_partial_function (target_pc, &name, NULL, NULL) == | |
5361 » » 0) | |
5362 » » return target_pc; | |
5363 » if (strncmp (name, "__fn_stub_", 10) != 0 | |
5364 » » && strcmp (name, "etext") != 0 | |
5365 » » && strcmp (name, "_etext") != 0) | |
5366 » » return target_pc; | |
5367 | |
5368 » /* Scan through this _fn_stub_ code for the lui/addiu pair. | |
5369 » The limit on the search is arbitrarily set to 20 | |
5370 » instructions. FIXME. */ | |
5371 » for (i = 0, pc = 0; i < 20; i++, target_pc += MIPS_INSN32_SIZE) | |
5372 » » { | |
5373 » » ULONGEST inst = mips_fetch_instruction (gdbarch, target_pc); | |
5374 » » CORE_ADDR addr = inst; | |
5375 | |
5376 » » if ((inst & 0xffff0000) == 0x3c010000)» /* lui $at */ | |
5377 » » pc = (((addr & 0xffff) ^ 0x8000) - 0x8000) << 16; | |
5378 » » » » » » » » /* high word */ | |
5379 » » else if ((inst & 0xffff0000) == 0x24210000)» /* addiu $at */ | |
5380 » » return pc + ((addr & 0xffff) ^ 0x8000) - 0x8000; | |
5381 » » » » » » » » /* low word */ | |
5382 » » } | |
5383 | |
5384 » /* Couldn't find the lui/addui pair, so return stub address. */ | |
5385 » return target_pc; | |
5386 » } | |
5387 else | 7491 else |
5388 /* This is the 'return' part of a call stub. The return | 7492 /* This is the 'return' part of a call stub. The return |
5389 » address is in $r18. */ | 7493 » address is in $18. */ |
5390 » return get_frame_register_signed (frame, 18); | 7494 » return get_frame_register_signed |
| 7495 » » (frame, gdbarch_num_regs (gdbarch) + MIPS_S2_REGNUM); |
5391 } | 7496 } |
5392 } | 7497 else |
5393 return 0;» » » /* not a stub */ | 7498 » return 0;» » /* Not a stub. */ |
| 7499 } |
| 7500 |
| 7501 /* If the PC is in __call_stub_* or __fn_stub*, this is one of the |
| 7502 compiler-generated call or call/return stubs. */ |
| 7503 if (strncmp (name, mips_str_fn_stub, strlen (mips_str_fn_stub)) == 0 |
| 7504 || strncmp (name, mips_str_call_stub, strlen (mips_str_call_stub)) == 0) |
| 7505 { |
| 7506 if (pc == start_addr) |
| 7507 » /* This is the 'call' part of a call stub. Call this helper |
| 7508 » to scan through this code for interesting instructions |
| 7509 » and determine the final PC. */ |
| 7510 » return mips_get_mips16_fn_stub_pc (frame, pc); |
| 7511 else |
| 7512 » /* This is the 'return' part of a call stub. The return address |
| 7513 » is in $18. */ |
| 7514 » return get_frame_register_signed |
| 7515 » » (frame, gdbarch_num_regs (gdbarch) + MIPS_S2_REGNUM); |
| 7516 } |
| 7517 |
| 7518 return 0;» » » /* Not a stub. */ |
| 7519 } |
| 7520 |
| 7521 /* Return non-zero if the PC is inside a return thunk (aka stub or trampoline). |
| 7522 This implements the IN_SOLIB_RETURN_TRAMPOLINE macro. */ |
| 7523 |
| 7524 static int |
| 7525 mips_in_return_stub (struct gdbarch *gdbarch, CORE_ADDR pc, const char *name) |
| 7526 { |
| 7527 CORE_ADDR start_addr; |
| 7528 size_t prefixlen; |
| 7529 |
| 7530 /* Find the starting address of the function containing the PC. */ |
| 7531 if (find_pc_partial_function (pc, NULL, &start_addr, NULL) == 0) |
| 7532 return 0; |
| 7533 |
| 7534 /* If the PC is in __mips16_call_stub_{s,d}{f,c}_{0..10} but not at |
| 7535 the start, i.e. after the JALR instruction, this is effectively |
| 7536 a return stub. */ |
| 7537 prefixlen = strlen (mips_str_mips16_call_stub); |
| 7538 if (pc != start_addr |
| 7539 && strncmp (name, mips_str_mips16_call_stub, prefixlen) == 0 |
| 7540 && mips_is_stub_mode (name + prefixlen) |
| 7541 && name[prefixlen + 2] == '_' |
| 7542 && mips_is_stub_suffix (name + prefixlen + 3, 1)) |
| 7543 return 1; |
| 7544 |
| 7545 /* If the PC is in __call_stub_fp_* but not at the start, i.e. after |
| 7546 the JAL or JALR instruction, this is effectively a return stub. */ |
| 7547 prefixlen = strlen (mips_str_call_fp_stub); |
| 7548 if (pc != start_addr |
| 7549 && strncmp (name, mips_str_call_fp_stub, prefixlen) == 0) |
| 7550 return 1; |
| 7551 |
| 7552 /* Consume the .pic. prefix of any PIC stub, this function must return |
| 7553 true when the PC is in a PIC stub of a __mips16_ret_{d,s}{f,c} stub |
| 7554 or the call stub path will trigger in handle_inferior_event causing |
| 7555 it to go astray. */ |
| 7556 prefixlen = strlen (mips_str_pic); |
| 7557 if (strncmp (name, mips_str_pic, prefixlen) == 0) |
| 7558 name += prefixlen; |
| 7559 |
| 7560 /* If the PC is in __mips16_ret_{d,s}{f,c}, this is a return stub. */ |
| 7561 prefixlen = strlen (mips_str_mips16_ret_stub); |
| 7562 if (strncmp (name, mips_str_mips16_ret_stub, prefixlen) == 0 |
| 7563 && mips_is_stub_mode (name + prefixlen) |
| 7564 && name[prefixlen + 2] == '\0') |
| 7565 return 1; |
| 7566 |
| 7567 return 0;» » » /* Not a stub. */ |
5394 } | 7568 } |
5395 | 7569 |
5396 /* If the current PC is the start of a non-PIC-to-PIC stub, return the | 7570 /* If the current PC is the start of a non-PIC-to-PIC stub, return the |
5397 PC of the stub target. The stub just loads $t9 and jumps to it, | 7571 PC of the stub target. The stub just loads $t9 and jumps to it, |
5398 so that $t9 has the correct value at function entry. */ | 7572 so that $t9 has the correct value at function entry. */ |
5399 | 7573 |
5400 static CORE_ADDR | 7574 static CORE_ADDR |
5401 mips_skip_pic_trampoline_code (struct frame_info *frame, CORE_ADDR pc) | 7575 mips_skip_pic_trampoline_code (struct frame_info *frame, CORE_ADDR pc) |
5402 { | 7576 { |
5403 struct gdbarch *gdbarch = get_frame_arch (frame); | 7577 struct gdbarch *gdbarch = get_frame_arch (frame); |
(...skipping 31 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... |
5435 j target | 7609 j target |
5436 addiu t9, t9, %lo(target) | 7610 addiu t9, t9, %lo(target) |
5437 nop | 7611 nop |
5438 | 7612 |
5439 This works even for N64, since stubs are only generated with | 7613 This works even for N64, since stubs are only generated with |
5440 -msym32. */ | 7614 -msym32. */ |
5441 if ((stub_words[0] & 0xffff0000U) == 0x3c190000 | 7615 if ((stub_words[0] & 0xffff0000U) == 0x3c190000 |
5442 && (stub_words[1] & 0xfc000000U) == 0x08000000 | 7616 && (stub_words[1] & 0xfc000000U) == 0x08000000 |
5443 && (stub_words[2] & 0xffff0000U) == 0x27390000 | 7617 && (stub_words[2] & 0xffff0000U) == 0x27390000 |
5444 && stub_words[3] == 0x00000000) | 7618 && stub_words[3] == 0x00000000) |
5445 » return (((stub_words[0] & 0x0000ffff) << 16) | 7619 » return ((((stub_words[0] & 0x0000ffff) << 16) |
5446 » » + (stub_words[2] & 0x0000ffff)); | 7620 » » + (stub_words[2] & 0x0000ffff)) ^ 0x8000) - 0x8000; |
5447 } | 7621 } |
5448 | 7622 |
5449 /* Not a recognized stub. */ | 7623 /* Not a recognized stub. */ |
5450 return 0; | 7624 return 0; |
5451 } | 7625 } |
5452 | 7626 |
5453 static CORE_ADDR | 7627 static CORE_ADDR |
5454 mips_skip_trampoline_code (struct frame_info *frame, CORE_ADDR pc) | 7628 mips_skip_trampoline_code (struct frame_info *frame, CORE_ADDR pc) |
5455 { | 7629 { |
| 7630 CORE_ADDR requested_pc = pc; |
5456 CORE_ADDR target_pc; | 7631 CORE_ADDR target_pc; |
| 7632 CORE_ADDR new_pc; |
5457 | 7633 |
5458 target_pc = mips_skip_mips16_trampoline_code (frame, pc); | 7634 do |
5459 if (target_pc) | 7635 { |
5460 return target_pc; | 7636 target_pc = pc; |
5461 | 7637 |
5462 target_pc = find_solib_trampoline_target (frame, pc); | 7638 new_pc = mips_skip_mips16_trampoline_code (frame, pc); |
5463 if (target_pc) | 7639 if (new_pc) |
5464 return target_pc; | 7640 » { |
| 7641 » pc = new_pc; |
| 7642 » if (is_compact_addr (pc)) |
| 7643 » pc = unmake_compact_addr (pc); |
| 7644 » } |
5465 | 7645 |
5466 target_pc = mips_skip_pic_trampoline_code (frame, pc); | 7646 new_pc = find_solib_trampoline_target (frame, pc); |
5467 if (target_pc) | 7647 if (new_pc) |
5468 return target_pc; | 7648 » { |
| 7649 » pc = new_pc; |
| 7650 » if (is_compact_addr (pc)) |
| 7651 » pc = unmake_compact_addr (pc); |
| 7652 » } |
5469 | 7653 |
5470 return 0; | 7654 new_pc = mips_skip_pic_trampoline_code (frame, pc); |
| 7655 if (new_pc) |
| 7656 » { |
| 7657 » pc = new_pc; |
| 7658 » if (is_compact_addr (pc)) |
| 7659 » pc = unmake_compact_addr (pc); |
| 7660 » } |
| 7661 } |
| 7662 while (pc != target_pc); |
| 7663 |
| 7664 return pc != requested_pc ? pc : 0; |
5471 } | 7665 } |
5472 | 7666 |
5473 /* Convert a dbx stab register number (from `r' declaration) to a GDB | 7667 /* Convert a dbx stab register number (from `r' declaration) to a GDB |
5474 [1 * gdbarch_num_regs .. 2 * gdbarch_num_regs) REGNUM. */ | 7668 [1 * gdbarch_num_regs .. 2 * gdbarch_num_regs) REGNUM. */ |
5475 | 7669 |
5476 static int | 7670 static int |
5477 mips_stab_reg_to_regnum (struct gdbarch *gdbarch, int num) | 7671 mips_stab_reg_to_regnum (struct gdbarch *gdbarch, int num) |
5478 { | 7672 { |
5479 int regnum; | 7673 int regnum; |
5480 if (num >= 0 && num < 32) | 7674 if (num >= 0 && num < 32) |
5481 regnum = num; | 7675 regnum = num; |
5482 else if (num >= 38 && num < 70) | 7676 else if (num >= 38 && num < 70) |
5483 regnum = num + mips_regnum (gdbarch)->fp0 - 38; | 7677 regnum = num + mips_regnum (gdbarch)->fp0 - 38; |
5484 else if (num == 70) | 7678 else if (num == 70) |
5485 regnum = mips_regnum (gdbarch)->hi; | 7679 regnum = mips_regnum (gdbarch)->hi; |
5486 else if (num == 71) | 7680 else if (num == 71) |
5487 regnum = mips_regnum (gdbarch)->lo; | 7681 regnum = mips_regnum (gdbarch)->lo; |
| 7682 else if (mips_regnum (gdbarch)->dspacc != -1 && num >= 72 && num < 78) |
| 7683 regnum = num + mips_regnum (gdbarch)->dspacc - 72; |
5488 else | 7684 else |
5489 /* This will hopefully (eventually) provoke a warning. Should | 7685 /* This will hopefully (eventually) provoke a warning. Should |
5490 we be calling complaint() here? */ | 7686 we be calling complaint() here? */ |
5491 return gdbarch_num_regs (gdbarch) + gdbarch_num_pseudo_regs (gdbarch); | 7687 return gdbarch_num_regs (gdbarch) + gdbarch_num_pseudo_regs (gdbarch); |
5492 return gdbarch_num_regs (gdbarch) + regnum; | 7688 return gdbarch_num_regs (gdbarch) + regnum; |
5493 } | 7689 } |
5494 | 7690 |
5495 | 7691 |
5496 /* Convert a dwarf, dwarf2, or ecoff register number to a GDB [1 * | 7692 /* Convert a dwarf, dwarf2, or ecoff register number to a GDB [1 * |
5497 gdbarch_num_regs .. 2 * gdbarch_num_regs) REGNUM. */ | 7693 gdbarch_num_regs .. 2 * gdbarch_num_regs) REGNUM. */ |
5498 | 7694 |
5499 static int | 7695 static int |
5500 mips_dwarf_dwarf2_ecoff_reg_to_regnum (struct gdbarch *gdbarch, int num) | 7696 mips_dwarf_dwarf2_ecoff_reg_to_regnum (struct gdbarch *gdbarch, int num) |
5501 { | 7697 { |
5502 int regnum; | 7698 int regnum; |
5503 if (num >= 0 && num < 32) | 7699 if (num >= 0 && num < 32) |
5504 regnum = num; | 7700 regnum = num; |
5505 else if (num >= 32 && num < 64) | 7701 else if (num >= 32 && num < 64) |
5506 regnum = num + mips_regnum (gdbarch)->fp0 - 32; | 7702 regnum = num + mips_regnum (gdbarch)->fp0 - 32; |
5507 else if (num == 64) | 7703 else if (num == 64) |
5508 regnum = mips_regnum (gdbarch)->hi; | 7704 regnum = mips_regnum (gdbarch)->hi; |
5509 else if (num == 65) | 7705 else if (num == 65) |
5510 regnum = mips_regnum (gdbarch)->lo; | 7706 regnum = mips_regnum (gdbarch)->lo; |
| 7707 else if (mips_regnum (gdbarch)->dspacc != -1 && num >= 66 && num < 72) |
| 7708 regnum = num + mips_regnum (gdbarch)->dspacc - 66; |
5511 else | 7709 else |
5512 /* This will hopefully (eventually) provoke a warning. Should we | 7710 /* This will hopefully (eventually) provoke a warning. Should we |
5513 be calling complaint() here? */ | 7711 be calling complaint() here? */ |
5514 return gdbarch_num_regs (gdbarch) + gdbarch_num_pseudo_regs (gdbarch); | 7712 return gdbarch_num_regs (gdbarch) + gdbarch_num_pseudo_regs (gdbarch); |
5515 return gdbarch_num_regs (gdbarch) + regnum; | 7713 return gdbarch_num_regs (gdbarch) + regnum; |
5516 } | 7714 } |
5517 | 7715 |
5518 static int | 7716 static int |
5519 mips_register_sim_regno (struct gdbarch *gdbarch, int regnum) | 7717 mips_register_sim_regno (struct gdbarch *gdbarch, int regnum) |
5520 { | 7718 { |
(...skipping 84 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... |
5605 { | 7803 { |
5606 int i; | 7804 int i; |
5607 | 7805 |
5608 for (i = 0; mips_abi_strings[i] != NULL; i++) | 7806 for (i = 0; mips_abi_strings[i] != NULL; i++) |
5609 if (mips_abi_strings[i] == mips_abi_string) | 7807 if (mips_abi_strings[i] == mips_abi_string) |
5610 return (enum mips_abi) i; | 7808 return (enum mips_abi) i; |
5611 | 7809 |
5612 internal_error (__FILE__, __LINE__, _("unknown ABI string")); | 7810 internal_error (__FILE__, __LINE__, _("unknown ABI string")); |
5613 } | 7811 } |
5614 | 7812 |
| 7813 /* Return the default compressed instruction set, either of MIPS16 |
| 7814 or microMIPS, selected when none could have been determined from |
| 7815 the ELF header of the binary being executed (or no binary has been |
| 7816 selected. */ |
| 7817 |
| 7818 static enum mips_isa |
| 7819 global_mips_compression (void) |
| 7820 { |
| 7821 int i; |
| 7822 |
| 7823 for (i = 0; mips_compression_strings[i] != NULL; i++) |
| 7824 if (mips_compression_strings[i] == mips_compression_string) |
| 7825 return (enum mips_isa) i; |
| 7826 |
| 7827 internal_error (__FILE__, __LINE__, _("unknown compressed ISA string")); |
| 7828 } |
| 7829 |
5615 static void | 7830 static void |
5616 mips_register_g_packet_guesses (struct gdbarch *gdbarch) | 7831 mips_register_g_packet_guesses (struct gdbarch *gdbarch) |
5617 { | 7832 { |
5618 /* If the size matches the set of 32-bit or 64-bit integer registers, | 7833 /* If the size matches the set of 32-bit or 64-bit integer registers, |
5619 assume that's what we've got. */ | 7834 assume that's what we've got. */ |
5620 register_remote_g_packet_guess (gdbarch, 38 * 4, mips_tdesc_gp32); | 7835 register_remote_g_packet_guess (gdbarch, 38 * 4, mips_tdesc_gp32); |
5621 register_remote_g_packet_guess (gdbarch, 38 * 8, mips_tdesc_gp64); | 7836 register_remote_g_packet_guess (gdbarch, 38 * 8, mips_tdesc_gp64); |
5622 | 7837 |
5623 /* If the size matches the full set of registers GDB traditionally | 7838 /* If the size matches the full set of registers GDB traditionally |
5624 knows about, including floating point, for either 32-bit or | 7839 knows about, including floating point, for either 32-bit or |
(...skipping 15 matching lines...) Expand all Loading... |
5640 mips_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) | 7855 mips_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) |
5641 { | 7856 { |
5642 struct gdbarch *gdbarch; | 7857 struct gdbarch *gdbarch; |
5643 struct gdbarch_tdep *tdep; | 7858 struct gdbarch_tdep *tdep; |
5644 int elf_flags; | 7859 int elf_flags; |
5645 enum mips_abi mips_abi, found_abi, wanted_abi; | 7860 enum mips_abi mips_abi, found_abi, wanted_abi; |
5646 int i, num_regs; | 7861 int i, num_regs; |
5647 enum mips_fpu_type fpu_type; | 7862 enum mips_fpu_type fpu_type; |
5648 struct tdesc_arch_data *tdesc_data = NULL; | 7863 struct tdesc_arch_data *tdesc_data = NULL; |
5649 int elf_fpu_type = 0; | 7864 int elf_fpu_type = 0; |
| 7865 const char **reg_names; |
| 7866 struct mips_regnum mips_regnum, *regnum; |
| 7867 enum mips_isa mips_isa; |
| 7868 int dspacc; |
| 7869 int dspctl; |
| 7870 |
| 7871 /* Fill in the OS dependent register numbers and names. */ |
| 7872 if (info.osabi == GDB_OSABI_IRIX) |
| 7873 { |
| 7874 mips_regnum.fp0 = 32; |
| 7875 mips_regnum.pc = 64; |
| 7876 mips_regnum.cause = 65; |
| 7877 mips_regnum.badvaddr = 66; |
| 7878 mips_regnum.hi = 67; |
| 7879 mips_regnum.lo = 68; |
| 7880 mips_regnum.fp_control_status = 69; |
| 7881 mips_regnum.fp_implementation_revision = 70; |
| 7882 mips_regnum.dspacc = dspacc = -1; |
| 7883 mips_regnum.dspctl = dspctl = -1; |
| 7884 num_regs = 71; |
| 7885 reg_names = mips_irix_reg_names; |
| 7886 } |
| 7887 else if (info.osabi == GDB_OSABI_LINUX) |
| 7888 { |
| 7889 mips_regnum.fp0 = 38; |
| 7890 mips_regnum.pc = 37; |
| 7891 mips_regnum.cause = 36; |
| 7892 mips_regnum.badvaddr = 35; |
| 7893 mips_regnum.hi = 34; |
| 7894 mips_regnum.lo = 33; |
| 7895 mips_regnum.fp_control_status = 70; |
| 7896 mips_regnum.fp_implementation_revision = 71; |
| 7897 mips_regnum.dspacc = -1; |
| 7898 mips_regnum.dspctl = -1; |
| 7899 dspacc = 72; |
| 7900 dspctl = 78; |
| 7901 num_regs = 79; |
| 7902 reg_names = mips_linux_reg_names; |
| 7903 } |
| 7904 else |
| 7905 { |
| 7906 mips_regnum.lo = MIPS_EMBED_LO_REGNUM; |
| 7907 mips_regnum.hi = MIPS_EMBED_HI_REGNUM; |
| 7908 mips_regnum.badvaddr = MIPS_EMBED_BADVADDR_REGNUM; |
| 7909 mips_regnum.cause = MIPS_EMBED_CAUSE_REGNUM; |
| 7910 mips_regnum.pc = MIPS_EMBED_PC_REGNUM; |
| 7911 mips_regnum.fp0 = MIPS_EMBED_FP0_REGNUM; |
| 7912 mips_regnum.fp_control_status = 70; |
| 7913 mips_regnum.fp_implementation_revision = 71; |
| 7914 mips_regnum.dspacc = dspacc = -1; |
| 7915 mips_regnum.dspctl = dspctl = -1; |
| 7916 num_regs = MIPS_LAST_EMBED_REGNUM + 1; |
| 7917 if (info.bfd_arch_info != NULL |
| 7918 && info.bfd_arch_info->mach == bfd_mach_mips3900) |
| 7919 reg_names = mips_tx39_reg_names; |
| 7920 else |
| 7921 reg_names = mips_generic_reg_names; |
| 7922 } |
5650 | 7923 |
5651 /* Check any target description for validity. */ | 7924 /* Check any target description for validity. */ |
5652 if (tdesc_has_registers (info.target_desc)) | 7925 if (tdesc_has_registers (info.target_desc)) |
5653 { | 7926 { |
5654 static const char *const mips_gprs[] = { | 7927 static const char *const mips_gprs[] = { |
5655 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", | 7928 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", |
5656 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | 7929 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", |
5657 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", | 7930 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", |
5658 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31" | 7931 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31" |
5659 }; | 7932 }; |
(...skipping 14 matching lines...) Expand all Loading... |
5674 | 7947 |
5675 tdesc_data = tdesc_data_alloc (); | 7948 tdesc_data = tdesc_data_alloc (); |
5676 | 7949 |
5677 valid_p = 1; | 7950 valid_p = 1; |
5678 for (i = MIPS_ZERO_REGNUM; i <= MIPS_RA_REGNUM; i++) | 7951 for (i = MIPS_ZERO_REGNUM; i <= MIPS_RA_REGNUM; i++) |
5679 valid_p &= tdesc_numbered_register (feature, tdesc_data, i, | 7952 valid_p &= tdesc_numbered_register (feature, tdesc_data, i, |
5680 mips_gprs[i]); | 7953 mips_gprs[i]); |
5681 | 7954 |
5682 | 7955 |
5683 valid_p &= tdesc_numbered_register (feature, tdesc_data, | 7956 valid_p &= tdesc_numbered_register (feature, tdesc_data, |
5684 » » » » » MIPS_EMBED_LO_REGNUM, "lo"); | 7957 » » » » » mips_regnum.lo, "lo"); |
5685 valid_p &= tdesc_numbered_register (feature, tdesc_data, | 7958 valid_p &= tdesc_numbered_register (feature, tdesc_data, |
5686 » » » » » MIPS_EMBED_HI_REGNUM, "hi"); | 7959 » » » » » mips_regnum.hi, "hi"); |
5687 valid_p &= tdesc_numbered_register (feature, tdesc_data, | 7960 valid_p &= tdesc_numbered_register (feature, tdesc_data, |
5688 » » » » » MIPS_EMBED_PC_REGNUM, "pc"); | 7961 » » » » » mips_regnum.pc, "pc"); |
5689 | 7962 |
5690 if (!valid_p) | 7963 if (!valid_p) |
5691 { | 7964 { |
5692 tdesc_data_cleanup (tdesc_data); | 7965 tdesc_data_cleanup (tdesc_data); |
5693 return NULL; | 7966 return NULL; |
5694 } | 7967 } |
5695 | 7968 |
5696 feature = tdesc_find_feature (info.target_desc, | 7969 feature = tdesc_find_feature (info.target_desc, |
5697 "org.gnu.gdb.mips.cp0"); | 7970 "org.gnu.gdb.mips.cp0"); |
5698 if (feature == NULL) | 7971 if (feature == NULL) |
5699 { | 7972 { |
5700 tdesc_data_cleanup (tdesc_data); | 7973 tdesc_data_cleanup (tdesc_data); |
5701 return NULL; | 7974 return NULL; |
5702 } | 7975 } |
5703 | 7976 |
5704 valid_p = 1; | 7977 valid_p = 1; |
5705 valid_p &= tdesc_numbered_register (feature, tdesc_data, | 7978 valid_p &= tdesc_numbered_register (feature, tdesc_data, |
5706 » » » » » MIPS_EMBED_BADVADDR_REGNUM, | 7979 » » » » » mips_regnum.badvaddr, "badvaddr"); |
5707 » » » » » "badvaddr"); | |
5708 valid_p &= tdesc_numbered_register (feature, tdesc_data, | 7980 valid_p &= tdesc_numbered_register (feature, tdesc_data, |
5709 MIPS_PS_REGNUM, "status"); | 7981 MIPS_PS_REGNUM, "status"); |
5710 valid_p &= tdesc_numbered_register (feature, tdesc_data, | 7982 valid_p &= tdesc_numbered_register (feature, tdesc_data, |
5711 » » » » » MIPS_EMBED_CAUSE_REGNUM, "cause"); | 7983 » » » » » mips_regnum.cause, "cause"); |
5712 | 7984 |
5713 if (!valid_p) | 7985 if (!valid_p) |
5714 { | 7986 { |
5715 tdesc_data_cleanup (tdesc_data); | 7987 tdesc_data_cleanup (tdesc_data); |
5716 return NULL; | 7988 return NULL; |
5717 } | 7989 } |
5718 | 7990 |
5719 /* FIXME drow/2007-05-17: The FPU should be optional. The MIPS | 7991 /* FIXME drow/2007-05-17: The FPU should be optional. The MIPS |
5720 backend is not prepared for that, though. */ | 7992 backend is not prepared for that, though. */ |
5721 feature = tdesc_find_feature (info.target_desc, | 7993 feature = tdesc_find_feature (info.target_desc, |
5722 "org.gnu.gdb.mips.fpu"); | 7994 "org.gnu.gdb.mips.fpu"); |
5723 if (feature == NULL) | 7995 if (feature == NULL) |
5724 { | 7996 { |
5725 tdesc_data_cleanup (tdesc_data); | 7997 tdesc_data_cleanup (tdesc_data); |
5726 return NULL; | 7998 return NULL; |
5727 } | 7999 } |
5728 | 8000 |
5729 valid_p = 1; | 8001 valid_p = 1; |
5730 for (i = 0; i < 32; i++) | 8002 for (i = 0; i < 32; i++) |
5731 valid_p &= tdesc_numbered_register (feature, tdesc_data, | 8003 valid_p &= tdesc_numbered_register (feature, tdesc_data, |
5732 » » » » » i + MIPS_EMBED_FP0_REGNUM, | 8004 » » » » » i + mips_regnum.fp0, mips_fprs[i]); |
5733 » » » » » mips_fprs[i]); | |
5734 | 8005 |
5735 valid_p &= tdesc_numbered_register (feature, tdesc_data, | 8006 valid_p &= tdesc_numbered_register (feature, tdesc_data, |
5736 » » » » » MIPS_EMBED_FP0_REGNUM + 32, "fcsr"); | 8007 » » » » » mips_regnum.fp_control_status, |
5737 valid_p &= tdesc_numbered_register (feature, tdesc_data, | 8008 » » » » » "fcsr"); |
5738 » » » » » MIPS_EMBED_FP0_REGNUM + 33, "fir"); | 8009 valid_p |
| 8010 » &= tdesc_numbered_register (feature, tdesc_data, |
| 8011 » » » » mips_regnum.fp_implementation_revision, |
| 8012 » » » » "fir"); |
5739 | 8013 |
5740 if (!valid_p) | 8014 if (!valid_p) |
5741 { | 8015 { |
5742 tdesc_data_cleanup (tdesc_data); | 8016 tdesc_data_cleanup (tdesc_data); |
5743 return NULL; | 8017 return NULL; |
5744 } | 8018 } |
5745 | 8019 |
| 8020 if (dspacc >= 0) |
| 8021 { |
| 8022 feature = tdesc_find_feature (info.target_desc, |
| 8023 "org.gnu.gdb.mips.dsp"); |
| 8024 /* The DSP registers are optional; it's OK if they are absent. */ |
| 8025 if (feature != NULL) |
| 8026 { |
| 8027 i = 0; |
| 8028 valid_p = 1; |
| 8029 valid_p &= tdesc_numbered_register (feature, tdesc_data, |
| 8030 dspacc + i++, "hi1"); |
| 8031 valid_p &= tdesc_numbered_register (feature, tdesc_data, |
| 8032 dspacc + i++, "lo1"); |
| 8033 valid_p &= tdesc_numbered_register (feature, tdesc_data, |
| 8034 dspacc + i++, "hi2"); |
| 8035 valid_p &= tdesc_numbered_register (feature, tdesc_data, |
| 8036 dspacc + i++, "lo2"); |
| 8037 valid_p &= tdesc_numbered_register (feature, tdesc_data, |
| 8038 dspacc + i++, "hi3"); |
| 8039 valid_p &= tdesc_numbered_register (feature, tdesc_data, |
| 8040 dspacc + i++, "lo3"); |
| 8041 |
| 8042 valid_p &= tdesc_numbered_register (feature, tdesc_data, |
| 8043 dspctl, "dspctl"); |
| 8044 |
| 8045 if (!valid_p) |
| 8046 { |
| 8047 tdesc_data_cleanup (tdesc_data); |
| 8048 return NULL; |
| 8049 } |
| 8050 |
| 8051 mips_regnum.dspacc = dspacc; |
| 8052 mips_regnum.dspctl = dspctl; |
| 8053 } |
| 8054 } |
| 8055 |
5746 /* It would be nice to detect an attempt to use a 64-bit ABI | 8056 /* It would be nice to detect an attempt to use a 64-bit ABI |
5747 when only 32-bit registers are provided. */ | 8057 when only 32-bit registers are provided. */ |
| 8058 reg_names = NULL; |
5748 } | 8059 } |
5749 | 8060 |
5750 /* First of all, extract the elf_flags, if available. */ | 8061 /* First of all, extract the elf_flags, if available. */ |
5751 if (info.abfd && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour) | 8062 if (info.abfd && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour) |
5752 elf_flags = elf_elfheader (info.abfd)->e_flags; | 8063 elf_flags = elf_elfheader (info.abfd)->e_flags; |
5753 else if (arches != NULL) | 8064 else if (arches != NULL) |
5754 elf_flags = gdbarch_tdep (arches->gdbarch)->elf_flags; | 8065 elf_flags = gdbarch_tdep (arches->gdbarch)->elf_flags; |
5755 else | 8066 else |
5756 elf_flags = 0; | 8067 elf_flags = 0; |
5757 if (gdbarch_debug) | 8068 if (gdbarch_debug) |
(...skipping 82 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... |
5840 if (wanted_abi != MIPS_ABI_UNKNOWN) | 8151 if (wanted_abi != MIPS_ABI_UNKNOWN) |
5841 mips_abi = wanted_abi; | 8152 mips_abi = wanted_abi; |
5842 else if (found_abi != MIPS_ABI_UNKNOWN) | 8153 else if (found_abi != MIPS_ABI_UNKNOWN) |
5843 mips_abi = found_abi; | 8154 mips_abi = found_abi; |
5844 else | 8155 else |
5845 mips_abi = MIPS_ABI_O32; | 8156 mips_abi = MIPS_ABI_O32; |
5846 if (gdbarch_debug) | 8157 if (gdbarch_debug) |
5847 fprintf_unfiltered (gdb_stdlog, "mips_gdbarch_init: mips_abi = %d\n", | 8158 fprintf_unfiltered (gdb_stdlog, "mips_gdbarch_init: mips_abi = %d\n", |
5848 mips_abi); | 8159 mips_abi); |
5849 | 8160 |
| 8161 /* Determine the default compressed ISA. */ |
| 8162 if ((elf_flags & EF_MIPS_ARCH_ASE_MICROMIPS) != 0 |
| 8163 && (elf_flags & EF_MIPS_ARCH_ASE_M16) == 0) |
| 8164 mips_isa = ISA_MICROMIPS; |
| 8165 else if ((elf_flags & EF_MIPS_ARCH_ASE_M16) != 0 |
| 8166 && (elf_flags & EF_MIPS_ARCH_ASE_MICROMIPS) == 0) |
| 8167 mips_isa = ISA_MIPS16; |
| 8168 else |
| 8169 mips_isa = global_mips_compression (); |
| 8170 mips_compression_string = mips_compression_strings[mips_isa]; |
| 8171 |
5850 /* Also used when doing an architecture lookup. */ | 8172 /* Also used when doing an architecture lookup. */ |
5851 if (gdbarch_debug) | 8173 if (gdbarch_debug) |
5852 fprintf_unfiltered (gdb_stdlog, | 8174 fprintf_unfiltered (gdb_stdlog, |
5853 "mips_gdbarch_init: " | 8175 "mips_gdbarch_init: " |
5854 "mips64_transfers_32bit_regs_p = %d\n", | 8176 "mips64_transfers_32bit_regs_p = %d\n", |
5855 mips64_transfers_32bit_regs_p); | 8177 mips64_transfers_32bit_regs_p); |
5856 | 8178 |
5857 /* Determine the MIPS FPU type. */ | 8179 /* Determine the MIPS FPU type. */ |
5858 #ifdef HAVE_ELF | 8180 #ifdef HAVE_ELF |
5859 if (info.abfd | 8181 if (info.abfd |
(...skipping 85 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... |
5945 return arches->gdbarch; | 8267 return arches->gdbarch; |
5946 } | 8268 } |
5947 | 8269 |
5948 /* Need a new architecture. Fill in a target specific vector. */ | 8270 /* Need a new architecture. Fill in a target specific vector. */ |
5949 tdep = (struct gdbarch_tdep *) xmalloc (sizeof (struct gdbarch_tdep)); | 8271 tdep = (struct gdbarch_tdep *) xmalloc (sizeof (struct gdbarch_tdep)); |
5950 gdbarch = gdbarch_alloc (&info, tdep); | 8272 gdbarch = gdbarch_alloc (&info, tdep); |
5951 tdep->elf_flags = elf_flags; | 8273 tdep->elf_flags = elf_flags; |
5952 tdep->mips64_transfers_32bit_regs_p = mips64_transfers_32bit_regs_p; | 8274 tdep->mips64_transfers_32bit_regs_p = mips64_transfers_32bit_regs_p; |
5953 tdep->found_abi = found_abi; | 8275 tdep->found_abi = found_abi; |
5954 tdep->mips_abi = mips_abi; | 8276 tdep->mips_abi = mips_abi; |
| 8277 tdep->mips_isa = mips_isa; |
5955 tdep->mips_fpu_type = fpu_type; | 8278 tdep->mips_fpu_type = fpu_type; |
5956 tdep->register_size_valid_p = 0; | 8279 tdep->register_size_valid_p = 0; |
5957 tdep->register_size = 0; | 8280 tdep->register_size = 0; |
5958 tdep->gregset = NULL; | 8281 tdep->gregset = NULL; |
5959 tdep->gregset64 = NULL; | 8282 tdep->gregset64 = NULL; |
5960 tdep->fpregset = NULL; | 8283 tdep->fpregset = NULL; |
5961 tdep->fpregset64 = NULL; | 8284 tdep->fpregset64 = NULL; |
5962 | 8285 |
5963 if (info.target_desc) | 8286 if (info.target_desc) |
5964 { | 8287 { |
(...skipping 21 matching lines...) Expand all Loading... |
5986 set_gdbarch_pseudo_register_write (gdbarch, mips_pseudo_register_write); | 8309 set_gdbarch_pseudo_register_write (gdbarch, mips_pseudo_register_write); |
5987 | 8310 |
5988 set_gdbarch_ax_pseudo_register_collect (gdbarch, | 8311 set_gdbarch_ax_pseudo_register_collect (gdbarch, |
5989 mips_ax_pseudo_register_collect); | 8312 mips_ax_pseudo_register_collect); |
5990 set_gdbarch_ax_pseudo_register_push_stack | 8313 set_gdbarch_ax_pseudo_register_push_stack |
5991 (gdbarch, mips_ax_pseudo_register_push_stack); | 8314 (gdbarch, mips_ax_pseudo_register_push_stack); |
5992 | 8315 |
5993 set_gdbarch_elf_make_msymbol_special (gdbarch, | 8316 set_gdbarch_elf_make_msymbol_special (gdbarch, |
5994 mips_elf_make_msymbol_special); | 8317 mips_elf_make_msymbol_special); |
5995 | 8318 |
5996 /* Fill in the OS dependant register numbers and names. */ | 8319 regnum = GDBARCH_OBSTACK_ZALLOC (gdbarch, struct mips_regnum); |
5997 { | 8320 *regnum = mips_regnum; |
5998 const char **reg_names; | 8321 set_gdbarch_fp0_regnum (gdbarch, regnum->fp0); |
5999 struct mips_regnum *regnum = GDBARCH_OBSTACK_ZALLOC (gdbarch, | 8322 set_gdbarch_num_regs (gdbarch, num_regs); |
6000 » » » » » » » struct mips_regnum); | 8323 set_gdbarch_num_pseudo_regs (gdbarch, num_regs); |
6001 if (tdesc_has_registers (info.target_desc)) | 8324 set_gdbarch_register_name (gdbarch, mips_register_name); |
6002 { | 8325 set_gdbarch_virtual_frame_pointer (gdbarch, mips_virtual_frame_pointer); |
6003 » regnum->lo = MIPS_EMBED_LO_REGNUM; | 8326 tdep->mips_processor_reg_names = reg_names; |
6004 » regnum->hi = MIPS_EMBED_HI_REGNUM; | 8327 tdep->regnum = regnum; |
6005 » regnum->badvaddr = MIPS_EMBED_BADVADDR_REGNUM; | |
6006 » regnum->cause = MIPS_EMBED_CAUSE_REGNUM; | |
6007 » regnum->pc = MIPS_EMBED_PC_REGNUM; | |
6008 » regnum->fp0 = MIPS_EMBED_FP0_REGNUM; | |
6009 » regnum->fp_control_status = 70; | |
6010 » regnum->fp_implementation_revision = 71; | |
6011 » num_regs = MIPS_LAST_EMBED_REGNUM + 1; | |
6012 » reg_names = NULL; | |
6013 } | |
6014 else if (info.osabi == GDB_OSABI_IRIX) | |
6015 { | |
6016 » regnum->fp0 = 32; | |
6017 » regnum->pc = 64; | |
6018 » regnum->cause = 65; | |
6019 » regnum->badvaddr = 66; | |
6020 » regnum->hi = 67; | |
6021 » regnum->lo = 68; | |
6022 » regnum->fp_control_status = 69; | |
6023 » regnum->fp_implementation_revision = 70; | |
6024 » num_regs = 71; | |
6025 » reg_names = mips_irix_reg_names; | |
6026 } | |
6027 else | |
6028 { | |
6029 » regnum->lo = MIPS_EMBED_LO_REGNUM; | |
6030 » regnum->hi = MIPS_EMBED_HI_REGNUM; | |
6031 » regnum->badvaddr = MIPS_EMBED_BADVADDR_REGNUM; | |
6032 » regnum->cause = MIPS_EMBED_CAUSE_REGNUM; | |
6033 » regnum->pc = MIPS_EMBED_PC_REGNUM; | |
6034 » regnum->fp0 = MIPS_EMBED_FP0_REGNUM; | |
6035 » regnum->fp_control_status = 70; | |
6036 » regnum->fp_implementation_revision = 71; | |
6037 » num_regs = 90; | |
6038 » if (info.bfd_arch_info != NULL | |
6039 » && info.bfd_arch_info->mach == bfd_mach_mips3900) | |
6040 » reg_names = mips_tx39_reg_names; | |
6041 » else | |
6042 » reg_names = mips_generic_reg_names; | |
6043 } | |
6044 /* FIXME: cagney/2003-11-15: For MIPS, hasn't gdbarch_pc_regnum been | |
6045 replaced by gdbarch_read_pc? */ | |
6046 set_gdbarch_pc_regnum (gdbarch, regnum->pc + num_regs); | |
6047 set_gdbarch_sp_regnum (gdbarch, MIPS_SP_REGNUM + num_regs); | |
6048 set_gdbarch_fp0_regnum (gdbarch, regnum->fp0); | |
6049 set_gdbarch_num_regs (gdbarch, num_regs); | |
6050 set_gdbarch_num_pseudo_regs (gdbarch, num_regs); | |
6051 set_gdbarch_register_name (gdbarch, mips_register_name); | |
6052 set_gdbarch_virtual_frame_pointer (gdbarch, mips_virtual_frame_pointer); | |
6053 tdep->mips_processor_reg_names = reg_names; | |
6054 tdep->regnum = regnum; | |
6055 } | |
6056 | 8328 |
6057 switch (mips_abi) | 8329 switch (mips_abi) |
6058 { | 8330 { |
6059 case MIPS_ABI_O32: | 8331 case MIPS_ABI_O32: |
6060 set_gdbarch_push_dummy_call (gdbarch, mips_o32_push_dummy_call); | 8332 set_gdbarch_push_dummy_call (gdbarch, mips_o32_push_dummy_call); |
6061 set_gdbarch_return_value (gdbarch, mips_o32_return_value); | 8333 set_gdbarch_return_value (gdbarch, mips_o32_return_value); |
6062 tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 4 - 1; | 8334 tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 4 - 1; |
6063 tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 4 - 1; | 8335 tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 4 - 1; |
6064 tdep->default_mask_address_p = 0; | 8336 tdep->default_mask_address_p = 0; |
6065 set_gdbarch_long_bit (gdbarch, 32); | 8337 set_gdbarch_long_bit (gdbarch, 32); |
(...skipping 145 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... |
6211 /* Map debug register numbers onto internal register numbers. */ | 8483 /* Map debug register numbers onto internal register numbers. */ |
6212 set_gdbarch_stab_reg_to_regnum (gdbarch, mips_stab_reg_to_regnum); | 8484 set_gdbarch_stab_reg_to_regnum (gdbarch, mips_stab_reg_to_regnum); |
6213 set_gdbarch_ecoff_reg_to_regnum (gdbarch, | 8485 set_gdbarch_ecoff_reg_to_regnum (gdbarch, |
6214 mips_dwarf_dwarf2_ecoff_reg_to_regnum); | 8486 mips_dwarf_dwarf2_ecoff_reg_to_regnum); |
6215 set_gdbarch_dwarf2_reg_to_regnum (gdbarch, | 8487 set_gdbarch_dwarf2_reg_to_regnum (gdbarch, |
6216 mips_dwarf_dwarf2_ecoff_reg_to_regnum); | 8488 mips_dwarf_dwarf2_ecoff_reg_to_regnum); |
6217 set_gdbarch_register_sim_regno (gdbarch, mips_register_sim_regno); | 8489 set_gdbarch_register_sim_regno (gdbarch, mips_register_sim_regno); |
6218 | 8490 |
6219 /* MIPS version of CALL_DUMMY. */ | 8491 /* MIPS version of CALL_DUMMY. */ |
6220 | 8492 |
6221 /* NOTE: cagney/2003-08-05: Eventually call dummy location will be | 8493 set_gdbarch_call_dummy_location (gdbarch, ON_STACK); |
6222 replaced by a command, and all targets will default to on stack | 8494 set_gdbarch_push_dummy_code (gdbarch, mips_push_dummy_code); |
6223 (regardless of the stack's execute status). */ | |
6224 set_gdbarch_call_dummy_location (gdbarch, AT_SYMBOL); | |
6225 set_gdbarch_frame_align (gdbarch, mips_frame_align); | 8495 set_gdbarch_frame_align (gdbarch, mips_frame_align); |
6226 | 8496 |
6227 set_gdbarch_convert_register_p (gdbarch, mips_convert_register_p); | 8497 set_gdbarch_convert_register_p (gdbarch, mips_convert_register_p); |
6228 set_gdbarch_register_to_value (gdbarch, mips_register_to_value); | 8498 set_gdbarch_register_to_value (gdbarch, mips_register_to_value); |
6229 set_gdbarch_value_to_register (gdbarch, mips_value_to_register); | 8499 set_gdbarch_value_to_register (gdbarch, mips_value_to_register); |
6230 | 8500 |
6231 set_gdbarch_inner_than (gdbarch, core_addr_lessthan); | 8501 set_gdbarch_inner_than (gdbarch, core_addr_lessthan); |
6232 set_gdbarch_breakpoint_from_pc (gdbarch, mips_breakpoint_from_pc); | 8502 set_gdbarch_breakpoint_from_pc (gdbarch, mips_breakpoint_from_pc); |
| 8503 set_gdbarch_remote_breakpoint_from_pc (gdbarch, |
| 8504 mips_remote_breakpoint_from_pc); |
| 8505 set_gdbarch_adjust_breakpoint_address (gdbarch, |
| 8506 mips_adjust_breakpoint_address); |
6233 | 8507 |
6234 set_gdbarch_skip_prologue (gdbarch, mips_skip_prologue); | 8508 set_gdbarch_skip_prologue (gdbarch, mips_skip_prologue); |
6235 | 8509 |
6236 set_gdbarch_in_function_epilogue_p (gdbarch, mips_in_function_epilogue_p); | 8510 set_gdbarch_in_function_epilogue_p (gdbarch, mips_in_function_epilogue_p); |
6237 | 8511 |
6238 set_gdbarch_pointer_to_address (gdbarch, signed_pointer_to_address); | 8512 set_gdbarch_pointer_to_address (gdbarch, signed_pointer_to_address); |
6239 set_gdbarch_address_to_pointer (gdbarch, address_to_signed_pointer); | 8513 set_gdbarch_address_to_pointer (gdbarch, address_to_signed_pointer); |
6240 set_gdbarch_integer_to_address (gdbarch, mips_integer_to_address); | 8514 set_gdbarch_integer_to_address (gdbarch, mips_integer_to_address); |
6241 | 8515 |
6242 set_gdbarch_register_type (gdbarch, mips_register_type); | 8516 set_gdbarch_register_type (gdbarch, mips_register_type); |
(...skipping 10 matching lines...) Expand all Loading... |
6253 /* FIXME: cagney/2003-08-29: The macros target_have_steppable_watchpoint, | 8527 /* FIXME: cagney/2003-08-29: The macros target_have_steppable_watchpoint, |
6254 HAVE_NONSTEPPABLE_WATCHPOINT, and target_have_continuable_watchpoint | 8528 HAVE_NONSTEPPABLE_WATCHPOINT, and target_have_continuable_watchpoint |
6255 need to all be folded into the target vector. Since they are | 8529 need to all be folded into the target vector. Since they are |
6256 being used as guards for target_stopped_by_watchpoint, why not have | 8530 being used as guards for target_stopped_by_watchpoint, why not have |
6257 target_stopped_by_watchpoint return the type of watchpoint that the code | 8531 target_stopped_by_watchpoint return the type of watchpoint that the code |
6258 is sitting on? */ | 8532 is sitting on? */ |
6259 set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1); | 8533 set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1); |
6260 | 8534 |
6261 set_gdbarch_skip_trampoline_code (gdbarch, mips_skip_trampoline_code); | 8535 set_gdbarch_skip_trampoline_code (gdbarch, mips_skip_trampoline_code); |
6262 | 8536 |
| 8537 /* NOTE drow/2012-04-25: We overload the core solib trampoline code |
| 8538 to support MIPS16. This is a bad thing. Make sure not to do it |
| 8539 if we have an OS ABI that actually supports shared libraries, since |
| 8540 shared library support is more important. If we have an OS someday |
| 8541 that supports both shared libraries and MIPS16, we'll have to find |
| 8542 a better place for these. |
| 8543 macro/2012-04-25: But that applies to return trampolines only and |
| 8544 currently no MIPS OS ABI uses shared libraries that have them. */ |
| 8545 set_gdbarch_in_solib_return_trampoline (gdbarch, mips_in_return_stub); |
| 8546 |
6263 set_gdbarch_single_step_through_delay (gdbarch, | 8547 set_gdbarch_single_step_through_delay (gdbarch, |
6264 mips_single_step_through_delay); | 8548 mips_single_step_through_delay); |
6265 | 8549 |
6266 /* Virtual tables. */ | 8550 /* Virtual tables. */ |
6267 set_gdbarch_vbit_in_delta (gdbarch, 1); | 8551 set_gdbarch_vbit_in_delta (gdbarch, 1); |
6268 | 8552 |
6269 mips_register_g_packet_guesses (gdbarch); | 8553 mips_register_g_packet_guesses (gdbarch); |
6270 | 8554 |
6271 /* Hook in OS ABI-specific overrides, if they have been registered. */ | 8555 /* Hook in OS ABI-specific overrides, if they have been registered. */ |
6272 info.tdep_info = (void *) tdesc_data; | 8556 info.tdep_info = (void *) tdesc_data; |
6273 gdbarch_init_osabi (info, gdbarch); | 8557 gdbarch_init_osabi (info, gdbarch); |
6274 | 8558 |
| 8559 /* The hook may have adjusted num_regs, fetch the final value and |
| 8560 set pc_regnum and sp_regnum now that it has been fixed. */ |
| 8561 num_regs = gdbarch_num_regs (gdbarch); |
| 8562 set_gdbarch_pc_regnum (gdbarch, regnum->pc + num_regs); |
| 8563 set_gdbarch_sp_regnum (gdbarch, MIPS_SP_REGNUM + num_regs); |
| 8564 |
6275 /* Unwind the frame. */ | 8565 /* Unwind the frame. */ |
6276 dwarf2_append_unwinders (gdbarch); | 8566 dwarf2_append_unwinders (gdbarch); |
6277 frame_unwind_append_unwinder (gdbarch, &mips_stub_frame_unwind); | 8567 frame_unwind_append_unwinder (gdbarch, &mips_stub_frame_unwind); |
6278 frame_unwind_append_unwinder (gdbarch, &mips_insn16_frame_unwind); | 8568 frame_unwind_append_unwinder (gdbarch, &mips_insn16_frame_unwind); |
| 8569 frame_unwind_append_unwinder (gdbarch, &mips_micro_frame_unwind); |
6279 frame_unwind_append_unwinder (gdbarch, &mips_insn32_frame_unwind); | 8570 frame_unwind_append_unwinder (gdbarch, &mips_insn32_frame_unwind); |
6280 frame_base_append_sniffer (gdbarch, dwarf2_frame_base_sniffer); | 8571 frame_base_append_sniffer (gdbarch, dwarf2_frame_base_sniffer); |
6281 frame_base_append_sniffer (gdbarch, mips_stub_frame_base_sniffer); | 8572 frame_base_append_sniffer (gdbarch, mips_stub_frame_base_sniffer); |
6282 frame_base_append_sniffer (gdbarch, mips_insn16_frame_base_sniffer); | 8573 frame_base_append_sniffer (gdbarch, mips_insn16_frame_base_sniffer); |
| 8574 frame_base_append_sniffer (gdbarch, mips_micro_frame_base_sniffer); |
6283 frame_base_append_sniffer (gdbarch, mips_insn32_frame_base_sniffer); | 8575 frame_base_append_sniffer (gdbarch, mips_insn32_frame_base_sniffer); |
6284 | 8576 |
6285 if (tdesc_data) | 8577 if (tdesc_data) |
6286 { | 8578 { |
6287 set_tdesc_pseudo_register_type (gdbarch, mips_pseudo_register_type); | 8579 set_tdesc_pseudo_register_type (gdbarch, mips_pseudo_register_type); |
6288 tdesc_use_registers (gdbarch, info.target_desc, tdesc_data); | 8580 tdesc_use_registers (gdbarch, info.target_desc, tdesc_data); |
6289 | 8581 |
6290 /* Override the normal target description methods to handle our | 8582 /* Override the normal target description methods to handle our |
6291 dual real and pseudo registers. */ | 8583 dual real and pseudo registers. */ |
6292 set_gdbarch_register_name (gdbarch, mips_register_name); | 8584 set_gdbarch_register_name (gdbarch, mips_register_name); |
(...skipping 73 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... |
6366 { | 8658 { |
6367 /* Probably shouldn't happen... */ | 8659 /* Probably shouldn't happen... */ |
6368 fprintf_filtered (file, | 8660 fprintf_filtered (file, |
6369 "The (auto detected) MIPS ABI \"%s\" is in use " | 8661 "The (auto detected) MIPS ABI \"%s\" is in use " |
6370 "even though the user setting was \"%s\".\n", | 8662 "even though the user setting was \"%s\".\n", |
6371 actual_abi_str, mips_abi_strings[global_abi]); | 8663 actual_abi_str, mips_abi_strings[global_abi]); |
6372 } | 8664 } |
6373 } | 8665 } |
6374 } | 8666 } |
6375 | 8667 |
| 8668 /* Print out which MIPS compressed ISA encoding is used. */ |
| 8669 |
| 8670 static void |
| 8671 show_mips_compression (struct ui_file *file, int from_tty, |
| 8672 struct cmd_list_element *c, const char *value) |
| 8673 { |
| 8674 fprintf_filtered (file, _("The compressed ISA encoding used is %s.\n"), |
| 8675 value); |
| 8676 } |
| 8677 |
6376 static void | 8678 static void |
6377 mips_dump_tdep (struct gdbarch *gdbarch, struct ui_file *file) | 8679 mips_dump_tdep (struct gdbarch *gdbarch, struct ui_file *file) |
6378 { | 8680 { |
6379 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | 8681 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); |
6380 if (tdep != NULL) | 8682 if (tdep != NULL) |
6381 { | 8683 { |
6382 int ef_mips_arch; | 8684 int ef_mips_arch; |
6383 int ef_mips_32bitmode; | 8685 int ef_mips_32bitmode; |
6384 /* Determine the ISA. */ | 8686 /* Determine the ISA. */ |
6385 switch (tdep->elf_flags & EF_MIPS_ARCH) | 8687 switch (tdep->elf_flags & EF_MIPS_ARCH) |
(...skipping 96 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... |
6482 o32\n\ | 8784 o32\n\ |
6483 o64\n\ | 8785 o64\n\ |
6484 n32\n\ | 8786 n32\n\ |
6485 n64\n\ | 8787 n64\n\ |
6486 eabi32\n\ | 8788 eabi32\n\ |
6487 eabi64"), | 8789 eabi64"), |
6488 mips_abi_update, | 8790 mips_abi_update, |
6489 show_mips_abi, | 8791 show_mips_abi, |
6490 &setmipscmdlist, &showmipscmdlist); | 8792 &setmipscmdlist, &showmipscmdlist); |
6491 | 8793 |
| 8794 /* Allow the user to set the ISA to assume for compressed code if ELF |
| 8795 file flags don't tell or there is no program file selected. This |
| 8796 setting is updated whenever unambiguous ELF file flags are interpreted, |
| 8797 and carried over to subsequent sessions. */ |
| 8798 add_setshow_enum_cmd ("compression", class_obscure, mips_compression_strings, |
| 8799 &mips_compression_string, _("\ |
| 8800 Set the compressed ISA encoding used by MIPS code."), _("\ |
| 8801 Show the compressed ISA encoding used by MIPS code."), _("\ |
| 8802 Select the compressed ISA encoding used in functions that have no symbol\n\ |
| 8803 information available. The encoding can be set to either of:\n\ |
| 8804 mips16\n\ |
| 8805 micromips\n\ |
| 8806 and is updated automatically from ELF file flags if available."), |
| 8807 mips_abi_update, |
| 8808 show_mips_compression, |
| 8809 &setmipscmdlist, &showmipscmdlist); |
| 8810 |
6492 /* Let the user turn off floating point and set the fence post for | 8811 /* Let the user turn off floating point and set the fence post for |
6493 heuristic_proc_start. */ | 8812 heuristic_proc_start. */ |
6494 | 8813 |
6495 add_prefix_cmd ("mipsfpu", class_support, set_mipsfpu_command, | 8814 add_prefix_cmd ("mipsfpu", class_support, set_mipsfpu_command, |
6496 _("Set use of MIPS floating-point coprocessor."), | 8815 _("Set use of MIPS floating-point coprocessor."), |
6497 &mipsfpulist, "set mipsfpu ", 0, &setlist); | 8816 &mipsfpulist, "set mipsfpu ", 0, &setlist); |
6498 add_cmd ("single", class_support, set_mipsfpu_single_command, | 8817 add_cmd ("single", class_support, set_mipsfpu_single_command, |
6499 _("Select single-precision MIPS floating-point coprocessor."), | 8818 _("Select single-precision MIPS floating-point coprocessor."), |
6500 &mipsfpulist); | 8819 &mipsfpulist); |
6501 add_cmd ("double", class_support, set_mipsfpu_double_command, | 8820 add_cmd ("double", class_support, set_mipsfpu_double_command, |
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6563 add_setshow_zinteger_cmd ("mips", class_maintenance, | 8882 add_setshow_zinteger_cmd ("mips", class_maintenance, |
6564 &mips_debug, _("\ | 8883 &mips_debug, _("\ |
6565 Set mips debugging."), _("\ | 8884 Set mips debugging."), _("\ |
6566 Show mips debugging."), _("\ | 8885 Show mips debugging."), _("\ |
6567 When non-zero, mips specific debugging is enabled."), | 8886 When non-zero, mips specific debugging is enabled."), |
6568 NULL, | 8887 NULL, |
6569 NULL, /* FIXME: i18n: Mips debugging is | 8888 NULL, /* FIXME: i18n: Mips debugging is |
6570 currently %s. */ | 8889 currently %s. */ |
6571 &setdebuglist, &showdebuglist); | 8890 &setdebuglist, &showdebuglist); |
6572 } | 8891 } |
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