Merge GDB 7.5.1

gdb/arm-tdep.h

 /* Common target dependent code for GDB on ARM systems.
    Copyright (C) 2002-2003, 2007-2012 Free Software Foundation, Inc.
 
    This file is part of GDB.
 
    This program is free software; you can redistribute it and/or modify
    it under the terms of the GNU General Public License as published by
    the Free Software Foundation; either version 3 of the License, or
    (at your option) any later version.
 
@@ skipping 53 matching lines @@
 };
 
 /* Size of integer registers.  */
 #define INT_REGISTER_SIZE               4
 
 /* Say how long FP registers are.  Used for documentation purposes and
    code readability in this header.  IEEE extended doubles are 80
    bits.  DWORD aligned they use 96 bits.  */
 #define FP_REGISTER_SIZE        12
 
+/* Say how long VFP double precision registers are.  Used for documentation
+   purposes and code readability.  These are fixed at 64 bits.  */
+#define VFP_REGISTER_SIZE       8
+
 /* Number of machine registers.  The only define actually required 
    is gdbarch_num_regs.  The other definitions are used for documentation
    purposes and code readability.  */
 /* For 26 bit ARM code, a fake copy of the PC is placed in register 25 (PS)
    (and called PS for processor status) so the status bits can be cleared
    from the PC (register 15).  For 32 bit ARM code, a copy of CPSR is placed
    in PS.  */
 #define NUM_FREGS       8       /* Number of floating point registers.  */
 #define NUM_SREGS       2       /* Number of status registers.  */
 #define NUM_GREGS       16      /* Number of general purpose registers.  */
@@ skipping 109 matching lines @@
   struct regset *gregset, *fpregset, *vfpregset;
 
   /* ISA-specific data types.  */
   struct type *arm_ext_type;
   struct type *neon_double_type;
   struct type *neon_quad_type;
 
   /* Return the expected next PC if FRAME is stopped at a syscall
      instruction.  */
   CORE_ADDR (*syscall_next_pc) (struct frame_info *frame);
+
+   /* Parse swi insn args, sycall record.  */
+  int (*arm_swi_record) (struct regcache *regcache);
 };
 
 /* Structures used for displaced stepping.  */
 
 /* The maximum number of temporaries available for displaced instructions.  */
 #define DISPLACED_TEMPS                 16
 /* The maximum number of modified instructions generated for one single-stepped
    instruction, including the breakpoint (usually at the end of the instruction
    sequence) and any scratch words, etc.  */
 #define DISPLACED_MODIFIED_INSNS        8
@@ skipping 110 matching lines @@
                                       struct displaced_step_closure *,
                                       CORE_ADDR, CORE_ADDR, struct regcache *);
 
 /* Return the bit mask in ARM_PS_REGNUM that indicates Thumb mode.  */
 extern int arm_psr_thumb_bit (struct gdbarch *);
 
 /* Is the instruction at the given memory address a Thumb or ARM
    instruction?  */
 extern int arm_pc_is_thumb (struct gdbarch *, CORE_ADDR);
 
+extern int arm_process_record (struct gdbarch *gdbarch, 
+                               struct regcache *regcache, CORE_ADDR addr);
 /* Functions exported from armbsd-tdep.h.  */
 
 /* Return the appropriate register set for the core section identified
    by SECT_NAME and SECT_SIZE.  */
 
 extern const struct regset *
   armbsd_regset_from_core_section (struct gdbarch *gdbarch,
                                    const char *sect_name, size_t sect_size);
 
 /* Target descriptions.  */
 extern struct target_desc *tdesc_arm_with_m;
 extern struct target_desc *tdesc_arm_with_iwmmxt;
 extern struct target_desc *tdesc_arm_with_vfpv2;
 extern struct target_desc *tdesc_arm_with_vfpv3;
 extern struct target_desc *tdesc_arm_with_neon;
 
 #endif /* arm-tdep.h */