Merge GDB 7.5.1

bfd/doc/reloc.texi

 @section Relocations
 BFD maintains relocations in much the same way it maintains
 symbols: they are left alone until required, then read in
 en-masse and translated into an internal form.  A common
 routine @code{bfd_perform_relocation} acts upon the
 canonical form to do the fixup.
 
 Relocations are maintained on a per section basis,
 while symbols are maintained on a per BFD basis.
 
@@ skipping 644 matching lines @@
 @deffnx {} BFD_RELOC_SPARC_5
 @deffnx {} BFD_RELOC_SPARC_DISP64
 @deffnx {} BFD_RELOC_SPARC_PLT32
 @deffnx {} BFD_RELOC_SPARC_PLT64
 @deffnx {} BFD_RELOC_SPARC_HIX22
 @deffnx {} BFD_RELOC_SPARC_LOX10
 @deffnx {} BFD_RELOC_SPARC_H44
 @deffnx {} BFD_RELOC_SPARC_M44
 @deffnx {} BFD_RELOC_SPARC_L44
 @deffnx {} BFD_RELOC_SPARC_REGISTER
+@deffnx {} BFD_RELOC_SPARC_H34
+@deffnx {} BFD_RELOC_SPARC_SIZE32
+@deffnx {} BFD_RELOC_SPARC_SIZE64
+@deffnx {} BFD_RELOC_SPARC_WDISP10
 SPARC64 relocations
 @end deffn
 @deffn {} BFD_RELOC_SPARC_REV32
 SPARC little endian relocation
 @end deffn
 @deffn {} BFD_RELOC_SPARC_TLS_GD_HI22
 @deffnx {} BFD_RELOC_SPARC_TLS_GD_LO10
 @deffnx {} BFD_RELOC_SPARC_TLS_GD_ADD
 @deffnx {} BFD_RELOC_SPARC_TLS_GD_CALL
 @deffnx {} BFD_RELOC_SPARC_TLS_LDM_HI22
@@ skipping 176 matching lines @@
 @end deffn
 @deffn {} BFD_RELOC_MIPS16_HI16_S
 MIPS16 high 16 bits of 32-bit value but the low 16 bits will be sign
 extended and added to form the final result.  If the low 16
 bits form a negative number, we need to add one to the high value
 to compensate for the borrow when the low bits are added.
 @end deffn
 @deffn {} BFD_RELOC_MIPS16_LO16
 MIPS16 low 16 bits.
 @end deffn
+@deffn {} BFD_RELOC_MIPS16_TLS_GD
+@deffnx {} BFD_RELOC_MIPS16_TLS_LDM
+@deffnx {} BFD_RELOC_MIPS16_TLS_DTPREL_HI16
+@deffnx {} BFD_RELOC_MIPS16_TLS_DTPREL_LO16
+@deffnx {} BFD_RELOC_MIPS16_TLS_GOTTPREL
+@deffnx {} BFD_RELOC_MIPS16_TLS_TPREL_HI16
+@deffnx {} BFD_RELOC_MIPS16_TLS_TPREL_LO16
+MIPS16 TLS relocations
+@end deffn
 @deffn {} BFD_RELOC_MIPS_LITERAL
 @deffnx {} BFD_RELOC_MICROMIPS_LITERAL
 Relocation against a MIPS literal section.
 @end deffn
 @deffn {} BFD_RELOC_MICROMIPS_7_PCREL_S1
 @deffnx {} BFD_RELOC_MICROMIPS_10_PCREL_S1
 @deffnx {} BFD_RELOC_MICROMIPS_16_PCREL_S1
 microMIPS PC-relative relocations.
 @end deffn
 @deffn {} BFD_RELOC_MICROMIPS_GPREL16
@@ skipping 137 matching lines @@
 @deffn {} BFD_RELOC_MN10300_SYM_DIFF
 Together with another reloc targeted at the same location,
 allows for a value that is the difference of two symbols
 in the same section.
 @end deffn
 @deffn {} BFD_RELOC_MN10300_ALIGN
 The addend of this reloc is an alignment power that must
 be honoured at the offset's location, regardless of linker
 relaxation.
 @end deffn
+@deffn {} BFD_RELOC_MN10300_TLS_GD
+@deffnx {} BFD_RELOC_MN10300_TLS_LD
+@deffnx {} BFD_RELOC_MN10300_TLS_LDO
+@deffnx {} BFD_RELOC_MN10300_TLS_GOTIE
+@deffnx {} BFD_RELOC_MN10300_TLS_IE
+@deffnx {} BFD_RELOC_MN10300_TLS_LE
+@deffnx {} BFD_RELOC_MN10300_TLS_DTPMOD
+@deffnx {} BFD_RELOC_MN10300_TLS_DTPOFF
+@deffnx {} BFD_RELOC_MN10300_TLS_TPOFF
+Various TLS-related relocations.
+@end deffn
+@deffn {} BFD_RELOC_MN10300_32_PCREL
+This is a 32bit pcrel reloc for the mn10300, offset by two bytes in the
+instruction.
+@end deffn
+@deffn {} BFD_RELOC_MN10300_16_PCREL
+This is a 16bit pcrel reloc for the mn10300, offset by two bytes in the
+instruction.
+@end deffn
 @deffn {} BFD_RELOC_386_GOT32
 @deffnx {} BFD_RELOC_386_PLT32
 @deffnx {} BFD_RELOC_386_COPY
 @deffnx {} BFD_RELOC_386_GLOB_DAT
 @deffnx {} BFD_RELOC_386_JUMP_SLOT
 @deffnx {} BFD_RELOC_386_RELATIVE
 @deffnx {} BFD_RELOC_386_GOTOFF
 @deffnx {} BFD_RELOC_386_GOTPC
 @deffnx {} BFD_RELOC_386_TLS_TPOFF
 @deffnx {} BFD_RELOC_386_TLS_IE
@@ skipping 91 matching lines @@
 @deffnx {} BFD_RELOC_PPC_EMB_SDA2I16
 @deffnx {} BFD_RELOC_PPC_EMB_SDA2REL
 @deffnx {} BFD_RELOC_PPC_EMB_SDA21
 @deffnx {} BFD_RELOC_PPC_EMB_MRKREF
 @deffnx {} BFD_RELOC_PPC_EMB_RELSEC16
 @deffnx {} BFD_RELOC_PPC_EMB_RELST_LO
 @deffnx {} BFD_RELOC_PPC_EMB_RELST_HI
 @deffnx {} BFD_RELOC_PPC_EMB_RELST_HA
 @deffnx {} BFD_RELOC_PPC_EMB_BIT_FLD
 @deffnx {} BFD_RELOC_PPC_EMB_RELSDA
+@deffnx {} BFD_RELOC_PPC_VLE_REL8
+@deffnx {} BFD_RELOC_PPC_VLE_REL15
+@deffnx {} BFD_RELOC_PPC_VLE_REL24
+@deffnx {} BFD_RELOC_PPC_VLE_LO16A
+@deffnx {} BFD_RELOC_PPC_VLE_LO16D
+@deffnx {} BFD_RELOC_PPC_VLE_HI16A
+@deffnx {} BFD_RELOC_PPC_VLE_HI16D
+@deffnx {} BFD_RELOC_PPC_VLE_HA16A
+@deffnx {} BFD_RELOC_PPC_VLE_HA16D
+@deffnx {} BFD_RELOC_PPC_VLE_SDA21
+@deffnx {} BFD_RELOC_PPC_VLE_SDA21_LO
+@deffnx {} BFD_RELOC_PPC_VLE_SDAREL_LO16A
+@deffnx {} BFD_RELOC_PPC_VLE_SDAREL_LO16D
+@deffnx {} BFD_RELOC_PPC_VLE_SDAREL_HI16A
+@deffnx {} BFD_RELOC_PPC_VLE_SDAREL_HI16D
+@deffnx {} BFD_RELOC_PPC_VLE_SDAREL_HA16A
+@deffnx {} BFD_RELOC_PPC_VLE_SDAREL_HA16D
 @deffnx {} BFD_RELOC_PPC64_HIGHER
 @deffnx {} BFD_RELOC_PPC64_HIGHER_S
 @deffnx {} BFD_RELOC_PPC64_HIGHEST
 @deffnx {} BFD_RELOC_PPC64_HIGHEST_S
 @deffnx {} BFD_RELOC_PPC64_TOC16_LO
 @deffnx {} BFD_RELOC_PPC64_TOC16_HI
 @deffnx {} BFD_RELOC_PPC64_TOC16_HA
 @deffnx {} BFD_RELOC_PPC64_TOC
 @deffnx {} BFD_RELOC_PPC64_PLTGOT16
 @deffnx {} BFD_RELOC_PPC64_PLTGOT16_LO
@@ skipping 703 matching lines @@
 @end deffn
 @deffn {} BFD_RELOC_V850_32_GOTOFF
 DSO relocations.
 @end deffn
 @deffn {} BFD_RELOC_V850_CODE
 start code.
 @end deffn
 @deffn {} BFD_RELOC_V850_DATA
 start data in text.
 @end deffn
-@deffn {} BFD_RELOC_MN10300_32_PCREL
-This is a 32bit pcrel reloc for the mn10300, offset by two bytes in the
-instruction.
-@end deffn
-@deffn {} BFD_RELOC_MN10300_16_PCREL
-This is a 16bit pcrel reloc for the mn10300, offset by two bytes in the
-instruction.
-@end deffn
 @deffn {} BFD_RELOC_TIC30_LDP
 This is a 8bit DP reloc for the tms320c30, where the most
 significant 8 bits of a 24 bit word are placed into the least
 significant 8 bits of the opcode.
 @end deffn
 @deffn {} BFD_RELOC_TIC54X_PARTLS7
 This is a 7bit reloc for the tms320c54x, where the least
 significant 7 bits of a 16 bit word are placed into the least
 significant 7 bits of the opcode.
 @end deffn
@@ skipping 250 matching lines @@
 for absolute addressing with ldi with overflow check to linktime
 @end deffn
 @deffn {} BFD_RELOC_AVR_6
 This is a 6 bit reloc for the AVR that stores offset for ldd/std
 instructions
 @end deffn
 @deffn {} BFD_RELOC_AVR_6_ADIW
 This is a 6 bit reloc for the AVR that stores offset for adiw/sbiw
 instructions
 @end deffn
+@deffn {} BFD_RELOC_AVR_8_LO
+This is a 8 bit reloc for the AVR that stores bits 0..7 of a symbol
+in .byte lo8(symbol)
+@end deffn
+@deffn {} BFD_RELOC_AVR_8_HI
+This is a 8 bit reloc for the AVR that stores bits 8..15 of a symbol
+in .byte hi8(symbol)
+@end deffn
+@deffn {} BFD_RELOC_AVR_8_HLO
+This is a 8 bit reloc for the AVR that stores bits 16..23 of a symbol
+in .byte hlo8(symbol)
+@end deffn
 @deffn {} BFD_RELOC_RL78_NEG8
 @deffnx {} BFD_RELOC_RL78_NEG16
 @deffnx {} BFD_RELOC_RL78_NEG24
 @deffnx {} BFD_RELOC_RL78_NEG32
 @deffnx {} BFD_RELOC_RL78_16_OP
 @deffnx {} BFD_RELOC_RL78_24_OP
 @deffnx {} BFD_RELOC_RL78_32_OP
 @deffnx {} BFD_RELOC_RL78_8U
 @deffnx {} BFD_RELOC_RL78_16U
 @deffnx {} BFD_RELOC_RL78_24U
@@ skipping 149 matching lines @@
 @deffnx {} BFD_RELOC_390_TLS_DTPOFF
 @deffnx {} BFD_RELOC_390_TLS_TPOFF
 s390 tls relocations.
 @end deffn
 @deffn {} BFD_RELOC_390_20
 @deffnx {} BFD_RELOC_390_GOT20
 @deffnx {} BFD_RELOC_390_GOTPLT20
 @deffnx {} BFD_RELOC_390_TLS_GOTIE20
 Long displacement extension.
 @end deffn
+@deffn {} BFD_RELOC_390_IRELATIVE
+STT_GNU_IFUNC relocation.
+@end deffn
 @deffn {} BFD_RELOC_SCORE_GPREL15
 Score relocations
 Low 16 bit for load/store
 @end deffn
 @deffn {} BFD_RELOC_SCORE_DUMMY2
 @deffnx {} BFD_RELOC_SCORE_JMP
 This is a 24-bit reloc with the right 1 bit assumed to be 0
 @end deffn
 @deffn {} BFD_RELOC_SCORE_BRANCH
 This is a 19-bit reloc with the right 1 bit assumed to be 0
@@ skipping 194 matching lines @@
 @deffn {} BFD_RELOC_M68HC11_24
 Motorola 68HC11 reloc.
 This is a 24-bit reloc that represents the address with a 16-bit
 value and a 8-bit page number.  The symbol address is transformed
 to follow the 16K memory bank of 68HC12 (seen as mapped in the window).
 @end deffn
 @deffn {} BFD_RELOC_M68HC12_5B
 Motorola 68HC12 reloc.
 This is the 5 bits of a value.
 @end deffn
+@deffn {} BFD_RELOC_XGATE_RL_JUMP
+Freescale XGATE reloc.
+This reloc marks the beginning of a bra/jal instruction.
+@end deffn
+@deffn {} BFD_RELOC_XGATE_RL_GROUP
+Freescale XGATE reloc.
+This reloc marks a group of several instructions that gcc generates
+and for which the linker relaxation pass can modify and/or remove
+some of them.
+@end deffn
+@deffn {} BFD_RELOC_XGATE_LO16
+Freescale XGATE reloc.
+This is the 16-bit lower part of an address.  It is used for the '16-bit'
+instructions.
+@end deffn
+@deffn {} BFD_RELOC_XGATE_GPAGE
+Freescale XGATE reloc.
+@end deffn
+@deffn {} BFD_RELOC_XGATE_24
+Freescale XGATE reloc.
+@end deffn
+@deffn {} BFD_RELOC_XGATE_PCREL_9
+Freescale XGATE reloc.
+This is a 9-bit pc-relative reloc.
+@end deffn
+@deffn {} BFD_RELOC_XGATE_PCREL_10
+Freescale XGATE reloc.
+This is a 10-bit pc-relative reloc.
+@end deffn
+@deffn {} BFD_RELOC_XGATE_IMM8_LO
+Freescale XGATE reloc.
+This is the 16-bit lower part of an address.  It is used for the '16-bit'
+instructions.
+@end deffn
+@deffn {} BFD_RELOC_XGATE_IMM8_HI
+Freescale XGATE reloc.
+This is the 16-bit higher part of an address.  It is used for the '16-bit'
+instructions.
+@end deffn
+@deffn {} BFD_RELOC_XGATE_IMM3
+Freescale XGATE reloc.
+This is a 3-bit pc-relative reloc.
+@end deffn
+@deffn {} BFD_RELOC_XGATE_IMM4
+Freescale XGATE reloc.
+This is a 4-bit pc-relative reloc.
+@end deffn
+@deffn {} BFD_RELOC_XGATE_IMM5
+Freescale XGATE reloc.
+This is a 5-bit pc-relative reloc.
+@end deffn
+@deffn {} BFD_RELOC_M68HC12_9B
+Motorola 68HC12 reloc.
+This is the 9 bits of a value.
+@end deffn
+@deffn {} BFD_RELOC_M68HC12_16B
+Motorola 68HC12 reloc.
+This is the 16 bits of a value.
+@end deffn
+@deffn {} BFD_RELOC_M68HC12_9_PCREL
+Motorola 68HC12/XGATE reloc.
+This is a PCREL9 branch.
+@end deffn
+@deffn {} BFD_RELOC_M68HC12_10_PCREL
+Motorola 68HC12/XGATE reloc.
+This is a PCREL10 branch.
+@end deffn
+@deffn {} BFD_RELOC_M68HC12_LO8XG
+Motorola 68HC12/XGATE reloc.
+This is the 8 bit low part of an absolute address and immediately precedes
+a matching HI8XG part.
+@end deffn
+@deffn {} BFD_RELOC_M68HC12_HI8XG
+Motorola 68HC12/XGATE reloc.
+This is the 8 bit high part of an absolute address and immediately follows
+a matching LO8XG part.
+@end deffn
 @deffn {} BFD_RELOC_16C_NUM08
 @deffnx {} BFD_RELOC_16C_NUM08_C
 @deffnx {} BFD_RELOC_16C_NUM16
 @deffnx {} BFD_RELOC_16C_NUM16_C
 @deffnx {} BFD_RELOC_16C_NUM32
 @deffnx {} BFD_RELOC_16C_NUM32_C
 @deffnx {} BFD_RELOC_16C_DISP04
 @deffnx {} BFD_RELOC_16C_DISP04_C
 @deffnx {} BFD_RELOC_16C_DISP08
 @deffnx {} BFD_RELOC_16C_DISP08_C
@@ skipping 345 matching lines @@
 @deffnx {} BFD_RELOC_LM32_COPY
 @deffnx {} BFD_RELOC_LM32_GLOB_DAT
 @deffnx {} BFD_RELOC_LM32_JMP_SLOT
 @deffnx {} BFD_RELOC_LM32_RELATIVE
 Lattice Mico32 relocations.
 @end deffn
 @deffn {} BFD_RELOC_MACH_O_SECTDIFF
 Difference between two section addreses.  Must be followed by a
 BFD_RELOC_MACH_O_PAIR.
 @end deffn
+@deffn {} BFD_RELOC_MACH_O_LOCAL_SECTDIFF
+Like BFD_RELOC_MACH_O_SECTDIFF but with a local symbol.
+@end deffn
 @deffn {} BFD_RELOC_MACH_O_PAIR
 Pair of relocation.  Contains the first symbol.
 @end deffn
 @deffn {} BFD_RELOC_MACH_O_X86_64_BRANCH32
 @deffnx {} BFD_RELOC_MACH_O_X86_64_BRANCH8
 PCREL relocations.  They are marked as branch to create PLT entry if
 required.
 @end deffn
 @deffn {} BFD_RELOC_MACH_O_X86_64_GOT
 Used when referencing a GOT entry.
@@ skipping 109 matching lines @@
 @deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_GOT_HA
 @deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_GOT_HA
 @deffnx {} BFD_RELOC_TILEPRO_MMSTART_X0
 @deffnx {} BFD_RELOC_TILEPRO_MMEND_X0
 @deffnx {} BFD_RELOC_TILEPRO_MMSTART_X1
 @deffnx {} BFD_RELOC_TILEPRO_MMEND_X1
 @deffnx {} BFD_RELOC_TILEPRO_SHAMT_X0
 @deffnx {} BFD_RELOC_TILEPRO_SHAMT_X1
 @deffnx {} BFD_RELOC_TILEPRO_SHAMT_Y0
 @deffnx {} BFD_RELOC_TILEPRO_SHAMT_Y1
+@deffnx {} BFD_RELOC_TILEPRO_TLS_GD_CALL
+@deffnx {} BFD_RELOC_TILEPRO_IMM8_X0_TLS_GD_ADD
+@deffnx {} BFD_RELOC_TILEPRO_IMM8_X1_TLS_GD_ADD
+@deffnx {} BFD_RELOC_TILEPRO_IMM8_Y0_TLS_GD_ADD
+@deffnx {} BFD_RELOC_TILEPRO_IMM8_Y1_TLS_GD_ADD
+@deffnx {} BFD_RELOC_TILEPRO_TLS_IE_LOAD
 @deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_TLS_GD
 @deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_TLS_GD
 @deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_TLS_GD_LO
 @deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_TLS_GD_LO
 @deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_TLS_GD_HI
 @deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_TLS_GD_HI
 @deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_TLS_GD_HA
 @deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_TLS_GD_HA
 @deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_TLS_IE
 @deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_TLS_IE
 @deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_TLS_IE_LO
 @deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_TLS_IE_LO
 @deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_TLS_IE_HI
 @deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_TLS_IE_HI
 @deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_TLS_IE_HA
 @deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_TLS_IE_HA
 @deffnx {} BFD_RELOC_TILEPRO_TLS_DTPMOD32
 @deffnx {} BFD_RELOC_TILEPRO_TLS_DTPOFF32
 @deffnx {} BFD_RELOC_TILEPRO_TLS_TPOFF32
+@deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_TLS_LE
+@deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_TLS_LE
+@deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_TLS_LE_LO
+@deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_TLS_LE_LO
+@deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_TLS_LE_HI
+@deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_TLS_LE_HI
+@deffnx {} BFD_RELOC_TILEPRO_IMM16_X0_TLS_LE_HA
+@deffnx {} BFD_RELOC_TILEPRO_IMM16_X1_TLS_LE_HA
 Tilera TILEPro Relocations.
 @end deffn
 @deffn {} BFD_RELOC_TILEGX_HW0
 @deffnx {} BFD_RELOC_TILEGX_HW1
 @deffnx {} BFD_RELOC_TILEGX_HW2
 @deffnx {} BFD_RELOC_TILEGX_HW3
 @deffnx {} BFD_RELOC_TILEGX_HW0_LAST
 @deffnx {} BFD_RELOC_TILEGX_HW1_LAST
 @deffnx {} BFD_RELOC_TILEGX_HW2_LAST
 @deffnx {} BFD_RELOC_TILEGX_COPY
@@ skipping 39 matching lines @@
 @deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW3_PCREL
 @deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW3_PCREL
 @deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_PCREL
 @deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_PCREL
 @deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_PCREL
 @deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_PCREL
 @deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW2_LAST_PCREL
 @deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW2_LAST_PCREL
 @deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW0_GOT
 @deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW0_GOT
-@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW1_GOT
-@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW1_GOT
-@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW2_GOT
-@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW2_GOT
-@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW3_GOT
-@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW3_GOT
 @deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_GOT
 @deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_GOT
 @deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_GOT
 @deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_GOT
-@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW2_LAST_GOT
-@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW2_LAST_GOT
 @deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW0_TLS_GD
 @deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW0_TLS_GD
-@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW1_TLS_GD
-@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW1_TLS_GD
-@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW2_TLS_GD
-@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW2_TLS_GD
-@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW3_TLS_GD
-@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW3_TLS_GD
+@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW0_TLS_LE
+@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW0_TLS_LE
+@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_TLS_LE
+@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_TLS_LE
+@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_TLS_LE
+@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_TLS_LE
 @deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_TLS_GD
 @deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_TLS_GD
 @deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_TLS_GD
 @deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_TLS_GD
-@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW2_LAST_TLS_GD
-@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW2_LAST_TLS_GD
 @deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW0_TLS_IE
 @deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW0_TLS_IE
-@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW1_TLS_IE
-@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW1_TLS_IE
-@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW2_TLS_IE
-@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW2_TLS_IE
-@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW3_TLS_IE
-@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW3_TLS_IE
 @deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_TLS_IE
 @deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_TLS_IE
 @deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_TLS_IE
 @deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_TLS_IE
-@deffnx {} BFD_RELOC_TILEGX_IMM16_X0_HW2_LAST_TLS_IE
-@deffnx {} BFD_RELOC_TILEGX_IMM16_X1_HW2_LAST_TLS_IE
 @deffnx {} BFD_RELOC_TILEGX_TLS_DTPMOD64
 @deffnx {} BFD_RELOC_TILEGX_TLS_DTPOFF64
 @deffnx {} BFD_RELOC_TILEGX_TLS_TPOFF64
 @deffnx {} BFD_RELOC_TILEGX_TLS_DTPMOD32
 @deffnx {} BFD_RELOC_TILEGX_TLS_DTPOFF32
 @deffnx {} BFD_RELOC_TILEGX_TLS_TPOFF32
+@deffnx {} BFD_RELOC_TILEGX_TLS_GD_CALL
+@deffnx {} BFD_RELOC_TILEGX_IMM8_X0_TLS_GD_ADD
+@deffnx {} BFD_RELOC_TILEGX_IMM8_X1_TLS_GD_ADD
+@deffnx {} BFD_RELOC_TILEGX_IMM8_Y0_TLS_GD_ADD
+@deffnx {} BFD_RELOC_TILEGX_IMM8_Y1_TLS_GD_ADD
+@deffnx {} BFD_RELOC_TILEGX_TLS_IE_LOAD
+@deffnx {} BFD_RELOC_TILEGX_IMM8_X0_TLS_ADD
+@deffnx {} BFD_RELOC_TILEGX_IMM8_X1_TLS_ADD
+@deffnx {} BFD_RELOC_TILEGX_IMM8_Y0_TLS_ADD
+@deffnx {} BFD_RELOC_TILEGX_IMM8_Y1_TLS_ADD
 Tilera TILE-Gx Relocations.
 @end deffn
 @deffn {} BFD_RELOC_EPIPHANY_SIMM8
 Adapteva EPIPHANY - 8 bit signed pc-relative displacement
 @end deffn
 @deffn {} BFD_RELOC_EPIPHANY_SIMM24
 Adapteva EPIPHANY - 24 bit signed pc-relative displacement
 @end deffn
 @deffn {} BFD_RELOC_EPIPHANY_HIGH
 Adapteva EPIPHANY - 16 most-significant bits of absolute address
@@ skipping 71 matching lines @@
    (bfd *, struct bfd_link_info *);
 @end example
 @strong{Description}@*
 Provides default handling for relaxing for back ends which
 don't do section gc -- i.e., does nothing.
 
 @findex bfd_generic_lookup_section_flags
 @subsubsection @code{bfd_generic_lookup_section_flags}
 @strong{Synopsis}
 @example
-void bfd_generic_lookup_section_flags
-   (struct bfd_link_info *, struct flag_info *);
+bfd_boolean bfd_generic_lookup_section_flags
+   (struct bfd_link_info *, struct flag_info *, asection *);
 @end example
 @strong{Description}@*
 Provides default handling for section flags lookup
 -- i.e., does nothing.
+Returns FALSE if the section should be omitted, otherwise TRUE.
 
 @findex bfd_generic_merge_sections
 @subsubsection @code{bfd_generic_merge_sections}
 @strong{Synopsis}
 @example
 bfd_boolean bfd_generic_merge_sections
    (bfd *, struct bfd_link_info *);
 @end example
 @strong{Description}@*
 Provides default handling for SEC_MERGE section merging for back ends
 which don't have SEC_MERGE support -- i.e., does nothing.
 
 @findex bfd_generic_get_relocated_section_contents
 @subsubsection @code{bfd_generic_get_relocated_section_contents}
 @strong{Synopsis}
 @example
 bfd_byte *bfd_generic_get_relocated_section_contents
    (bfd *abfd,
     struct bfd_link_info *link_info,
     struct bfd_link_order *link_order,
     bfd_byte *data,
     bfd_boolean relocatable,
     asymbol **symbols);
 @end example
 @strong{Description}@*
 Provides default handling of relocation effort for back ends
 which can't be bothered to do it efficiently.