Index: src/mips/constants-mips.cc |
diff --git a/src/mips/constants-mips.cc b/src/mips/constants-mips.cc |
index bf272875e808bdf7d6eedbf42bda5e4aa1f315ef..0ef64f508d6c950f53c90c940cad6abaaba64c26 100644 |
--- a/src/mips/constants-mips.cc |
+++ b/src/mips/constants-mips.cc |
@@ -141,6 +141,8 @@ bool Instruction::IsForbiddenInBranchDelay() const { |
case BNEL: |
case BLEZL: |
case BGTZL: |
+ case BC: |
+ case BALC: |
return true; |
case REGIMM: |
switch (RtFieldRaw()) { |
@@ -173,6 +175,11 @@ bool Instruction::IsLinkingInstruction() const { |
switch (op) { |
case JAL: |
return true; |
+ case POP76: |
+ if (RsFieldRawNoAssert() == JIALC) |
+ return true; // JIALC |
+ else |
+ return false; // BNEZC |
case REGIMM: |
switch (RtFieldRaw()) { |
case BGEZAL: |
@@ -272,8 +279,25 @@ Instruction::Type Instruction::InstructionType() const { |
switch (FunctionFieldRaw()) { |
case INS: |
case EXT: |
- case BITSWAP: |
return kRegisterType; |
+ case BSHFL: { |
+ int sa = SaFieldRaw() >> kSaShift; |
+ switch (sa) { |
+ case BITSWAP: |
+ return kRegisterType; |
+ case WSBH: |
+ case SEB: |
+ case SEH: |
+ return kUnsupported; |
+ } |
+ sa >>= kBp2Bits; |
+ switch (sa) { |
+ case ALIGN: |
+ return kRegisterType; |
+ default: |
+ return kUnsupported; |
+ } |
+ } |
default: |
return kUnsupported; |
} |
@@ -309,8 +333,8 @@ Instruction::Type Instruction::InstructionType() const { |
case BNEL: |
case BLEZL: |
case BGTZL: |
- case BEQZC: |
- case BNEZC: |
+ case POP66: |
+ case POP76: |
case LB: |
case LH: |
case LWL: |
@@ -327,6 +351,9 @@ Instruction::Type Instruction::InstructionType() const { |
case LDC1: |
case SWC1: |
case SDC1: |
+ case PCREL: |
+ case BC: |
+ case BALC: |
return kImmediateType; |
// 26 bits immediate type instructions. e.g.: j imm26. |
case J: |