MIPS: Implemented PC-relative instructions for R6.

src/mips64/constants-mips64.cc

 // Copyright 2011 the V8 project authors. All rights reserved.
 // Use of this source code is governed by a BSD-style license that can be
 // found in the LICENSE file.
 
 #include "src/v8.h"
 
 #if V8_TARGET_ARCH_MIPS64
 
 #include "src/mips64/constants-mips64.h"
 
@@ skipping 123 matching lines @@
     case J:
     case JAL:
     case BEQ:
     case BNE:
     case BLEZ:
     case BGTZ:
     case BEQL:
     case BNEL:
     case BLEZL:
     case BGTZL:
+    case BC:
+    case BALC:
       return true;
     case REGIMM:
       switch (RtFieldRaw()) {
         case BLTZ:
         case BGEZ:
         case BLTZAL:
         case BGEZAL:
           return true;
         default:
           return false;
@@ skipping 12 matching lines @@
       return false;
   }
 }
 
 
 bool Instruction::IsLinkingInstruction() const {
   const int op = OpcodeFieldRaw();
   switch (op) {
     case JAL:
       return true;
+    case POP76:
+      if (RsFieldRawNoAssert() == JIALC)
+        return true;  // JIALC
+      else
+        return false;  // BNEZC
     case REGIMM:
       switch (RtFieldRaw()) {
         case BGEZAL:
         case BLTZAL:
           return true;
       default:
         return false;
       }
     case SPECIAL:
       switch (FunctionFieldRaw()) {
@@ skipping 97 matching lines @@
           return kRegisterType;
         default:
           return kUnsupported;
       }
       break;
     case SPECIAL3:
       switch (FunctionFieldRaw()) {
         case INS:
         case EXT:
         case DEXT:
-        case BITSWAP:
-        case DBITSWAP:
           return kRegisterType;
+        case BSHFL: {
+          int sa = SaFieldRaw() >> kSaShift;
+          switch (sa) {
+            case BITSWAP:
+              return kRegisterType;
+            case WSBH:
+            case SEB:
+            case SEH:
+              return kUnsupported;
+          }
+          sa >>= kBp2Bits;
+          switch (sa) {
+            case ALIGN:
+              return kRegisterType;
+            default:
+              return kUnsupported;
+          }
+        }
+        case DBSHFL: {
+          int sa = SaFieldRaw() >> kSaShift;
+          switch (sa) {
+            case DBITSWAP:
+              return kRegisterType;
+            case DSBH:
+            case DSHD:
+              return kUnsupported;
+          }
+          sa = SaFieldRaw() >> kSaShift;
+          sa >>= kBp3Bits;
+          switch (sa) {
+            case DALIGN:
+              return kRegisterType;
+            default:
+              return kUnsupported;
+          }
+        }
         default:
           return kUnsupported;
       }
       break;
     case COP1:    // Coprocessor instructions.
       switch (RsFieldRawNoAssert()) {
         case BC1:   // Branch on coprocessor condition.
         case BC1EQZ:
         case BC1NEZ:
           return kImmediateType;
@@ skipping 16 matching lines @@
     case SLTI:
     case SLTIU:
     case ANDI:
     case ORI:
     case XORI:
     case LUI:
     case BEQL:
     case BNEL:
     case BLEZL:
     case BGTZL:
-    case BEQZC:
-    case BNEZC:
+    case POP66:
+    case POP76:
     case LB:
     case LH:
     case LWL:
     case LW:
     case LWU:
     case LD:
     case LBU:
     case LHU:
     case LWR:
     case SB:
     case SH:
     case SWL:
     case SW:
     case SD:
     case SWR:
     case LWC1:
     case LDC1:
     case SWC1:
     case SDC1:
+    case PCREL:
+    case BC:
+    case BALC:
       return kImmediateType;
     // 26 bits immediate type instructions. e.g.: j imm26.
     case J:
     case JAL:
       return kJumpType;
     default:
       return kUnsupported;
   }
   return kUnsupported;
 }
 
 
 }  // namespace internal
 }  // namespace v8
 
 #endif  // V8_TARGET_ARCH_MIPS64