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Side by Side Diff: src/mips/disasm-mips.cc

Issue 1195793002: MIPS: Implemented PC-relative instructions for R6. (Closed) Base URL: https://chromium.googlesource.com/v8/v8.git@master
Patch Set: Created 5 years, 6 months ago
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1 // Copyright 2012 the V8 project authors. All rights reserved. 1 // Copyright 2012 the V8 project authors. All rights reserved.
2 // Use of this source code is governed by a BSD-style license that can be 2 // Use of this source code is governed by a BSD-style license that can be
3 // found in the LICENSE file. 3 // found in the LICENSE file.
4 4
5 // A Disassembler object is used to disassemble a block of code instruction by 5 // A Disassembler object is used to disassemble a block of code instruction by
6 // instruction. The default implementation of the NameConverter object can be 6 // instruction. The default implementation of the NameConverter object can be
7 // overriden to modify register names or to do symbol lookup on addresses. 7 // overriden to modify register names or to do symbol lookup on addresses.
8 // 8 //
9 // The example below will disassemble a block of code and print it to stdout. 9 // The example below will disassemble a block of code and print it to stdout.
10 // 10 //
(...skipping 63 matching lines...) Expand 10 before | Expand all | Expand 10 after
74 void PrintRd(Instruction* instr); 74 void PrintRd(Instruction* instr);
75 void PrintFs(Instruction* instr); 75 void PrintFs(Instruction* instr);
76 void PrintFt(Instruction* instr); 76 void PrintFt(Instruction* instr);
77 void PrintFd(Instruction* instr); 77 void PrintFd(Instruction* instr);
78 void PrintSa(Instruction* instr); 78 void PrintSa(Instruction* instr);
79 void PrintSd(Instruction* instr); 79 void PrintSd(Instruction* instr);
80 void PrintSs1(Instruction* instr); 80 void PrintSs1(Instruction* instr);
81 void PrintSs2(Instruction* instr); 81 void PrintSs2(Instruction* instr);
82 void PrintBc(Instruction* instr); 82 void PrintBc(Instruction* instr);
83 void PrintCc(Instruction* instr); 83 void PrintCc(Instruction* instr);
84 void PrintBp2(Instruction* instr);
84 void PrintFunction(Instruction* instr); 85 void PrintFunction(Instruction* instr);
85 void PrintSecondaryField(Instruction* instr); 86 void PrintSecondaryField(Instruction* instr);
86 void PrintUImm16(Instruction* instr); 87 void PrintUImm16(Instruction* instr);
87 void PrintSImm16(Instruction* instr); 88 void PrintSImm16(Instruction* instr);
88 void PrintXImm16(Instruction* instr); 89 void PrintXImm16(Instruction* instr);
90 void PrintXImm18(Instruction* instr);
91 void PrintSImm18(Instruction* instr);
92 void PrintXImm19(Instruction* instr);
93 void PrintSImm19(Instruction* instr);
89 void PrintXImm21(Instruction* instr); 94 void PrintXImm21(Instruction* instr);
95 void PrintSImm21(Instruction* instr);
90 void PrintXImm26(Instruction* instr); 96 void PrintXImm26(Instruction* instr);
97 void PrintSImm26(Instruction* instr);
91 void PrintCode(Instruction* instr); // For break and trap instructions. 98 void PrintCode(Instruction* instr); // For break and trap instructions.
92 void PrintFormat(Instruction* instr); // For floating format postfix. 99 void PrintFormat(Instruction* instr); // For floating format postfix.
93 // Printing of instruction name. 100 // Printing of instruction name.
94 void PrintInstructionName(Instruction* instr); 101 void PrintInstructionName(Instruction* instr);
95 102
96 // Handle formatting of instructions and their options. 103 // Handle formatting of instructions and their options.
97 int FormatRegister(Instruction* instr, const char* option); 104 int FormatRegister(Instruction* instr, const char* option);
98 int FormatFPURegister(Instruction* instr, const char* option); 105 int FormatFPURegister(Instruction* instr, const char* option);
99 int FormatOption(Instruction* instr, const char* option); 106 int FormatOption(Instruction* instr, const char* option);
100 void Format(Instruction* instr, const char* format); 107 void Format(Instruction* instr, const char* format);
(...skipping 128 matching lines...) Expand 10 before | Expand all | Expand 10 after
229 } 236 }
230 237
231 238
232 // Print the integer value of the cc field for the FP compare instructions. 239 // Print the integer value of the cc field for the FP compare instructions.
233 void Decoder::PrintCc(Instruction* instr) { 240 void Decoder::PrintCc(Instruction* instr) {
234 int cc = instr->FCccValue(); 241 int cc = instr->FCccValue();
235 out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_, "cc(%d)", cc); 242 out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_, "cc(%d)", cc);
236 } 243 }
237 244
238 245
246 void Decoder::PrintBp2(Instruction* instr) {
247 int bp2 = instr->Bp2Value();
248 out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_, "%d", bp2);
249 }
250
251
239 // Print 16-bit unsigned immediate value. 252 // Print 16-bit unsigned immediate value.
240 void Decoder::PrintUImm16(Instruction* instr) { 253 void Decoder::PrintUImm16(Instruction* instr) {
241 int32_t imm = instr->Imm16Value(); 254 int32_t imm = instr->Imm16Value();
242 out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_, "%u", imm); 255 out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_, "%u", imm);
243 } 256 }
244 257
245 258
246 // Print 16-bit signed immediate value. 259 // Print 16-bit signed immediate value.
247 void Decoder::PrintSImm16(Instruction* instr) { 260 void Decoder::PrintSImm16(Instruction* instr) {
248 int32_t imm = ((instr->Imm16Value()) << 16) >> 16; 261 int32_t imm = ((instr->Imm16Value()) << 16) >> 16;
249 out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_, "%d", imm); 262 out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_, "%d", imm);
250 } 263 }
251 264
252 265
253 // Print 16-bit hexa immediate value. 266 // Print 16-bit hexa immediate value.
254 void Decoder::PrintXImm16(Instruction* instr) { 267 void Decoder::PrintXImm16(Instruction* instr) {
255 int32_t imm = instr->Imm16Value(); 268 int32_t imm = instr->Imm16Value();
256 out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_, "0x%x", imm); 269 out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_, "0x%x", imm);
257 } 270 }
258 271
259 272
273 // Print 18-bit signed immediate value.
274 void Decoder::PrintSImm18(Instruction* instr) {
275 int32_t imm =
276 ((instr->Imm18Value()) << (32 - kImm18Bits)) >> (32 - kImm18Bits);
277 out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_, "%d", imm);
278 }
279
280
281 // Print 18-bit hexa immediate value.
282 void Decoder::PrintXImm18(Instruction* instr) {
283 int32_t imm = instr->Imm18Value();
284 out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_, "0x%x", imm);
285 }
286
287
288 // Print 19-bit hexa immediate value.
289 void Decoder::PrintXImm19(Instruction* instr) {
290 int32_t imm = instr->Imm19Value();
291 out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_, "0x%x", imm);
292 }
293
294
295 // Print 19-bit signed immediate value.
296 void Decoder::PrintSImm19(Instruction* instr) {
297 int32_t imm19 = instr->Imm19Value();
298 // set sign
299 imm19 <<= (32 - kImm19Bits);
300 imm19 >>= (32 - kImm19Bits);
301 out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_, "%d", imm19);
302 }
303
304
260 // Print 21-bit immediate value. 305 // Print 21-bit immediate value.
261 void Decoder::PrintXImm21(Instruction* instr) { 306 void Decoder::PrintXImm21(Instruction* instr) {
262 uint32_t imm = instr->Imm21Value(); 307 uint32_t imm = instr->Imm21Value();
263 out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_, "0x%x", imm); 308 out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_, "0x%x", imm);
264 } 309 }
265 310
266 311
267 // Print 26-bit immediate value. 312 // Print 21-bit signed immediate value.
313 void Decoder::PrintSImm21(Instruction* instr) {
314 int32_t imm21 = instr->Imm21Value();
315 // set sign
316 imm21 <<= (32 - kImm21Bits);
317 imm21 >>= (32 - kImm21Bits);
318 out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_, "%d", imm21);
319 }
320
321
322 // Print 26-bit hex immediate value.
268 void Decoder::PrintXImm26(Instruction* instr) { 323 void Decoder::PrintXImm26(Instruction* instr) {
269 uint32_t imm = instr->Imm26Value() << kImmFieldShift; 324 uint32_t imm = instr->Imm26Value() << kImmFieldShift;
270 out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_, "0x%x", imm); 325 out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_, "0x%x", imm);
271 } 326 }
272 327
273 328
329 // Print 26-bit signed immediate value.
330 void Decoder::PrintSImm26(Instruction* instr) {
331 int32_t imm26 = instr->Imm26Value();
332 // set sign
333 imm26 <<= (32 - kImm26Bits);
334 imm26 >>= (32 - kImm26Bits);
335 out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_, "%d", imm26);
336 }
337
338
274 // Print 26-bit immediate value. 339 // Print 26-bit immediate value.
275 void Decoder::PrintCode(Instruction* instr) { 340 void Decoder::PrintCode(Instruction* instr) {
276 if (instr->OpcodeFieldRaw() != SPECIAL) 341 if (instr->OpcodeFieldRaw() != SPECIAL)
277 return; // Not a break or trap instruction. 342 return; // Not a break or trap instruction.
278 switch (instr->FunctionFieldRaw()) { 343 switch (instr->FunctionFieldRaw()) {
279 case BREAK: { 344 case BREAK: {
280 int32_t code = instr->Bits(25, 6); 345 int32_t code = instr->Bits(25, 6);
281 out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_, 346 out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_,
282 "0x%05x (%d)", code, code); 347 "0x%05x (%d)", code, code);
283 break; 348 break;
(...skipping 98 matching lines...) Expand 10 before | Expand all | Expand 10 after
382 // characters that were consumed from the formatting string. 447 // characters that were consumed from the formatting string.
383 int Decoder::FormatOption(Instruction* instr, const char* format) { 448 int Decoder::FormatOption(Instruction* instr, const char* format) {
384 switch (format[0]) { 449 switch (format[0]) {
385 case 'c': { // 'code for break or trap instructions. 450 case 'c': { // 'code for break or trap instructions.
386 DCHECK(STRING_STARTS_WITH(format, "code")); 451 DCHECK(STRING_STARTS_WITH(format, "code"));
387 PrintCode(instr); 452 PrintCode(instr);
388 return 4; 453 return 4;
389 } 454 }
390 case 'i': { // 'imm16u or 'imm26. 455 case 'i': { // 'imm16u or 'imm26.
391 if (format[3] == '1') { 456 if (format[3] == '1') {
392 DCHECK(STRING_STARTS_WITH(format, "imm16")); 457 if (format[4] == '6') {
393 if (format[5] == 's') { 458 DCHECK(STRING_STARTS_WITH(format, "imm16"));
394 DCHECK(STRING_STARTS_WITH(format, "imm16s")); 459 switch (format[5]) {
395 PrintSImm16(instr); 460 case 's':
396 } else if (format[5] == 'u') { 461 DCHECK(STRING_STARTS_WITH(format, "imm16s"));
397 DCHECK(STRING_STARTS_WITH(format, "imm16u")); 462 PrintSImm16(instr);
398 PrintSImm16(instr); 463 break;
399 } else { 464 case 'u':
400 DCHECK(STRING_STARTS_WITH(format, "imm16x")); 465 DCHECK(STRING_STARTS_WITH(format, "imm16u"));
401 PrintXImm16(instr); 466 PrintSImm16(instr);
467 break;
468 case 'x':
469 DCHECK(STRING_STARTS_WITH(format, "imm16x"));
470 PrintXImm16(instr);
471 break;
472 }
473 return 6;
474 } else if (format[4] == '8') {
475 DCHECK(STRING_STARTS_WITH(format, "imm18"));
476 switch (format[5]) {
477 case 's':
478 DCHECK(STRING_STARTS_WITH(format, "imm18s"));
479 PrintSImm18(instr);
480 break;
481 case 'x':
482 DCHECK(STRING_STARTS_WITH(format, "imm18x"));
483 PrintXImm18(instr);
484 break;
485 }
486 return 6;
487 } else if (format[4] == '9') {
488 DCHECK(STRING_STARTS_WITH(format, "imm19"));
489 switch (format[5]) {
490 case 's':
491 DCHECK(STRING_STARTS_WITH(format, "imm19s"));
492 PrintSImm19(instr);
493 break;
494 case 'x':
495 DCHECK(STRING_STARTS_WITH(format, "imm19x"));
496 PrintXImm19(instr);
497 break;
498 }
499 return 6;
500 }
501 } else if (format[3] == '2' && format[4] == '1') {
502 DCHECK(STRING_STARTS_WITH(format, "imm21"));
503 switch (format[5]) {
504 case 's':
505 DCHECK(STRING_STARTS_WITH(format, "imm21s"));
506 PrintSImm21(instr);
507 break;
508 case 'x':
509 DCHECK(STRING_STARTS_WITH(format, "imm21x"));
510 PrintXImm21(instr);
511 break;
402 } 512 }
403 return 6; 513 return 6;
404 } else if (format[3] == '2' && format[4] == '1') {
405 DCHECK(STRING_STARTS_WITH(format, "imm21x"));
406 PrintXImm21(instr);
407 return 6;
408 } else if (format[3] == '2' && format[4] == '6') { 514 } else if (format[3] == '2' && format[4] == '6') {
409 DCHECK(STRING_STARTS_WITH(format, "imm26x")); 515 DCHECK(STRING_STARTS_WITH(format, "imm26"));
410 PrintXImm26(instr); 516 switch (format[5]) {
517 case 's':
518 DCHECK(STRING_STARTS_WITH(format, "imm26s"));
519 PrintSImm26(instr);
520 break;
521 case 'x':
522 DCHECK(STRING_STARTS_WITH(format, "imm26x"));
523 PrintXImm26(instr);
524 break;
525 }
411 return 6; 526 return 6;
412 } 527 }
413 } 528 }
414 case 'r': { // 'r: registers. 529 case 'r': { // 'r: registers.
415 return FormatRegister(instr, format); 530 return FormatRegister(instr, format);
416 } 531 }
417 case 'f': { // 'f: FPUregisters. 532 case 'f': { // 'f: FPUregisters.
418 return FormatFPURegister(instr, format); 533 return FormatFPURegister(instr, format);
419 } 534 }
420 case 's': { // 'sa. 535 case 's': { // 'sa.
(...skipping 14 matching lines...) Expand all
435 PrintSs1(instr); 550 PrintSs1(instr);
436 return 3; 551 return 3;
437 } else { 552 } else {
438 DCHECK(STRING_STARTS_WITH(format, "ss2")); /* ins size */ 553 DCHECK(STRING_STARTS_WITH(format, "ss2")); /* ins size */
439 PrintSs2(instr); 554 PrintSs2(instr);
440 return 3; 555 return 3;
441 } 556 }
442 } 557 }
443 } 558 }
444 } 559 }
445 case 'b': { // 'bc - Special for bc1 cc field. 560 case 'b': {
446 DCHECK(STRING_STARTS_WITH(format, "bc")); 561 switch (format[1]) {
447 PrintBc(instr); 562 case 'c': { // 'bc - Special for bc1 cc field.
448 return 2; 563 DCHECK(STRING_STARTS_WITH(format, "bc"));
564 PrintBc(instr);
565 return 2;
566 }
567 case 'p': {
568 switch (format[2]) {
569 case '2': { // 'bp2
570 DCHECK(STRING_STARTS_WITH(format, "bp2"));
571 PrintBp2(instr);
572 return 3;
573 }
574 }
575 }
576 }
449 } 577 }
450 case 'C': { // 'Cc - Special for c.xx.d cc field. 578 case 'C': { // 'Cc - Special for c.xx.d cc field.
451 DCHECK(STRING_STARTS_WITH(format, "Cc")); 579 DCHECK(STRING_STARTS_WITH(format, "Cc"));
452 PrintCc(instr); 580 PrintCc(instr);
453 return 2; 581 return 2;
454 } 582 }
455 case 't': 583 case 't':
456 PrintFormat(instr); 584 PrintFormat(instr);
457 return 1; 585 return 1;
458 } 586 }
(...skipping 475 matching lines...) Expand 10 before | Expand all | Expand 10 after
934 break; 1062 break;
935 default: 1063 default:
936 UNREACHABLE(); 1064 UNREACHABLE();
937 } 1065 }
938 } 1066 }
939 1067
940 1068
941 void Decoder::DecodeTypeRegisterSPECIAL3(Instruction* instr) { 1069 void Decoder::DecodeTypeRegisterSPECIAL3(Instruction* instr) {
942 switch (instr->FunctionFieldRaw()) { 1070 switch (instr->FunctionFieldRaw()) {
943 case INS: { 1071 case INS: {
944 if (IsMipsArchVariant(kMips32r2)) { 1072 if (IsMipsArchVariant(kMips32r2) || IsMipsArchVariant(kMips32r6)) {
945 Format(instr, "ins 'rt, 'rs, 'sa, 'ss2"); 1073 Format(instr, "ins 'rt, 'rs, 'sa, 'ss2");
946 } else { 1074 } else {
947 Unknown(instr); 1075 Unknown(instr);
948 } 1076 }
949 break; 1077 break;
950 } 1078 }
951 case EXT: { 1079 case EXT: {
952 if (IsMipsArchVariant(kMips32r2)) { 1080 if (IsMipsArchVariant(kMips32r2) || IsMipsArchVariant(kMips32r6)) {
953 Format(instr, "ext 'rt, 'rs, 'sa, 'ss1"); 1081 Format(instr, "ext 'rt, 'rs, 'sa, 'ss1");
954 } else { 1082 } else {
955 Unknown(instr); 1083 Unknown(instr);
956 } 1084 }
957 break; 1085 break;
958 } 1086 }
959 case BITSWAP: { 1087 case BSHFL: {
960 if (IsMipsArchVariant(kMips32r6)) { 1088 int sa = instr->SaFieldRaw() >> kSaShift;
961 Format(instr, "bitswap 'rd, 'rt"); 1089 switch (sa) {
962 } else { 1090 case BITSWAP: {
963 Unknown(instr); 1091 if (IsMipsArchVariant(kMips32r6)) {
1092 Format(instr, "bitswap 'rd, 'rt");
1093 } else {
1094 Unknown(instr);
1095 }
1096 break;
1097 }
1098 case SEB:
1099 case SEH:
1100 case WSBH:
1101 UNREACHABLE();
1102 break;
1103 default: {
1104 sa >>= kBp2Bits;
1105 switch (sa) {
1106 case ALIGN: {
1107 if (IsMipsArchVariant(kMips32r6)) {
1108 Format(instr, "align 'rd, 'rs, 'rt, 'bp2");
1109 } else {
1110 Unknown(instr);
1111 }
1112 break;
1113 }
1114 default:
1115 UNREACHABLE();
1116 break;
1117 }
1118 }
964 } 1119 }
965 break; 1120 break;
966 } 1121 }
967 default: 1122 default:
968 UNREACHABLE(); 1123 UNREACHABLE();
969 } 1124 }
970 } 1125 }
971 1126
972 1127
973 void Decoder::DecodeTypeRegister(Instruction* instr) { 1128 void Decoder::DecodeTypeRegister(Instruction* instr) {
(...skipping 106 matching lines...) Expand 10 before | Expand all | Expand 10 after
1080 Format(instr, "bgezall 'rs, 'imm16u"); 1235 Format(instr, "bgezall 'rs, 'imm16u");
1081 break; 1236 break;
1082 default: 1237 default:
1083 UNREACHABLE(); 1238 UNREACHABLE();
1084 } 1239 }
1085 break; // Case REGIMM. 1240 break; // Case REGIMM.
1086 // ------------- Branch instructions. 1241 // ------------- Branch instructions.
1087 case BEQ: 1242 case BEQ:
1088 Format(instr, "beq 'rs, 'rt, 'imm16u"); 1243 Format(instr, "beq 'rs, 'rt, 'imm16u");
1089 break; 1244 break;
1245 case BC:
1246 Format(instr, "bc 'imm26s");
1247 break;
1248 case BALC:
1249 Format(instr, "balc 'imm26s");
1250 break;
1090 case BNE: 1251 case BNE:
1091 Format(instr, "bne 'rs, 'rt, 'imm16u"); 1252 Format(instr, "bne 'rs, 'rt, 'imm16u");
1092 break; 1253 break;
1093 case BLEZ: 1254 case BLEZ:
1094 if ((instr->RtFieldRaw() == 0) 1255 if ((instr->RtFieldRaw() == 0)
1095 && (instr->RsFieldRaw() != 0)) { 1256 && (instr->RsFieldRaw() != 0)) {
1096 Format(instr, "blez 'rs, 'imm16u"); 1257 Format(instr, "blez 'rs, 'imm16u");
1097 } else if ((instr->RtFieldRaw() != instr->RsFieldRaw()) 1258 } else if ((instr->RtFieldRaw() != instr->RsFieldRaw())
1098 && (instr->RsFieldRaw() != 0) && (instr->RtFieldRaw() != 0)) { 1259 && (instr->RsFieldRaw() != 0) && (instr->RtFieldRaw() != 0)) {
1099 Format(instr, "bgeuc 'rs, 'rt, 'imm16u"); 1260 Format(instr, "bgeuc 'rs, 'rt, 'imm16u");
(...skipping 45 matching lines...) Expand 10 before | Expand all | Expand 10 after
1145 } else if ((instr->RtFieldRaw() != instr->RsFieldRaw()) 1306 } else if ((instr->RtFieldRaw() != instr->RsFieldRaw())
1146 && (instr->RsFieldRaw() != 0) && (instr->RtFieldRaw() != 0)) { 1307 && (instr->RsFieldRaw() != 0) && (instr->RtFieldRaw() != 0)) {
1147 Format(instr, "bltc 'rs, 'rt, 'imm16u"); 1308 Format(instr, "bltc 'rs, 'rt, 'imm16u");
1148 } else if ((instr->RsFieldRaw() == 0) 1309 } else if ((instr->RsFieldRaw() == 0)
1149 && (instr->RtFieldRaw() != 0)) { 1310 && (instr->RtFieldRaw() != 0)) {
1150 Format(instr, "bgtzc 'rt, 'imm16u"); 1311 Format(instr, "bgtzc 'rt, 'imm16u");
1151 } else { 1312 } else {
1152 UNREACHABLE(); 1313 UNREACHABLE();
1153 } 1314 }
1154 break; 1315 break;
1155 case BEQZC: 1316 case POP66:
1156 if (instr->RsFieldRaw() != 0) { 1317 if (instr->RsValue() == JIC) {
1157 Format(instr, "beqzc 'rs, 'imm21x"); 1318 Format(instr, "jic 'rt, 'imm16s");
1319 } else {
1320 Format(instr, "beqzc 'rs, 'imm21s");
1158 } 1321 }
1159 break; 1322 break;
1160 case BNEZC: 1323 case POP76:
1161 if (instr->RsFieldRaw() != 0) { 1324 if (instr->RsValue() == JIALC) {
1325 Format(instr, "jialc 'rt, 'imm16x");
1326 } else {
1162 Format(instr, "bnezc 'rs, 'imm21x"); 1327 Format(instr, "bnezc 'rs, 'imm21x");
1163 } 1328 }
1164 break; 1329 break;
1165 // ------------- Arithmetic instructions. 1330 // ------------- Arithmetic instructions.
1166 case ADDI: 1331 case ADDI:
1167 if (!IsMipsArchVariant(kMips32r6)) { 1332 if (!IsMipsArchVariant(kMips32r6)) {
1168 Format(instr, "addi 'rt, 'rs, 'imm16s"); 1333 Format(instr, "addi 'rt, 'rs, 'imm16s");
1169 } else { 1334 } else {
1170 // Check if BOVC or BEQC instruction. 1335 // Check if BOVC or BEQC instruction.
1171 if (instr->RsFieldRaw() >= instr->RtFieldRaw()) { 1336 if (instr->RsFieldRaw() >= instr->RtFieldRaw()) {
(...skipping 91 matching lines...) Expand 10 before | Expand all | Expand 10 after
1263 break; 1428 break;
1264 case LDC1: 1429 case LDC1:
1265 Format(instr, "ldc1 'ft, 'imm16s('rs)"); 1430 Format(instr, "ldc1 'ft, 'imm16s('rs)");
1266 break; 1431 break;
1267 case SWC1: 1432 case SWC1:
1268 Format(instr, "swc1 'ft, 'imm16s('rs)"); 1433 Format(instr, "swc1 'ft, 'imm16s('rs)");
1269 break; 1434 break;
1270 case SDC1: 1435 case SDC1:
1271 Format(instr, "sdc1 'ft, 'imm16s('rs)"); 1436 Format(instr, "sdc1 'ft, 'imm16s('rs)");
1272 break; 1437 break;
1438 case PCREL: {
1439 int32_t imm21 = instr->Imm21Value();
1440 // rt field: 5-bits checking
1441 uint8_t rt = (imm21 >> kImm16Bits);
1442 switch (rt) {
1443 case ALUIPC:
1444 Format(instr, "aluipc 'rs, 'imm16s");
1445 break;
1446 case AUIPC:
1447 Format(instr, "auipc 'rs, 'imm16s");
1448 break;
1449 default: {
1450 // rt field: checking of the most significant 2-bits
1451 rt = (imm21 >> kImm19Bits);
1452 switch (rt) {
1453 case LWPC:
1454 Format(instr, "lwpc 'rs, 'imm19s");
1455 break;
1456 case ADDIUPC:
1457 Format(instr, "addiupc 'rs, 'imm19s");
1458 break;
1459 default:
1460 UNREACHABLE();
1461 break;
1462 }
1463 }
1464 }
1465 break;
1466 }
1273 default: 1467 default:
1274 printf("a 0x%x \n", instr->OpcodeFieldRaw()); 1468 printf("a 0x%x \n", instr->OpcodeFieldRaw());
1275 UNREACHABLE(); 1469 UNREACHABLE();
1276 break; 1470 break;
1277 } 1471 }
1278 } 1472 }
1279 1473
1280 1474
1281 void Decoder::DecodeTypeJump(Instruction* instr) { 1475 void Decoder::DecodeTypeJump(Instruction* instr) {
1282 switch (instr->OpcodeFieldRaw()) { 1476 switch (instr->OpcodeFieldRaw()) {
(...skipping 114 matching lines...) Expand 10 before | Expand all | Expand 10 after
1397 prev_pc, *reinterpret_cast<int32_t*>(prev_pc), buffer.start()); 1591 prev_pc, *reinterpret_cast<int32_t*>(prev_pc), buffer.start());
1398 } 1592 }
1399 } 1593 }
1400 1594
1401 1595
1402 #undef UNSUPPORTED 1596 #undef UNSUPPORTED
1403 1597
1404 } // namespace disasm 1598 } // namespace disasm
1405 1599
1406 #endif // V8_TARGET_ARCH_MIPS 1600 #endif // V8_TARGET_ARCH_MIPS
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