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| 1 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file | 1 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file |
| 2 // for details. All rights reserved. Use of this source code is governed by a | 2 // for details. All rights reserved. Use of this source code is governed by a |
| 3 // BSD-style license that can be found in the LICENSE file. | 3 // BSD-style license that can be found in the LICENSE file. |
| 4 | 4 |
| 5 #include "vm/globals.h" // Needed here to get TARGET_ARCH_ARM. | 5 #include "vm/globals.h" // Needed here to get TARGET_ARCH_ARM. |
| 6 #if defined(TARGET_ARCH_ARM) | 6 #if defined(TARGET_ARCH_ARM) |
| 7 | 7 |
| 8 #include "vm/assembler.h" | 8 #include "vm/assembler.h" |
| 9 #include "vm/constants_arm.h" | 9 #include "vm/constants_arm.h" |
| 10 #include "vm/cpu.h" | 10 #include "vm/cpu.h" |
| 11 #include "vm/instructions.h" | 11 #include "vm/instructions.h" |
| 12 #include "vm/object.h" | 12 #include "vm/object.h" |
| 13 | 13 |
| 14 namespace dart { | 14 namespace dart { |
| 15 | 15 |
| 16 CallPattern::CallPattern(uword pc, const Code& code) | 16 CallPattern::CallPattern(uword pc, const Code& code) |
| 17 : object_pool_(ObjectPool::Handle(code.GetObjectPool())), | 17 : object_pool_(ObjectPool::Handle(code.GetObjectPool())), |
| 18 end_(pc), | 18 end_(pc), |
| 19 ic_data_load_end_(0), | 19 ic_data_load_end_(0), |
| 20 target_address_pool_index_(-1), | 20 target_code_pool_index_(-1), |
| 21 ic_data_(ICData::Handle()) { | 21 ic_data_(ICData::Handle()) { |
| 22 ASSERT(code.ContainsInstructionAt(pc)); | 22 ASSERT(code.ContainsInstructionAt(pc)); |
| 23 // Last instruction: blx lr. | 23 // Last instruction: blx lr. |
| 24 ASSERT(*(reinterpret_cast<uword*>(end_) - 1) == 0xe12fff3e); | 24 ASSERT(*(reinterpret_cast<uword*>(end_) - 1) == 0xe12fff3e); |
| 25 | 25 |
| 26 Register reg; | 26 Register reg; |
| 27 ic_data_load_end_ = | 27 ic_data_load_end_ = |
| 28 InstructionPattern::DecodeLoadWordFromPool(end_ - Instr::kInstrSize, | 28 InstructionPattern::DecodeLoadWordFromPool(end_ - 2 * Instr::kInstrSize, |
| 29 ®, | 29 ®, |
| 30 &target_address_pool_index_); | 30 &target_code_pool_index_); |
| 31 ASSERT(reg == LR); | 31 ASSERT(reg == CODE_REG); |
| 32 } | 32 } |
| 33 | 33 |
| 34 | 34 |
| 35 int CallPattern::LengthInBytes() { | 35 int CallPattern::DeoptCallPatternLengthInBytes() { |
| 36 const ARMVersion version = TargetCPUFeatures::arm_version(); | 36 const ARMVersion version = TargetCPUFeatures::arm_version(); |
| 37 if ((version == ARMv5TE) || (version == ARMv6)) { | 37 if ((version == ARMv5TE) || (version == ARMv6)) { |
| 38 return 5 * Instr::kInstrSize; | 38 return 5 * Instr::kInstrSize; |
| 39 } else { | 39 } else { |
| 40 ASSERT(version == ARMv7); | 40 ASSERT(version == ARMv7); |
| 41 return 3 * Instr::kInstrSize; | 41 return 3 * Instr::kInstrSize; |
| 42 } | 42 } |
| 43 } | 43 } |
| 44 | 44 |
| 45 | 45 |
| 46 NativeCallPattern::NativeCallPattern(uword pc, const Code& code) | 46 NativeCallPattern::NativeCallPattern(uword pc, const Code& code) |
| 47 : object_pool_(ObjectPool::Handle(code.GetObjectPool())), | 47 : object_pool_(ObjectPool::Handle(code.GetObjectPool())), |
| 48 end_(pc), | 48 end_(pc), |
| 49 native_function_pool_index_(-1), | 49 native_function_pool_index_(-1), |
| 50 target_address_pool_index_(-1) { | 50 target_code_pool_index_(-1) { |
| 51 ASSERT(code.ContainsInstructionAt(pc)); | 51 ASSERT(code.ContainsInstructionAt(pc)); |
| 52 // Last instruction: blx lr. | 52 // Last instruction: blx lr. |
| 53 ASSERT(*(reinterpret_cast<uword*>(end_) - 1) == 0xe12fff3e); | 53 ASSERT(*(reinterpret_cast<uword*>(end_) - 1) == 0xe12fff3e); |
| 54 | 54 |
| 55 Register reg; | 55 Register reg; |
| 56 uword native_function_load_end = | 56 uword native_function_load_end = |
| 57 InstructionPattern::DecodeLoadWordFromPool(end_ - Instr::kInstrSize, | 57 InstructionPattern::DecodeLoadWordFromPool(end_ - 2 * Instr::kInstrSize, |
| 58 ®, | 58 ®, |
| 59 &target_address_pool_index_); | 59 &target_code_pool_index_); |
| 60 ASSERT(reg == LR); | 60 ASSERT(reg == CODE_REG); |
| 61 InstructionPattern::DecodeLoadWordFromPool(native_function_load_end, | 61 InstructionPattern::DecodeLoadWordFromPool(native_function_load_end, |
| 62 ®, | 62 ®, |
| 63 &native_function_pool_index_); | 63 &native_function_pool_index_); |
| 64 ASSERT(reg == R5); | 64 ASSERT(reg == R5); |
| 65 } | 65 } |
| 66 | 66 |
| 67 | 67 |
| 68 uword NativeCallPattern::target() const { | 68 RawCode* NativeCallPattern::target() const { |
| 69 return object_pool_.RawValueAt(target_address_pool_index_); | 69 return reinterpret_cast<RawCode*>( |
| 70 object_pool_.ObjectAt(target_code_pool_index_)); |
| 70 } | 71 } |
| 71 | 72 |
| 72 | 73 |
| 73 void NativeCallPattern::set_target(uword target_address) const { | 74 void NativeCallPattern::set_target(const Code& new_target) const { |
| 74 object_pool_.SetRawValueAt(target_address_pool_index_, target_address); | 75 object_pool_.SetObjectAt(target_code_pool_index_, new_target); |
| 75 // No need to flush the instruction cache, since the code is not modified. | 76 // No need to flush the instruction cache, since the code is not modified. |
| 76 } | 77 } |
| 77 | 78 |
| 78 | 79 |
| 79 NativeFunction NativeCallPattern::native_function() const { | 80 NativeFunction NativeCallPattern::native_function() const { |
| 80 return reinterpret_cast<NativeFunction>( | 81 return reinterpret_cast<NativeFunction>( |
| 81 object_pool_.RawValueAt(native_function_pool_index_)); | 82 object_pool_.RawValueAt(native_function_pool_index_)); |
| 82 } | 83 } |
| 83 | 84 |
| 84 | 85 |
| (...skipping 83 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... |
| 168 // sequence is the instruction before the one at end). Returns a pointer to | 169 // sequence is the instruction before the one at end). Returns a pointer to |
| 169 // the first instruction in the sequence. Returns the register being loaded | 170 // the first instruction in the sequence. Returns the register being loaded |
| 170 // and the index in the pool being read from in the output parameters 'reg' | 171 // and the index in the pool being read from in the output parameters 'reg' |
| 171 // and 'index' respectively. | 172 // and 'index' respectively. |
| 172 uword InstructionPattern::DecodeLoadWordFromPool(uword end, | 173 uword InstructionPattern::DecodeLoadWordFromPool(uword end, |
| 173 Register* reg, | 174 Register* reg, |
| 174 intptr_t* index) { | 175 intptr_t* index) { |
| 175 uword start = end - Instr::kInstrSize; | 176 uword start = end - Instr::kInstrSize; |
| 176 int32_t instr = Instr::At(start)->InstructionBits(); | 177 int32_t instr = Instr::At(start)->InstructionBits(); |
| 177 intptr_t offset = 0; | 178 intptr_t offset = 0; |
| 178 if ((instr & 0xffff0000) == 0xe59a0000) { // ldr reg, [pp, #+offset] | 179 if ((instr & 0xffff0000) == 0xe5990000) { // ldr reg, [pp, #+offset] |
| 179 offset = instr & 0xfff; | 180 offset = instr & 0xfff; |
| 180 *reg = static_cast<Register>((instr & 0xf000) >> 12); | 181 *reg = static_cast<Register>((instr & 0xf000) >> 12); |
| 181 } else { | 182 } else { |
| 182 ASSERT((instr & 0xfff00000) == 0xe5900000); // ldr reg, [reg, #+offset] | 183 ASSERT((instr & 0xfff00000) == 0xe5900000); // ldr reg, [reg, #+offset] |
| 183 offset = instr & 0xfff; | 184 offset = instr & 0xfff; |
| 184 start -= Instr::kInstrSize; | 185 start -= Instr::kInstrSize; |
| 185 instr = Instr::At(start)->InstructionBits(); | 186 instr = Instr::At(start)->InstructionBits(); |
| 186 if ((instr & 0xffff0000) == 0xe28a0000) { // add reg, pp, operand | 187 if ((instr & 0xffff0000) == 0xe2890000) { // add reg, pp, operand |
| 187 const intptr_t rot = (instr & 0xf00) >> 7; | 188 const intptr_t rot = (instr & 0xf00) >> 7; |
| 188 const intptr_t imm8 = instr & 0xff; | 189 const intptr_t imm8 = instr & 0xff; |
| 189 offset += (imm8 >> rot) | (imm8 << (32 - rot)); | 190 offset += (imm8 >> rot) | (imm8 << (32 - rot)); |
| 190 *reg = static_cast<Register>((instr & 0xf000) >> 12); | 191 *reg = static_cast<Register>((instr & 0xf000) >> 12); |
| 191 } else { | 192 } else { |
| 192 ASSERT((instr & 0xffff0000) == 0xe08a0000); // add reg, pp, reg | 193 ASSERT((instr & 0xffff0000) == 0xe0890000); // add reg, pp, reg |
| 193 end = DecodeLoadWordImmediate(end, reg, &offset); | 194 end = DecodeLoadWordImmediate(end, reg, &offset); |
| 194 } | 195 } |
| 195 } | 196 } |
| 196 *index = ObjectPool::IndexFromOffset(offset); | 197 *index = ObjectPool::IndexFromOffset(offset); |
| 197 return start; | 198 return start; |
| 198 } | 199 } |
| 199 | 200 |
| 200 | 201 |
| 201 RawICData* CallPattern::IcData() { | 202 RawICData* CallPattern::IcData() { |
| 202 if (ic_data_.IsNull()) { | 203 if (ic_data_.IsNull()) { |
| 203 Register reg; | 204 Register reg; |
| 204 InstructionPattern::DecodeLoadObject(ic_data_load_end_, | 205 InstructionPattern::DecodeLoadObject(ic_data_load_end_, |
| 205 object_pool_, | 206 object_pool_, |
| 206 ®, | 207 ®, |
| 207 &ic_data_); | 208 &ic_data_); |
| 208 ASSERT(reg == R5); | 209 ASSERT(reg == R5); |
| 209 } | 210 } |
| 210 return ic_data_.raw(); | 211 return ic_data_.raw(); |
| 211 } | 212 } |
| 212 | 213 |
| 213 | 214 |
| 214 uword CallPattern::TargetAddress() const { | 215 RawCode* CallPattern::TargetCode() const { |
| 215 return object_pool_.RawValueAt(target_address_pool_index_); | 216 return reinterpret_cast<RawCode*>( |
| 217 object_pool_.ObjectAt(target_code_pool_index_)); |
| 216 } | 218 } |
| 217 | 219 |
| 218 | 220 |
| 219 void CallPattern::SetTargetAddress(uword target_address) const { | 221 void CallPattern::SetTargetCode(const Code& target_code) const { |
| 220 object_pool_.SetRawValueAt(target_address_pool_index_, target_address); | 222 object_pool_.SetObjectAt(target_code_pool_index_, target_code); |
| 221 // No need to flush the instruction cache, since the code is not modified. | |
| 222 } | 223 } |
| 223 | 224 |
| 224 | 225 |
| 225 void CallPattern::InsertAt(uword pc, uword target_address) { | 226 void CallPattern::InsertDeoptCallAt(uword pc, uword target_address) { |
| 226 const ARMVersion version = TargetCPUFeatures::arm_version(); | 227 const ARMVersion version = TargetCPUFeatures::arm_version(); |
| 227 if ((version == ARMv5TE) || (version == ARMv6)) { | 228 if ((version == ARMv5TE) || (version == ARMv6)) { |
| 228 const uint32_t byte0 = (target_address & 0x000000ff); | 229 const uint32_t byte0 = (target_address & 0x000000ff); |
| 229 const uint32_t byte1 = (target_address & 0x0000ff00) >> 8; | 230 const uint32_t byte1 = (target_address & 0x0000ff00) >> 8; |
| 230 const uint32_t byte2 = (target_address & 0x00ff0000) >> 16; | 231 const uint32_t byte2 = (target_address & 0x00ff0000) >> 16; |
| 231 const uint32_t byte3 = (target_address & 0xff000000) >> 24; | 232 const uint32_t byte3 = (target_address & 0xff000000) >> 24; |
| 232 | 233 |
| 233 const uword mov_ip = 0xe3a0c400 | byte3; // mov ip, (byte3 rot 4) | 234 const uword mov_ip = 0xe3a0c400 | byte3; // mov ip, (byte3 rot 4) |
| 234 const uword or1_ip = 0xe38cc800 | byte2; // orr ip, ip, (byte2 rot 8) | 235 const uword or1_ip = 0xe38cc800 | byte2; // orr ip, ip, (byte2 rot 8) |
| 235 const uword or2_ip = 0xe38ccc00 | byte1; // orr ip, ip, (byte1 rot 12) | 236 const uword or2_ip = 0xe38ccc00 | byte1; // orr ip, ip, (byte1 rot 12) |
| 236 const uword or3_ip = 0xe38cc000 | byte0; // orr ip, ip, byte0 | 237 const uword or3_ip = 0xe38cc000 | byte0; // orr ip, ip, byte0 |
| 237 const uword blx_ip = 0xe12fff3c; | 238 const uword blx_ip = 0xe12fff3c; |
| 238 | 239 |
| 239 *reinterpret_cast<uword*>(pc + (0 * Instr::kInstrSize)) = mov_ip; | 240 *reinterpret_cast<uword*>(pc + (0 * Instr::kInstrSize)) = mov_ip; |
| 240 *reinterpret_cast<uword*>(pc + (1 * Instr::kInstrSize)) = or1_ip; | 241 *reinterpret_cast<uword*>(pc + (1 * Instr::kInstrSize)) = or1_ip; |
| 241 *reinterpret_cast<uword*>(pc + (2 * Instr::kInstrSize)) = or2_ip; | 242 *reinterpret_cast<uword*>(pc + (2 * Instr::kInstrSize)) = or2_ip; |
| 242 *reinterpret_cast<uword*>(pc + (3 * Instr::kInstrSize)) = or3_ip; | 243 *reinterpret_cast<uword*>(pc + (3 * Instr::kInstrSize)) = or3_ip; |
| 243 *reinterpret_cast<uword*>(pc + (4 * Instr::kInstrSize)) = blx_ip; | 244 *reinterpret_cast<uword*>(pc + (4 * Instr::kInstrSize)) = blx_ip; |
| 244 | 245 |
| 245 ASSERT(LengthInBytes() == 5 * Instr::kInstrSize); | 246 ASSERT(DeoptCallPatternLengthInBytes() == 5 * Instr::kInstrSize); |
| 246 CPU::FlushICache(pc, LengthInBytes()); | 247 CPU::FlushICache(pc, DeoptCallPatternLengthInBytes()); |
| 247 } else { | 248 } else { |
| 248 ASSERT(version == ARMv7); | 249 ASSERT(version == ARMv7); |
| 249 const uint16_t target_lo = target_address & 0xffff; | 250 const uint16_t target_lo = target_address & 0xffff; |
| 250 const uint16_t target_hi = target_address >> 16; | 251 const uint16_t target_hi = target_address >> 16; |
| 251 | 252 |
| 252 const uword movw_ip = | 253 const uword movw_ip = |
| 253 0xe300c000 | ((target_lo >> 12) << 16) | (target_lo & 0xfff); | 254 0xe300c000 | ((target_lo >> 12) << 16) | (target_lo & 0xfff); |
| 254 const uword movt_ip = | 255 const uword movt_ip = |
| 255 0xe340c000 | ((target_hi >> 12) << 16) | (target_hi & 0xfff); | 256 0xe340c000 | ((target_hi >> 12) << 16) | (target_hi & 0xfff); |
| 256 const uword blx_ip = 0xe12fff3c; | 257 const uword blx_ip = 0xe12fff3c; |
| 257 | 258 |
| 258 *reinterpret_cast<uword*>(pc + (0 * Instr::kInstrSize)) = movw_ip; | 259 *reinterpret_cast<uword*>(pc + (0 * Instr::kInstrSize)) = movw_ip; |
| 259 *reinterpret_cast<uword*>(pc + (1 * Instr::kInstrSize)) = movt_ip; | 260 *reinterpret_cast<uword*>(pc + (1 * Instr::kInstrSize)) = movt_ip; |
| 260 *reinterpret_cast<uword*>(pc + (2 * Instr::kInstrSize)) = blx_ip; | 261 *reinterpret_cast<uword*>(pc + (2 * Instr::kInstrSize)) = blx_ip; |
| 261 | 262 |
| 262 ASSERT(LengthInBytes() == 3 * Instr::kInstrSize); | 263 ASSERT(DeoptCallPatternLengthInBytes() == 3 * Instr::kInstrSize); |
| 263 CPU::FlushICache(pc, LengthInBytes()); | 264 CPU::FlushICache(pc, DeoptCallPatternLengthInBytes()); |
| 264 } | 265 } |
| 265 } | 266 } |
| 266 | 267 |
| 267 | |
| 268 JumpPattern::JumpPattern(uword pc, const Code& code) : pc_(pc) { } | |
| 269 | |
| 270 | |
| 271 int JumpPattern::pattern_length_in_bytes() { | |
| 272 const ARMVersion version = TargetCPUFeatures::arm_version(); | |
| 273 if ((version == ARMv5TE) || (version == ARMv6)) { | |
| 274 return 5 * Instr::kInstrSize; | |
| 275 } else { | |
| 276 ASSERT(version == ARMv7); | |
| 277 return 3 * Instr::kInstrSize; | |
| 278 } | |
| 279 } | |
| 280 | |
| 281 | |
| 282 bool JumpPattern::IsValid() const { | |
| 283 const ARMVersion version = TargetCPUFeatures::arm_version(); | |
| 284 if ((version == ARMv5TE) || (version == ARMv6)) { | |
| 285 Instr* mov_ip = Instr::At(pc_ + (0 * Instr::kInstrSize)); | |
| 286 Instr* or1_ip = Instr::At(pc_ + (1 * Instr::kInstrSize)); | |
| 287 Instr* or2_ip = Instr::At(pc_ + (2 * Instr::kInstrSize)); | |
| 288 Instr* or3_ip = Instr::At(pc_ + (3 * Instr::kInstrSize)); | |
| 289 Instr* bx_ip = Instr::At(pc_ + (4 * Instr::kInstrSize)); | |
| 290 return ((mov_ip->InstructionBits() & 0xffffff00) == 0xe3a0c400) && | |
| 291 ((or1_ip->InstructionBits() & 0xffffff00) == 0xe38cc800) && | |
| 292 ((or2_ip->InstructionBits() & 0xffffff00) == 0xe38ccc00) && | |
| 293 ((or3_ip->InstructionBits() & 0xffffff00) == 0xe38cc000) && | |
| 294 ((bx_ip->InstructionBits() & 0xffffffff) == 0xe12fff1c); | |
| 295 } else { | |
| 296 ASSERT(version == ARMv7); | |
| 297 Instr* movw_ip = Instr::At(pc_ + (0 * Instr::kInstrSize)); // target_lo | |
| 298 Instr* movt_ip = Instr::At(pc_ + (1 * Instr::kInstrSize)); // target_hi | |
| 299 Instr* bx_ip = Instr::At(pc_ + (2 * Instr::kInstrSize)); | |
| 300 return (movw_ip->InstructionBits() & 0xfff0f000) == 0xe300c000 && | |
| 301 (movt_ip->InstructionBits() & 0xfff0f000) == 0xe340c000 && | |
| 302 (bx_ip->InstructionBits() & 0xffffffff) == 0xe12fff1c; | |
| 303 } | |
| 304 } | |
| 305 | |
| 306 | |
| 307 uword JumpPattern::TargetAddress() const { | |
| 308 const ARMVersion version = TargetCPUFeatures::arm_version(); | |
| 309 if ((version == ARMv5TE) || (version == ARMv6)) { | |
| 310 Instr* mov_ip = Instr::At(pc_ + (0 * Instr::kInstrSize)); | |
| 311 Instr* or1_ip = Instr::At(pc_ + (1 * Instr::kInstrSize)); | |
| 312 Instr* or2_ip = Instr::At(pc_ + (2 * Instr::kInstrSize)); | |
| 313 Instr* or3_ip = Instr::At(pc_ + (3 * Instr::kInstrSize)); | |
| 314 uword imm = 0; | |
| 315 imm |= or3_ip->Immed8Field(); | |
| 316 imm |= or2_ip->Immed8Field() << 8; | |
| 317 imm |= or1_ip->Immed8Field() << 16; | |
| 318 imm |= mov_ip->Immed8Field() << 24; | |
| 319 return imm; | |
| 320 } else { | |
| 321 ASSERT(version == ARMv7); | |
| 322 Instr* movw_ip = Instr::At(pc_ + (0 * Instr::kInstrSize)); // target_lo | |
| 323 Instr* movt_ip = Instr::At(pc_ + (1 * Instr::kInstrSize)); // target_hi | |
| 324 uint16_t target_lo = movw_ip->MovwField(); | |
| 325 uint16_t target_hi = movt_ip->MovwField(); | |
| 326 return (target_hi << 16) | target_lo; | |
| 327 } | |
| 328 } | |
| 329 | |
| 330 | |
| 331 void JumpPattern::SetTargetAddress(uword target_address) const { | |
| 332 const ARMVersion version = TargetCPUFeatures::arm_version(); | |
| 333 if ((version == ARMv5TE) || (version == ARMv6)) { | |
| 334 const uint32_t byte0 = (target_address & 0x000000ff); | |
| 335 const uint32_t byte1 = (target_address & 0x0000ff00) >> 8; | |
| 336 const uint32_t byte2 = (target_address & 0x00ff0000) >> 16; | |
| 337 const uint32_t byte3 = (target_address & 0xff000000) >> 24; | |
| 338 | |
| 339 const uword mov_ip = 0xe3a0c400 | byte3; // mov ip, (byte3 rot 4) | |
| 340 const uword or1_ip = 0xe38cc800 | byte2; // orr ip, ip, (byte2 rot 8) | |
| 341 const uword or2_ip = 0xe38ccc00 | byte1; // orr ip, ip, (byte1 rot 12) | |
| 342 const uword or3_ip = 0xe38cc000 | byte0; // orr ip, ip, byte0 | |
| 343 | |
| 344 *reinterpret_cast<uword*>(pc_ + (0 * Instr::kInstrSize)) = mov_ip; | |
| 345 *reinterpret_cast<uword*>(pc_ + (1 * Instr::kInstrSize)) = or1_ip; | |
| 346 *reinterpret_cast<uword*>(pc_ + (2 * Instr::kInstrSize)) = or2_ip; | |
| 347 *reinterpret_cast<uword*>(pc_ + (3 * Instr::kInstrSize)) = or3_ip; | |
| 348 CPU::FlushICache(pc_, 4 * Instr::kInstrSize); | |
| 349 } else { | |
| 350 ASSERT(version == ARMv7); | |
| 351 const uint16_t target_lo = target_address & 0xffff; | |
| 352 const uint16_t target_hi = target_address >> 16; | |
| 353 | |
| 354 const uword movw_ip = | |
| 355 0xe300c000 | ((target_lo >> 12) << 16) | (target_lo & 0xfff); | |
| 356 const uword movt_ip = | |
| 357 0xe340c000 | ((target_hi >> 12) << 16) | (target_hi & 0xfff); | |
| 358 | |
| 359 *reinterpret_cast<uword*>(pc_ + (0 * Instr::kInstrSize)) = movw_ip; | |
| 360 *reinterpret_cast<uword*>(pc_ + (1 * Instr::kInstrSize)) = movt_ip; | |
| 361 CPU::FlushICache(pc_, 2 * Instr::kInstrSize); | |
| 362 } | |
| 363 } | |
| 364 | |
| 365 | 268 |
| 366 ReturnPattern::ReturnPattern(uword pc) | 269 ReturnPattern::ReturnPattern(uword pc) |
| 367 : pc_(pc) { | 270 : pc_(pc) { |
| 368 } | 271 } |
| 369 | 272 |
| 370 | 273 |
| 371 bool ReturnPattern::IsValid() const { | 274 bool ReturnPattern::IsValid() const { |
| 372 Instr* bx_lr = Instr::At(pc_); | 275 Instr* bx_lr = Instr::At(pc_); |
| 373 const int32_t B4 = 1 << 4; | 276 const int32_t B4 = 1 << 4; |
| 374 const int32_t B21 = 1 << 21; | 277 const int32_t B21 = 1 << 21; |
| 375 const int32_t B24 = 1 << 24; | 278 const int32_t B24 = 1 << 24; |
| 376 int32_t instruction = (static_cast<int32_t>(AL) << kConditionShift) | | 279 int32_t instruction = (static_cast<int32_t>(AL) << kConditionShift) | |
| 377 B24 | B21 | (0xfff << 8) | B4 | | 280 B24 | B21 | (0xfff << 8) | B4 | |
| 378 (static_cast<int32_t>(LR) << kRmShift); | 281 (static_cast<int32_t>(LR) << kRmShift); |
| 379 const ARMVersion version = TargetCPUFeatures::arm_version(); | 282 const ARMVersion version = TargetCPUFeatures::arm_version(); |
| 380 if ((version == ARMv5TE) || (version == ARMv6)) { | 283 if ((version == ARMv5TE) || (version == ARMv6)) { |
| 381 return bx_lr->InstructionBits() == instruction; | 284 return bx_lr->InstructionBits() == instruction; |
| 382 } else { | 285 } else { |
| 383 ASSERT(version == ARMv7); | 286 ASSERT(version == ARMv7); |
| 384 return bx_lr->InstructionBits() == instruction; | 287 return bx_lr->InstructionBits() == instruction; |
| 385 } | 288 } |
| 386 return false; | 289 return false; |
| 387 } | 290 } |
| 388 | 291 |
| 389 } // namespace dart | 292 } // namespace dart |
| 390 | 293 |
| 391 #endif // defined TARGET_ARCH_ARM | 294 #endif // defined TARGET_ARCH_ARM |
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