Add a basic enum for ARM InstructionSet / cpu features.

src/IceTypes.h

 //===- subzero/src/IceTypes.h - Primitive ICE types -------------*- C++ -*-===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 //
 // This file declares a few properties of the primitive types allowed
@@ skipping 25 matching lines @@
 
 const char *targetArchString(TargetArch Arch);
 
 inline Ostream &operator<<(Ostream &Stream, TargetArch Arch) {
   return Stream << targetArchString(Arch);
 }
 
 // The list of all target instruction sets. Individual targets will
 // map this to include only what is valid for the target.
 enum TargetInstructionSet {
+  // Represents baseline that can be assumed for a target (usually "Begin").
+  BaseInstructionSet,
   X86InstructionSet_Begin,
-  // SSE2 is the PNaCl baseline instruction set.
   X86InstructionSet_SSE2 = X86InstructionSet_Begin,
   X86InstructionSet_SSE4_1,
   X86InstructionSet_End,
+  ARM32InstructionSet_Begin,
+  ARM32InstructionSet_Neon = ARM32InstructionSet_Begin,
+  ARM32InstructionSet_HWDivArm,
+  ARM32InstructionSet_End,
 };
 
 enum OptLevel { Opt_m1, Opt_0, Opt_1, Opt_2 };
 
 size_t typeWidthInBytes(Type Ty);
 size_t typeAlignInBytes(Type Ty);
 size_t typeNumElements(Type Ty);
 Type typeElementType(Type Ty);
 const char *typeString(Type Ty);
 
@@ skipping 87 matching lines @@
 };
 
 inline Ostream &operator<<(Ostream &Stream, const FuncSigType &Sig) {
   Sig.dump(Stream);
   return Stream;
 }
 
 } // end of namespace Ice
 
 #endif // SUBZERO_SRC_ICETYPES_H