Add a basic enum for ARM InstructionSet / cpu features.

src/IceClFlags.cpp

 //===- subzero/src/IceClFlags.cpp - Command line flags and parsing --------===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 //
 // This file defines commandline flags parsing.
@@ skipping 124 matching lines @@
         clEnumValN(Ice::Target_X8664, "x86-64", "x86-64 (same as x8664)"),
         clEnumValN(Ice::Target_X8664, "x86_64", "x86-64 (same as x8664)"),
         clEnumValN(Ice::Target_ARM32, "arm", "arm32"),
         clEnumValN(Ice::Target_ARM32, "arm32", "arm32 (same as arm)"),
         clEnumValN(Ice::Target_ARM64, "arm64", "arm64"),
         clEnumValN(Ice::Target_MIPS32, "mips", "mips32"),
         clEnumValN(Ice::Target_MIPS32, "mips32", "mips32 (same as mips)"),
         clEnumValEnd));
 cl::opt<Ice::TargetInstructionSet> TargetInstructionSet(
     "mattr", cl::desc("Target architecture attributes"),
-    cl::init(Ice::X86InstructionSet_SSE2),
-    cl::values(clEnumValN(Ice::X86InstructionSet_SSE2, "sse2",
-                          "Enable SSE2 instructions (default)"),
+    cl::init(Ice::BaseInstructionSet),
+    cl::values(clEnumValN(Ice::BaseInstructionSet, "base",
+                          "Target chooses baseline instruction set (default)"),
+               clEnumValN(Ice::X86InstructionSet_SSE2, "sse2",
+                          "Enable X86 SSE2 instructions"),
                clEnumValN(Ice::X86InstructionSet_SSE4_1, "sse4.1",
-                          "Enable SSE 4.1 instructions"),
+                          "Enable X86 SSE 4.1 instructions"),
+               clEnumValN(Ice::ARM32InstructionSet_Neon, "neon",
+                          "Enable ARM Neon instructions"),
+               clEnumValN(Ice::ARM32InstructionSet_HWDivArm, "hwdiv-arm",
+                          "Enable ARM integer divide instructions in ARM mode"),
                clEnumValEnd));
 cl::opt<std::string>
     TestPrefix("prefix",
                cl::desc("Prepend a prefix to symbol names for testing"),
                cl::init(""), cl::value_desc("prefix"));
 
 cl::opt<bool> TimeEachFunction(
     "timing-funcs", cl::desc("Print total translation time for each function"));
 
 cl::opt<std::string> TimingFocusOn(
@@ skipping 191 matching lines @@
   OutFlagsExtra.setGenerateBuildAtts(GenerateBuildAtts);
   OutFlagsExtra.setLLVMVerboseErrors(LLVMVerboseErrors);
   OutFlagsExtra.setAppName(AppName);
   OutFlagsExtra.setInputFileFormat(InputFileFormat);
   OutFlagsExtra.setIRFilename(IRFilename);
   OutFlagsExtra.setLogFilename(LogFilename);
   OutFlagsExtra.setOutputFilename(OutputFilename);
 }
 
 } // end of namespace Ice