[turbofan] Add CalleeSavedFPRegisters to CallDescriptor.

src/compiler/arm64/code-generator-arm64.cc

Index: src/compiler/arm64/code-generator-arm64.cc
diff --git a/src/compiler/arm64/code-generator-arm64.cc b/src/compiler/arm64/code-generator-arm64.cc
index 736d5638d8edddb63ade5e5c4bf5c1e2d67675c4..f6a5c627a7b7ffc0c6b24a234a1b7644be114eea 100644
--- a/src/compiler/arm64/code-generator-arm64.cc
+++ b/src/compiler/arm64/code-generator-arm64.cc
@@ -1077,9 +1077,24 @@ void CodeGenerator::AssemblePrologue() {
     __ SetStackPointer(csp);
     __ Push(lr, fp);
     __ Mov(fp, csp);
-    // TODO(dcarney): correct callee saved registers.
-    __ PushCalleeSavedRegisters();
-    frame()->SetRegisterSaveAreaSize(20 * kPointerSize);
+
+    // Save FP registers.
+    CPURegList callee_save_fp =

[paul.l..., 2015/06/23 20:07:00]

nit: change these vars to saves_fp, and saves, to match the other arch's. This
will have small readability benefit as you (or clang-format) can move following
function up to this line using 2 lines total.

[akos.palfi.imgtec, 2015/06/23 20:33:18]

Done.

+        CPURegList(CPURegister::kFPRegister, kDRegSizeInBits,
+                   descriptor->CalleeSavedFPRegisters());
+    DCHECK(callee_save_fp.list() == CPURegList::GetCalleeSavedFP().list());
+    int saved_count = callee_save_fp.Count();
+    __ PushCPURegList(callee_save_fp);
+    // Save registers.
+    CPURegList callee_save = CPURegList(CPURegister::kRegister, kXRegSizeInBits,
+                                        descriptor->CalleeSavedRegisters());
+    // TODO(palfia): TF save list is not in sync with
+    // CPURegList::GetCalleeSaved(): x30 is missing.
+    // DCHECK(callee_save.list() == CPURegList::GetCalleeSaved().list());
+    saved_count += callee_save.Count();
+    __ PushCPURegList(callee_save);
+
+    frame()->SetRegisterSaveAreaSize(saved_count * kPointerSize);
   } else if (descriptor->IsJSFunctionCall()) {
     CompilationInfo* info = this->info();
     __ SetStackPointer(jssp);
@@ -1128,10 +1143,19 @@ void CodeGenerator::AssembleReturn() {
       if (stack_slots > 0) {
         __ Add(csp, csp, AlignedStackSlots(stack_slots) * kPointerSize);
       }
+
       // Restore registers.
-      // TODO(dcarney): correct callee saved registers.
-      __ PopCalleeSavedRegisters();
+      CPURegList callee_save =
+          CPURegList(CPURegister::kRegister, kXRegSizeInBits,
+                     descriptor->CalleeSavedRegisters());
+      __ PopCPURegList(callee_save);
+
+      CPURegList callee_save_fp =

[paul.l..., 2015/06/23 20:07:00]

nit: same here.

[akos.palfi.imgtec, 2015/06/23 20:33:18]

Done.

+          CPURegList(CPURegister::kFPRegister, kDRegSizeInBits,
+                     descriptor->CalleeSavedFPRegisters());
+      __ PopCPURegList(callee_save_fp);
     }
+
     __ Mov(csp, fp);
     __ Pop(fp, lr);
     __ Ret();