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Side by Side Diff: lib/Target/Mips/MipsNaClRewritePass.cpp

Issue 11883035: [MIPS] Skip masking loads and stores via thread pointer. (Closed) Base URL: http://git.chromium.org/native_client/pnacl-llvm.git@master
Patch Set: Created 7 years, 11 months ago
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1 //===-- MipsNaClRewritePass.cpp - Native Client Rewrite Pass -----*- C++ -*-=// 1 //===-- MipsNaClRewritePass.cpp - Native Client Rewrite Pass -----*- C++ -*-=//
2 // 2 //
3 // The LLVM Compiler Infrastructure 3 // The LLVM Compiler Infrastructure
4 // 4 //
5 // This file is distributed under the University of Illinois Open Source 5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details. 6 // License. See LICENSE.TXT for details.
7 // 7 //
8 //===----------------------------------------------------------------------===// 8 //===----------------------------------------------------------------------===//
9 // 9 //
10 // Native Client Rewrite Pass 10 // Native Client Rewrite Pass
(...skipping 191 matching lines...) Expand 10 before | Expand all | Expand 10 after
202 case Mips::LW: 202 case Mips::LW:
203 case Mips::LWC1: 203 case Mips::LWC1:
204 case Mips::LDC1: 204 case Mips::LDC1:
205 case Mips::LL: 205 case Mips::LL:
206 case Mips::LWL: 206 case Mips::LWL:
207 case Mips::LWR: 207 case Mips::LWR:
208 *AddrIdx = 1; 208 *AddrIdx = 1;
209 break; 209 break;
210 } 210 }
211 211
212 if (MI.getOperand(*AddrIdx).getReg() == Mips::SP) { 212 switch (MI.getOperand(*AddrIdx).getReg()) {
213 // The contents of SP do not require masking. 213 default: break;
214 return false; 214 // The contents of SP and thread pointer register do not require masking.
215 case Mips::SP:
216 case Mips::T8:
217 return false;
215 } 218 }
216 219
217 return true; 220 return true;
218 } 221 }
219 222
220 bool IsDangerousStore(const MachineInstr &MI, int *AddrIdx) { 223 bool IsDangerousStore(const MachineInstr &MI, int *AddrIdx) {
221 unsigned Opcode = MI.getOpcode(); 224 unsigned Opcode = MI.getOpcode();
222 switch (Opcode) { 225 switch (Opcode) {
223 default: return false; 226 default: return false;
224 227
225 // Instructions with base address register in position 1 228 // Instructions with base address register in position 1
226 case Mips::SB: 229 case Mips::SB:
227 case Mips::SH: 230 case Mips::SH:
228 case Mips::SW: 231 case Mips::SW:
229 case Mips::SWC1: 232 case Mips::SWC1:
230 case Mips::SDC1: 233 case Mips::SDC1:
231 case Mips::SWL: 234 case Mips::SWL:
232 case Mips::SWR: 235 case Mips::SWR:
233 *AddrIdx = 1; 236 *AddrIdx = 1;
234 break; 237 break;
235 238
236 case Mips::SC: 239 case Mips::SC:
237 *AddrIdx = 2; 240 *AddrIdx = 2;
238 break; 241 break;
239 } 242 }
240 243
241 if (MI.getOperand(*AddrIdx).getReg() == Mips::SP) { 244 switch (MI.getOperand(*AddrIdx).getReg()) {
242 // The contents of SP do not require masking. 245 default: break;
243 return false; 246 // The contents of SP and thread pointer register do not require masking.
247 case Mips::SP:
248 case Mips::T8:
249 return false;
244 } 250 }
245 251
246 return true; 252 return true;
247 } 253 }
248 254
249 bool MipsNaClRewritePass::SandboxLoadsInBlock(MachineBasicBlock &MBB) { 255 bool MipsNaClRewritePass::SandboxLoadsInBlock(MachineBasicBlock &MBB) {
250 bool Modified = false; 256 bool Modified = false;
251 for (MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end(); 257 for (MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end();
252 MBBI != E; 258 MBBI != E;
253 ++MBBI) { 259 ++MBBI) {
(...skipping 70 matching lines...) Expand 10 before | Expand all | Expand 10 after
324 if (FlagSfiBranch) 330 if (FlagSfiBranch)
325 AlignAllJumpTargets(MF); 331 AlignAllJumpTargets(MF);
326 332
327 return Modified; 333 return Modified;
328 } 334 }
329 335
330 /// createMipsNaClRewritePass - returns an instance of the NaClRewritePass. 336 /// createMipsNaClRewritePass - returns an instance of the NaClRewritePass.
331 FunctionPass *llvm::createMipsNaClRewritePass() { 337 FunctionPass *llvm::createMipsNaClRewritePass() {
332 return new MipsNaClRewritePass(); 338 return new MipsNaClRewritePass();
333 } 339 }
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