ARM: Assign "actuals" at call site to the appropriate GPR/stack slot.

src/IceTargetLoweringARM32.h

 //===- subzero/src/IceTargetLoweringARM32.h - ARM32 lowering ----*- C++ -*-===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 //
 // This file declares the TargetLoweringARM32 class, which implements the
@@ skipping 141 matching lines @@
   void _adds(Variable *Dest, Variable *Src0, Operand *Src1,
              CondARM32::Cond Pred = CondARM32::AL) {
     const bool SetFlags = true;
     Context.insert(
         InstARM32Add::create(Func, Dest, Src0, Src1, Pred, SetFlags));
   }
   void _adc(Variable *Dest, Variable *Src0, Operand *Src1,
             CondARM32::Cond Pred = CondARM32::AL) {
     Context.insert(InstARM32Adc::create(Func, Dest, Src0, Src1, Pred));
   }
+  void _adjust_stack(int32_t Amount, Operand *SrcAmount) {
+    Context.insert(InstARM32AdjustStack::create(
+        Func, getPhysicalRegister(RegARM32::Reg_sp), Amount, SrcAmount));
+  }
   void _and(Variable *Dest, Variable *Src0, Operand *Src1,
             CondARM32::Cond Pred = CondARM32::AL) {
     Context.insert(InstARM32And::create(Func, Dest, Src0, Src1, Pred));
   }
   void _asr(Variable *Dest, Variable *Src0, Operand *Src1,
             CondARM32::Cond Pred = CondARM32::AL) {
     Context.insert(InstARM32Asr::create(Func, Dest, Src0, Src1, Pred));
   }
   void _bic(Variable *Dest, Variable *Src0, Operand *Src1,
             CondARM32::Cond Pred = CondARM32::AL) {
@@ skipping 130 matching lines @@
   bool UsesFramePointer;
   bool NeedsStackAlignment;
   bool MaybeLeafFunc;
   size_t SpillAreaSizeBytes;
   llvm::SmallBitVector TypeToRegisterSet[IceType_NUM];
   llvm::SmallBitVector ScratchRegs;
   llvm::SmallBitVector RegsUsed;
   VarList PhysicalRegisters[IceType_NUM];
   static IceString RegNames[];
 
+  // Helper class that understands the Calling Convention and register
+  // assignments. The first few integer type parameters can use r0-r3,
+  // regardless of their position relative to the floating-point/vector
+  // arguments in the argument list. Floating-point and vector arguments
+  // can use q0-q3 (aka d0-d7, s0-s15). Technically, arguments that can
+  // start with registers but extend beyond the available registers can be
+  // split between the registers and the stack. However, this is typically
+  // for passing GPR structs by value, and PNaCl transforms expand this out.
+  //
+  // Also, at the point before the call, the stack must be aligned.
+  class CallingConv {
+    CallingConv(const CallingConv &) = delete;
+    CallingConv &operator=(const CallingConv &) = delete;
+
+  public:
+    CallingConv() : NumGPRRegsUsed(0) {}
+    ~CallingConv() = default;
+
+    bool I64InRegs(std::pair<int32_t, int32_t> *Regs);
+    bool I32InReg(int32_t *Reg);
+
+    static constexpr uint32_t ARM32_MAX_GPR_ARG = 4;
+
+  private:
+    uint32_t NumGPRRegsUsed;
+  };
+
 private:
   ~TargetARM32() override {}
 };
 
 class TargetDataARM32 final : public TargetDataLowering {
   TargetDataARM32() = delete;
   TargetDataARM32(const TargetDataARM32 &) = delete;
   TargetDataARM32 &operator=(const TargetDataARM32 &) = delete;
 
 public:
@@ skipping 28 matching lines @@
 protected:
   explicit TargetHeaderARM32(GlobalContext *Ctx);
 
 private:
   ~TargetHeaderARM32() = default;
 };
 
 } // end of namespace Ice
 
 #endif // SUBZERO_SRC_ICETARGETLOWERINGARM32_H