Chromium Code Reviews
chromiumcodereview-hr@appspot.gserviceaccount.com (chromiumcodereview-hr) | Please choose your nickname with Settings | Help | Chromium Project | Gerrit Changes | Sign out
(89)

Side by Side Diff: src/IceInstARM32.cpp

Issue 1187513006: ARM: Assign "actuals" at call site to the appropriate GPR/stack slot. (Closed) Base URL: https://chromium.googlesource.com/native_client/pnacl-subzero.git@master
Patch Set: tpypo Created 5 years, 6 months ago
Use n/p to move between diff chunks; N/P to move between comments. Draft comments are only viewable by you.
Jump to:
View unified diff | Download patch
OLDNEW
1 //===- subzero/src/IceInstARM32.cpp - ARM32 instruction implementation ----===// 1 //===- subzero/src/IceInstARM32.cpp - ARM32 instruction implementation ----===//
2 // 2 //
3 // The Subzero Code Generator 3 // The Subzero Code Generator
4 // 4 //
5 // This file is distributed under the University of Illinois Open Source 5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details. 6 // License. See LICENSE.TXT for details.
7 // 7 //
8 //===----------------------------------------------------------------------===// 8 //===----------------------------------------------------------------------===//
9 // 9 //
10 // This file implements the InstARM32 and OperandARM32 classes, 10 // This file implements the InstARM32 and OperandARM32 classes,
(...skipping 180 matching lines...) Expand 10 before | Expand all | Expand 10 after
191 NumVars = 1; 191 NumVars = 1;
192 Variable *ShiftVar = llvm::dyn_cast_or_null<Variable>(ShiftAmt); 192 Variable *ShiftVar = llvm::dyn_cast_or_null<Variable>(ShiftAmt);
193 if (ShiftVar) 193 if (ShiftVar)
194 ++NumVars; 194 ++NumVars;
195 Vars = Func->allocateArrayOf<Variable *>(NumVars); 195 Vars = Func->allocateArrayOf<Variable *>(NumVars);
196 Vars[0] = Reg; 196 Vars[0] = Reg;
197 if (ShiftVar) 197 if (ShiftVar)
198 Vars[1] = ShiftVar; 198 Vars[1] = ShiftVar;
199 } 199 }
200 200
201 InstARM32AdjustStack::InstARM32AdjustStack(Cfg *Func, Variable *SP,
202 SizeT Amount, Operand *SrcAmount)
203 : InstARM32(Func, InstARM32::Adjuststack, 2, SP), Amount(Amount) {
204 addSource(SP);
205 addSource(SrcAmount);
206 }
207
201 InstARM32Br::InstARM32Br(Cfg *Func, const CfgNode *TargetTrue, 208 InstARM32Br::InstARM32Br(Cfg *Func, const CfgNode *TargetTrue,
202 const CfgNode *TargetFalse, CondARM32::Cond Pred) 209 const CfgNode *TargetFalse, CondARM32::Cond Pred)
203 : InstARM32Pred(Func, InstARM32::Br, 0, nullptr, Pred), 210 : InstARM32Pred(Func, InstARM32::Br, 0, nullptr, Pred),
204 TargetTrue(TargetTrue), TargetFalse(TargetFalse) {} 211 TargetTrue(TargetTrue), TargetFalse(TargetFalse) {}
205 212
206 bool InstARM32Br::optimizeBranch(const CfgNode *NextNode) { 213 bool InstARM32Br::optimizeBranch(const CfgNode *NextNode) {
207 // If there is no next block, then there can be no fallthrough to 214 // If there is no next block, then there can be no fallthrough to
208 // optimize. 215 // optimize.
209 if (NextNode == nullptr) 216 if (NextNode == nullptr)
210 return false; 217 return false;
(...skipping 413 matching lines...) Expand 10 before | Expand all | Expand 10 after
624 Ostream &Str = Func->getContext()->getStrDump(); 631 Ostream &Str = Func->getContext()->getStrDump();
625 Str << "pop" 632 Str << "pop"
626 << " "; 633 << " ";
627 for (SizeT I = 0; I < Dests.size(); ++I) { 634 for (SizeT I = 0; I < Dests.size(); ++I) {
628 if (I > 0) 635 if (I > 0)
629 Str << ", "; 636 Str << ", ";
630 Dests[I]->dump(Func); 637 Dests[I]->dump(Func);
631 } 638 }
632 } 639 }
633 640
641 void InstARM32AdjustStack::emit(const Cfg *Func) const {
642 if (!ALLOW_DUMP)
643 return;
644 Ostream &Str = Func->getContext()->getStrEmit();
645 assert(getSrcSize() == 2);
646 Str << "\t"
647 << "sub"
648 << "\tsp, ";
Jim Stichnoth 2015/06/18 19:47:33 There is both "sp" and getSrc(0). Should they bot
jvoung (off chromium) 2015/06/18 21:18:30 Hmm yeah, I'll just use the actual operand.
649 getSrc(0)->emit(Func);
650 Str << ", ";
651 getSrc(1)->emit(Func);
652 Func->getTarget()->updateStackAdjustment(Amount);
653 }
654
655 void InstARM32AdjustStack::emitIAS(const Cfg *Func) const {
656 (void)Func;
657 llvm_unreachable("Not yet implemented");
658 Func->getTarget()->updateStackAdjustment(Amount);
659 }
660
661 void InstARM32AdjustStack::dump(const Cfg *Func) const {
662 if (!ALLOW_DUMP)
663 return;
664 Ostream &Str = Func->getContext()->getStrDump();
665 Str << "sp = sub.i32 sp, " << Amount;
Jim Stichnoth 2015/06/18 19:47:33 Maybe add SrcAmount to the dump output for complet
jvoung (off chromium) 2015/06/18 21:18:30 Done.
666 }
667
634 void InstARM32Push::emit(const Cfg *Func) const { 668 void InstARM32Push::emit(const Cfg *Func) const {
635 if (!ALLOW_DUMP) 669 if (!ALLOW_DUMP)
636 return; 670 return;
637 assert(getSrcSize() > 0); 671 assert(getSrcSize() > 0);
638 Ostream &Str = Func->getContext()->getStrEmit(); 672 Ostream &Str = Func->getContext()->getStrEmit();
639 Str << "\t" 673 Str << "\t"
640 << "push" 674 << "push"
641 << "\t{"; 675 << "\t{";
642 emitSources(Func); 676 emitSources(Func);
643 Str << "}"; 677 Str << "}";
(...skipping 215 matching lines...) Expand 10 before | Expand all | Expand 10 after
859 if (getShiftOp() != kNoShift) { 893 if (getShiftOp() != kNoShift) {
860 Str << ", " << InstARM32ShiftAttributes[getShiftOp()].EmitString << " "; 894 Str << ", " << InstARM32ShiftAttributes[getShiftOp()].EmitString << " ";
861 if (Func) 895 if (Func)
862 getShiftAmt()->dump(Func); 896 getShiftAmt()->dump(Func);
863 else 897 else
864 getShiftAmt()->dump(Str); 898 getShiftAmt()->dump(Str);
865 } 899 }
866 } 900 }
867 901
868 } // end of namespace Ice 902 } // end of namespace Ice
OLDNEW
« src/IceInstARM32.h ('K') | « src/IceInstARM32.h ('k') | src/IceTargetLoweringARM32.h » ('j') | no next file with comments »

Powered by Google App Engine
This is Rietveld 408576698