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Issue 1187063002: MIPS: Fix for Remove unsafe EmitLoadRegister usage in AddI/SubI for constant right operand. (Closed) Base URL: https://chromium.googlesource.com/v8/v8.git@master
Patch Set: Specify scratch reg to Overflow macros, to avoid 'at' reg conflict. Created 5 years, 6 months ago
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1 // Copyright 2012 the V8 project authors. All rights reserved. 1 // Copyright 2012 the V8 project authors. All rights reserved.
2 // Use of this source code is governed by a BSD-style license that can be 2 // Use of this source code is governed by a BSD-style license that can be
3 // found in the LICENSE file. 3 // found in the LICENSE file.
4 4
5 #include <limits.h> // For LONG_MIN, LONG_MAX. 5 #include <limits.h> // For LONG_MIN, LONG_MAX.
6 6
7 #include "src/v8.h" 7 #include "src/v8.h"
8 8
9 #if V8_TARGET_ARCH_MIPS 9 #if V8_TARGET_ARCH_MIPS
10 10
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4452 } else { 4452 } else {
4453 if (dst.is(left)) { 4453 if (dst.is(left)) {
4454 mov(scratch, left); // Preserve left. 4454 mov(scratch, left); // Preserve left.
4455 Addu(dst, left, right.immediate()); // Left is overwritten. 4455 Addu(dst, left, right.immediate()); // Left is overwritten.
4456 xor_(scratch, dst, scratch); // Original left. 4456 xor_(scratch, dst, scratch); // Original left.
4457 // Load right since xori takes uint16 as immediate. 4457 // Load right since xori takes uint16 as immediate.
4458 Addu(t9, zero_reg, right); 4458 Addu(t9, zero_reg, right);
4459 xor_(overflow_dst, dst, t9); 4459 xor_(overflow_dst, dst, t9);
4460 and_(overflow_dst, overflow_dst, scratch); 4460 and_(overflow_dst, overflow_dst, scratch);
4461 } else { 4461 } else {
4462 addiu(dst, left, right.immediate()); 4462 Addu(dst, left, right.immediate());
4463 xor_(overflow_dst, dst, left); 4463 xor_(overflow_dst, dst, left);
4464 // Load right since xori takes uint16 as immediate. 4464 // Load right since xori takes uint16 as immediate.
4465 Addu(t9, zero_reg, right); 4465 Addu(t9, zero_reg, right);
4466 xor_(scratch, dst, t9); 4466 xor_(scratch, dst, t9);
4467 and_(overflow_dst, scratch, overflow_dst); 4467 and_(overflow_dst, scratch, overflow_dst);
4468 } 4468 }
4469 } 4469 }
4470 } 4470 }
4471 4471
4472 4472
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6126 if (mag.shift > 0) sra(result, result, mag.shift); 6126 if (mag.shift > 0) sra(result, result, mag.shift);
6127 srl(at, dividend, 31); 6127 srl(at, dividend, 31);
6128 Addu(result, result, Operand(at)); 6128 Addu(result, result, Operand(at));
6129 } 6129 }
6130 6130
6131 6131
6132 } // namespace internal 6132 } // namespace internal
6133 } // namespace v8 6133 } // namespace v8
6134 6134
6135 #endif // V8_TARGET_ARCH_MIPS 6135 #endif // V8_TARGET_ARCH_MIPS
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