Optimize the emitted instruction of random function for X64

src/x64/assembler-x64.cc

 // Copyright 2012 the V8 project authors. All rights reserved.
 // Redistribution and use in source and binary forms, with or without
 // modification, are permitted provided that the following conditions are
 // met:
 //
 //     * Redistributions of source code must retain the above copyright
 //       notice, this list of conditions and the following disclaimer.
 //     * Redistributions in binary form must reproduce the above
 //       copyright notice, this list of conditions and the following
 //       disclaimer in the documentation and/or other materials provided
@@ skipping 295 matching lines @@
     // Need no displacement.
     buf_[0] = (modrm & 0x3f);  // Mode 0.
     len_ = disp_offset;
   }
   if (has_sib) {
     buf_[1] = operand.buf_[1];
   }
 }
 
 
+Operand::Operand(Register reg) {
+  len_ = 1;
+  set_modrm(3, reg);
+}
+
+
 bool Operand::AddressUsesRegister(Register reg) const {
   int code = reg.code();
   ASSERT((buf_[0] & 0xC0) != 0xC0);  // Always a memory operand.
   // Start with only low three bits of base register. Initial decoding doesn't
   // distinguish on the REX.B bit.
   int base_code = buf_[0] & 0x07;
   if (base_code == rsp.code()) {
     // SIB byte present in buf_[1].
     // Check the index register from the SIB byte + REX.X prefix.
     int index_code = ((buf_[1] >> 3) & 0x07) | ((rex_ & 0x02) << 2);
@@ skipping 2715 matching lines @@
 bool RelocInfo::IsCodedSpecially() {
   // The deserializer needs to know whether a pointer is specially coded.  Being
   // specially coded on x64 means that it is a relative 32 bit address, as used
   // by branch instructions.
   return (1 << rmode_) & kApplyMask;
 }
 
 } }  // namespace v8::internal
 
 #endif  // V8_TARGET_ARCH_X64