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Issue 1182603004: Subzero: Transform suitable Load/Arith/Store sequences into RMW ops. (Closed) Base URL: https://chromium.googlesource.com/native_client/pnacl-subzero.git@master
Patch Set: Code review changes Created 5 years, 6 months ago
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1 //===- subzero/src/IceCfg.cpp - Control flow graph implementation ---------===// 1 //===- subzero/src/IceCfg.cpp - Control flow graph implementation ---------===//
2 // 2 //
3 // The Subzero Code Generator 3 // The Subzero Code Generator
4 // 4 //
5 // This file is distributed under the University of Illinois Open Source 5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details. 6 // License. See LICENSE.TXT for details.
7 // 7 //
8 //===----------------------------------------------------------------------===// 8 //===----------------------------------------------------------------------===//
9 // 9 //
10 // This file implements the Cfg class, including constant pool 10 // This file implements the Cfg class, including constant pool
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426 if (Mode == Liveness_Intervals) { 426 if (Mode == Liveness_Intervals) {
427 // Special treatment for live in-args. Their liveness needs to 427 // Special treatment for live in-args. Their liveness needs to
428 // extend beyond the beginning of the function, otherwise an arg 428 // extend beyond the beginning of the function, otherwise an arg
429 // whose only use is in the first instruction will end up having 429 // whose only use is in the first instruction will end up having
430 // the trivial live range [2,2) and will *not* interfere with 430 // the trivial live range [2,2) and will *not* interfere with
431 // other arguments. So if the first instruction of the method 431 // other arguments. So if the first instruction of the method
432 // is "r=arg1+arg2", both args may be assigned the same 432 // is "r=arg1+arg2", both args may be assigned the same
433 // register. This is accomplished by extending the entry 433 // register. This is accomplished by extending the entry
434 // block's instruction range from [2,n) to [1,n) which will 434 // block's instruction range from [2,n) to [1,n) which will
435 // transform the problematic [2,2) live ranges into [1,2). 435 // transform the problematic [2,2) live ranges into [1,2).
436 if (FirstInstNum == Inst::NumberInitial) 436 if (Node == getEntryNode()) {
437 // TODO(stichnot): Make it a strict requirement that the entry
438 // node gets the lowest instruction numbers, so that extending
439 // the live range for in-args is guaranteed to work.
437 FirstInstNum = Inst::NumberExtended; 440 FirstInstNum = Inst::NumberExtended;
441 }
438 Node->livenessAddIntervals(getLiveness(), FirstInstNum, LastInstNum); 442 Node->livenessAddIntervals(getLiveness(), FirstInstNum, LastInstNum);
439 } 443 }
440 } 444 }
441 } 445 }
442 446
443 // Traverse every Variable of every Inst and verify that it 447 // Traverse every Variable of every Inst and verify that it
444 // appears within the Variable's computed live range. 448 // appears within the Variable's computed live range.
445 bool Cfg::validateLiveness() const { 449 bool Cfg::validateLiveness() const {
446 TimerMarker T(TimerStack::TT_validateLiveness, this); 450 TimerMarker T(TimerStack::TT_validateLiveness, this);
447 bool Valid = true; 451 bool Valid = true;
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615 } 619 }
616 } 620 }
617 // Print each basic block 621 // Print each basic block
618 for (CfgNode *Node : Nodes) 622 for (CfgNode *Node : Nodes)
619 Node->dump(this); 623 Node->dump(this);
620 if (isVerbose(IceV_Instructions)) 624 if (isVerbose(IceV_Instructions))
621 Str << "}\n"; 625 Str << "}\n";
622 } 626 }
623 627
624 } // end of namespace Ice 628 } // end of namespace Ice
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