Subzero: Transform suitable Load/Arith/Store sequences into RMW ops.

src/IceInstX8632.h

 //===- subzero/src/IceInstX8632.h - x86-32 machine instructions -*- C++ -*-===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 //
 // This file declares the InstX8632 and OperandX8632 classes and
@@ skipping 158 matching lines @@
 class InstX8632 : public InstTarget {
   InstX8632() = delete;
   InstX8632(const InstX8632 &) = delete;
   InstX8632 &operator=(const InstX8632 &) = delete;
 
 public:
   enum InstKindX8632 {
     k__Start = Inst::Target,
     Adc,
     Add,
+    AddRMW,
     Addps,
     Addss,
     Adjuststack,
     And,
     Blendvps,
     Br,
     Bsf,
     Bsr,
     Bswap,
     Call,
     Cbwdq,
     Cmov,
     Cmpps,
     Cmpxchg,
     Cmpxchg8b,
     Cvt,
     Div,
     Divps,
     Divss,
+    FakeRMW,
     Fld,
     Fstp,
     Icmp,
     Idiv,
     Imul,
     Insertps,
     Jmp,
     Label,
     Lea,
     Load,
@@ skipping 97 matching lines @@
   }
 
 private:
   static void validateVectorAddrModeOpnd(const Operand *Opnd) {
     if (llvm::isa<OperandX8632Mem>(Opnd) && isVectorType(Opnd->getType())) {
       llvm::report_fatal_error("Possible misaligned vector memory operation");
     }
   }
 };
 
+// InstX8632FakeRMW represents a non-atomic read-modify-write

[jvoung (off chromium), 2015/06/17 16:40:22]

In this case the "Fake" seems a bit different from FakeDef/FakeUse. It seems to
represent more of a high level instruction that hasn't been lowered yet (like
AddRMW is). Might be worth pointing out that there's still some lowering?

[Jim Stichnoth, 2015/06/18 05:15:12]

Done.

+// operation on a memory location.  If A is some memory address, D is
+// some data value to apply, and OP is an arithmetic operator, the
+// instruction operates as:
+//   (*A) = (*A) OP D
+class InstX8632FakeRMW : public InstX8632 {
+  InstX8632FakeRMW() = delete;
+  InstX8632FakeRMW(const InstX8632FakeRMW &) = delete;
+  InstX8632FakeRMW &operator=(const InstX8632FakeRMW &) = delete;
+
+public:
+  static InstX8632FakeRMW *create(Cfg *Func, Operand *Data, Operand *Addr,
+                                  Variable *Beacon, InstArithmetic::OpKind Op,
+                                  uint32_t Align = 1) {
+    // TODO(stichnot): Stop ignoring alignment specification.
+    (void)Align;
+    return new (Func->allocate<InstX8632FakeRMW>())
+        InstX8632FakeRMW(Func, Data, Addr, Op, Beacon);
+  }
+  Operand *getAddr() const { return getSrc(1); }
+  Operand *getData() const { return getSrc(0); }
+  InstArithmetic::OpKind getOp() const { return Op; }
+  Variable *getBeacon() const { return llvm::cast<Variable>(getSrc(2)); }
+  void dump(const Cfg *Func) const override;
+  static bool classof(const Inst *Inst) { return isClassof(Inst, FakeRMW); }
+
+private:
+  InstArithmetic::OpKind Op;
+  InstX8632FakeRMW(Cfg *Func, Operand *Data, Operand *Addr,
+                   InstArithmetic::OpKind Op, Variable *Beacon);
+  ~InstX8632FakeRMW() override {}
+};
+
 // InstX8632Label represents an intra-block label that is the target
 // of an intra-block branch.  The offset between the label and the
 // branch must be fit into one byte (considered "near").  These are
 // used for lowering i1 calculations, Select instructions, and 64-bit
 // compares on a 32-bit architecture, without basic block splitting.
 // Basic block splitting is not so desirable for several reasons, one
 // of which is the impact on decisions based on whether a variable's
 // live range spans multiple basic blocks.
 //
 // Intra-block control flow must be used with caution.  Consider the
@@ skipping 183 matching lines @@
   static bool classof(const Inst *Inst) { return isClassof(Inst, Call); }
 
 private:
   InstX8632Call(Cfg *Func, Variable *Dest, Operand *CallTarget);
   ~InstX8632Call() override {}
 };
 
 // Emit a one-operand (GPR) instruction.
 void emitIASOpTyGPR(const Cfg *Func, Type Ty, const Operand *Var,
                     const X8632::AssemblerX8632::GPREmitterOneOp &Emitter);
+void emitIASAsAddrOpTyGPR(
+    const Cfg *Func, Type Ty, const Operand *Op0, const Operand *Op1,
+    const X8632::AssemblerX8632::GPREmitterAddrOp &Emitter);
 
 // Instructions of the form x := op(x).
 template <InstX8632::InstKindX8632 K>
 class InstX8632InplaceopGPR : public InstX8632 {
   InstX8632InplaceopGPR() = delete;
   InstX8632InplaceopGPR(const InstX8632InplaceopGPR &) = delete;
   InstX8632InplaceopGPR &operator=(const InstX8632InplaceopGPR &) = delete;
 
 public:
   static InstX8632InplaceopGPR *create(Cfg *Func, Operand *SrcDest) {
@@ skipping 230 matching lines @@
   InstX8632BinopGPR(Cfg *Func, Variable *Dest, Operand *Source)
       : InstX8632(Func, K, 2, Dest) {
     addSource(Dest);
     addSource(Source);
   }
   ~InstX8632BinopGPR() override {}
   static const char *Opcode;
   static const X8632::AssemblerX8632::GPREmitterRegOp Emitter;
 };
 
+template <InstX8632::InstKindX8632 K>
+class InstX8632BinopRMW : public InstX8632 {
+  InstX8632BinopRMW() = delete;
+  InstX8632BinopRMW(const InstX8632BinopRMW &) = delete;
+  InstX8632BinopRMW &operator=(const InstX8632BinopRMW &) = delete;
+
+public:
+  // Create an ordinary binary-op instruction like add or sub.
+  static InstX8632BinopRMW *create(Cfg *Func, OperandX8632Mem *DestSrc0,
+                                   Operand *Src1) {
+    return new (Func->allocate<InstX8632BinopRMW>())
+        InstX8632BinopRMW(Func, DestSrc0, Src1);
+  }
+  void emit(const Cfg *Func) const override {
+    if (!ALLOW_DUMP)
+      return;
+    const bool ShiftHack = false;
+    emitTwoAddress(Opcode, this, Func, ShiftHack);
+  }
+  void emitIAS(const Cfg *Func) const override {
+    Type Ty = getSrc(0)->getType();
+    assert(getSrcSize() == 2);
+    emitIASAsAddrOpTyGPR(Func, Ty, getSrc(0), getSrc(1), Emitter);
+  }
+  void dump(const Cfg *Func) const override {
+    if (!ALLOW_DUMP)
+      return;
+    Ostream &Str = Func->getContext()->getStrDump();
+    Str << Opcode << "." << getSrc(0)->getType() << " ";
+    dumpSources(Func);
+  }
+  static bool classof(const Inst *Inst) { return isClassof(Inst, K); }
+
+private:
+  InstX8632BinopRMW(Cfg *Func, Operand *DestSrc0, Operand *Src1)

[jvoung (off chromium), 2015/06/17 16:40:22]

OperandX8632Mem *DestSrc0 too?

[Jim Stichnoth, 2015/06/18 05:15:12]

Done.

+      : InstX8632(Func, K, 2, nullptr) {
+    addSource(DestSrc0);
+    addSource(Src1);
+  }
+  ~InstX8632BinopRMW() override {}
+  static const char *Opcode;
+  static const X8632::AssemblerX8632::GPREmitterAddrOp Emitter;
+};
+
 template <InstX8632::InstKindX8632 K, bool NeedsElementType>
 class InstX8632BinopXmm : public InstX8632 {
   InstX8632BinopXmm() = delete;
   InstX8632BinopXmm(const InstX8632BinopXmm &) = delete;
   InstX8632BinopXmm &operator=(const InstX8632BinopXmm &) = delete;
 
 public:
   // Create an XMM binary-op instruction like addss or addps.
   static InstX8632BinopXmm *create(Cfg *Func, Variable *Dest, Operand *Source) {
     return new (Func->allocate<InstX8632BinopXmm>())
@@ skipping 232 matching lines @@
 typedef InstX8632UnaryopXmm<InstX8632::Movd> InstX8632Movd;
 typedef InstX8632UnaryopXmm<InstX8632::Sqrtss> InstX8632Sqrtss;
 // Move/assignment instruction - wrapper for mov/movss/movsd.
 typedef InstX8632Movlike<InstX8632::Mov> InstX8632Mov;
 // Move packed - copy 128 bit values between XMM registers, or mem128
 // and XMM registers.
 typedef InstX8632Movlike<InstX8632::Movp> InstX8632Movp;
 // Movq - copy between XMM registers, or mem64 and XMM registers.
 typedef InstX8632Movlike<InstX8632::Movq> InstX8632Movq;
 typedef InstX8632BinopGPR<InstX8632::Add> InstX8632Add;
+typedef InstX8632BinopRMW<InstX8632::AddRMW> InstX8632AddRMW;
 typedef InstX8632BinopXmm<InstX8632::Addps, true> InstX8632Addps;
 typedef InstX8632BinopGPR<InstX8632::Adc> InstX8632Adc;
 typedef InstX8632BinopXmm<InstX8632::Addss, false> InstX8632Addss;
 typedef InstX8632BinopXmm<InstX8632::Padd, true> InstX8632Padd;
 typedef InstX8632BinopGPR<InstX8632::Sub> InstX8632Sub;
 typedef InstX8632BinopXmm<InstX8632::Subps, true> InstX8632Subps;
 typedef InstX8632BinopXmm<InstX8632::Subss, false> InstX8632Subss;
 typedef InstX8632BinopGPR<InstX8632::Sbb> InstX8632Sbb;
 typedef InstX8632BinopXmm<InstX8632::Psub, true> InstX8632Psub;
 typedef InstX8632BinopGPR<InstX8632::And> InstX8632And;
@@ skipping 675 matching lines @@
 template <> void InstX8632Pinsr::emitIAS(const Cfg *Func) const;
 template <> void InstX8632Movsx::emitIAS(const Cfg *Func) const;
 template <> void InstX8632Movzx::emitIAS(const Cfg *Func) const;
 template <> void InstX8632Pmull::emitIAS(const Cfg *Func) const;
 template <> void InstX8632Pshufd::emitIAS(const Cfg *Func) const;
 template <> void InstX8632Shufps::emitIAS(const Cfg *Func) const;
 
 } // end of namespace Ice
 
 #endif // SUBZERO_SRC_ICEINSTX8632_H