Subzero: Transform suitable Load/Arith/Store sequences into RMW ops.

src/IceTargetLowering.cpp

 //===- subzero/src/IceTargetLowering.cpp - Basic lowering implementation --===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 //
 // This file implements the skeleton of the TargetLowering class,
@@ skipping 112 matching lines @@
 // The lowering method may look ahead in the instruction stream as
 // desired, and lower additional instructions in conjunction with the
 // current one, for example fusing a compare and branch.  If it does,
 // it should advance Context.Cur to point to the next non-deleted
 // instruction to process, and it should delete any additional
 // instructions it consumes.
 void TargetLowering::lower() {
   assert(!Context.atEnd());
   Inst *Inst = Context.getCur();
   Inst->deleteIfDead();
-  if (!Inst->isDeleted()) {
+  if (!Inst->isDeleted() && !llvm::isa<InstFakeDef>(Inst) &&
+      !llvm::isa<InstFakeUse>(Inst)) {
     // Mark the current instruction as deleted before lowering,
     // otherwise the Dest variable will likely get marked as non-SSA.
-    // See Variable::setDefinition().
+    // See Variable::setDefinition().  However, just pass-through
+    // FakeDef and FakeUse instructions that might have been inserted
+    // prior to lowering.
     Inst->setDeleted();
     switch (Inst->getKind()) {
     case Inst::Alloca:
       lowerAlloca(llvm::cast<InstAlloca>(Inst));
       break;
     case Inst::Arithmetic:
       lowerArithmetic(llvm::cast<InstArithmetic>(Inst));
       break;
     case Inst::Assign:
       lowerAssign(llvm::cast<InstAssign>(Inst));
@@ skipping 40 matching lines @@
       break;
     case Inst::Store:
       lowerStore(llvm::cast<InstStore>(Inst));
       break;
     case Inst::Switch:
       lowerSwitch(llvm::cast<InstSwitch>(Inst));
       break;
     case Inst::Unreachable:
       lowerUnreachable(llvm::cast<InstUnreachable>(Inst));
       break;
-    case Inst::BundleLock:
-    case Inst::BundleUnlock:
-    case Inst::FakeDef:
-    case Inst::FakeUse:
-    case Inst::FakeKill:
-    case Inst::Target:
-      // These are all Target instruction types and shouldn't be
-      // encountered at this stage.
-      Func->setError("Can't lower unsupported instruction type");
+    default:
+      lowerOther(Inst);
       break;
     }
 
     postLower();
   }
 
   Context.advanceCur();
   Context.advanceNext();
 }
 
+void TargetLowering::lowerOther(const Inst *Instr) {
+  (void)Instr;
+  Func->setError("Can't lower unsupported instruction type");
+}
+
 // Drives register allocation, allowing all physical registers (except
 // perhaps for the frame pointer) to be allocated.  This set of
 // registers could potentially be parameterized if we want to restrict
 // registers e.g. for performance testing.
 void TargetLowering::regAlloc(RegAllocKind Kind) {
   TimerMarker T(TimerStack::TT_regAlloc, Func);
   LinearScan LinearScan(Func);
   RegSetMask RegInclude = RegSet_None;
   RegSetMask RegExclude = RegSet_None;
   RegInclude |= RegSet_CallerSave;
@@ skipping 310 matching lines @@
   if (Target == Target_##X)                                                    \
     return TargetHeader##X::create(Ctx);
 #include "llvm/Config/SZTargets.def"
 
   llvm::report_fatal_error("Unsupported target header lowering");
 }
 
 TargetHeaderLowering::~TargetHeaderLowering() {}
 
 } // end of namespace Ice