Subzero: Transform suitable Load/Arith/Store sequences into RMW ops.

src/IceInstX8632.cpp

 //===- subzero/src/IceInstX8632.cpp - X86-32 instruction implementation ---===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 //
 // This file implements the InstX8632 and OperandX8632 classes,
@@ skipping 93 matching lines @@
     Vars = Func->allocateArrayOf<Variable *>(NumVars);
     SizeT I = 0;
     if (Base)
       Vars[I++] = Base;
     if (Index)
       Vars[I++] = Index;
     assert(I == NumVars);
   }
 }
 
+InstX8632FakeRMW::InstX8632FakeRMW(Cfg *Func, Operand *Data, Operand *Addr,
+                                   InstArithmetic::OpKind Op, Variable *Beacon)
+    : InstX8632(Func, InstX8632::FakeRMW, 3, nullptr), Op(Op) {
+  addSource(Data);
+  addSource(Addr);
+  addSource(Beacon);
+}
+
 InstX8632AdjustStack::InstX8632AdjustStack(Cfg *Func, SizeT Amount,
                                            Variable *Esp)
     : InstX8632(Func, InstX8632::Adjuststack, 1, Esp), Amount(Amount) {
   addSource(Esp);
 }
 
 InstX8632Mul::InstX8632Mul(Cfg *Func, Variable *Dest, Variable *Source1,
                            Operand *Source2)
     : InstX8632(Func, InstX8632::Mul, 2, Dest) {
   addSource(Source1);
@@ skipping 239 matching lines @@
 // ======================== Dump routines ======================== //
 
 void InstX8632::dump(const Cfg *Func) const {
   if (!ALLOW_DUMP)
     return;
   Ostream &Str = Func->getContext()->getStrDump();
   Str << "[X8632] ";
   Inst::dump(Func);
 }
 
+void InstX8632FakeRMW::dump(const Cfg *Func) const {
+  if (!ALLOW_DUMP)
+    return;
+  Ostream &Str = Func->getContext()->getStrDump();
+  Type Ty = getData()->getType();
+  Str << "rmw " << InstArithmetic::getOpName(getOp()) << " " << Ty << " *";
+  getAddr()->dump(Func);
+  Str << ", ";
+  getData()->dump(Func);

[jvoung (off chromium), 2015/06/16 17:59:21]

Would it be helpful for this to dump the beacon too?

[Jim Stichnoth, 2015/06/17 00:15:40]

Done.

+}
+
 void InstX8632Label::emit(const Cfg *Func) const {
   if (!ALLOW_DUMP)
     return;
   Ostream &Str = Func->getContext()->getStrEmit();
   Str << getName(Func) << ":";
 }
 
 void InstX8632Label::emitIAS(const Cfg *Func) const {
   X8632::AssemblerX8632 *Asm = Func->getAssembler<X8632::AssemblerX8632>();
   Asm->BindLocalLabel(Number);
@@ skipping 199 matching lines @@
 // The ShiftHack parameter is used to emit "cl" instead of "ecx" for
 // shift instructions, in order to be syntactically valid.  The
 // Opcode parameter needs to be char* and not IceString because of
 // template issues.
 void InstX8632::emitTwoAddress(const char *Opcode, const Inst *Inst,
                                const Cfg *Func, bool ShiftHack) {
   if (!ALLOW_DUMP)
     return;
   Ostream &Str = Func->getContext()->getStrEmit();
   assert(Inst->getSrcSize() == 2);
-  Variable *Dest = Inst->getDest();
+  Operand *Dest = Inst->getDest();
+  if (Dest == nullptr)
+    Dest = Inst->getSrc(0);
   assert(Dest == Inst->getSrc(0));
   Operand *Src1 = Inst->getSrc(1);
   Str << "\t" << Opcode << InstX8632::getWidthString(Dest->getType()) << "\t";
   const auto ShiftReg = llvm::dyn_cast<Variable>(Src1);
   if (ShiftHack && ShiftReg && ShiftReg->getRegNum() == RegX8632::Reg_ecx)
     Str << "%cl";
   else
     Src1->emit(Func);
   Str << ", ";
   Dest->emit(Func);
@@ skipping 301 matching lines @@
 template <> const char *InstX8632Movsx::Opcode = "movs";
 template <> const char *InstX8632Movzx::Opcode = "movz";
 template <> const char *InstX8632Sqrtss::Opcode = "sqrtss";
 template <> const char *InstX8632Cbwdq::Opcode = "cbw/cwd/cdq";
 // Mov-like ops
 template <> const char *InstX8632Mov::Opcode = "mov";
 template <> const char *InstX8632Movp::Opcode = "movups";
 template <> const char *InstX8632Movq::Opcode = "movq";
 // Binary ops
 template <> const char *InstX8632Add::Opcode = "add";
+template <> const char *InstX8632AddRMW::Opcode = "add";
 template <> const char *InstX8632Addps::Opcode = "addps";
 template <> const char *InstX8632Adc::Opcode = "adc";
 template <> const char *InstX8632Addss::Opcode = "addss";
 template <> const char *InstX8632Padd::Opcode = "padd";
 template <> const char *InstX8632Sub::Opcode = "sub";
 template <> const char *InstX8632Subps::Opcode = "subps";
 template <> const char *InstX8632Subss::Opcode = "subss";
 template <> const char *InstX8632Sbb::Opcode = "sbb";
 template <> const char *InstX8632Psub::Opcode = "psub";
 template <> const char *InstX8632And::Opcode = "and";
@@ skipping 63 matching lines @@
 template <>
 const X8632::AssemblerX8632::XmmEmitterRegOp InstX8632Sqrtss::Emitter = {
     &X8632::AssemblerX8632::sqrtss, &X8632::AssemblerX8632::sqrtss};
 
 // Binary GPR ops
 template <>
 const X8632::AssemblerX8632::GPREmitterRegOp InstX8632Add::Emitter = {
     &X8632::AssemblerX8632::add, &X8632::AssemblerX8632::add,
     &X8632::AssemblerX8632::add};
 template <>
+const X8632::AssemblerX8632::GPREmitterAddrOp InstX8632AddRMW::Emitter = {
+    &X8632::AssemblerX8632::add, &X8632::AssemblerX8632::add};
+template <>
 const X8632::AssemblerX8632::GPREmitterRegOp InstX8632Adc::Emitter = {
     &X8632::AssemblerX8632::adc, &X8632::AssemblerX8632::adc,
     &X8632::AssemblerX8632::adc};
 template <>
 const X8632::AssemblerX8632::GPREmitterRegOp InstX8632And::Emitter = {
     &X8632::AssemblerX8632::And, &X8632::AssemblerX8632::And,
     &X8632::AssemblerX8632::And};
 template <>
 const X8632::AssemblerX8632::GPREmitterRegOp InstX8632Or::Emitter = {
     &X8632::AssemblerX8632::Or, &X8632::AssemblerX8632::Or,
@@ skipping 1995 matching lines @@
   }
   Str << "(";
   if (Func)
     Var->dump(Func);
   else
     Var->dump(Str);
   Str << ")";
 }
 
 } // end of namespace Ice