subclassed MCAsmStreamer

lib/Target/X86/MCTargetDesc/X86MCNaCl.cpp

 //=== X86MCNaCl.cpp - Expansion of NaCl pseudo-instructions      --*- C++ -*-=//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 //
 //===----------------------------------------------------------------------===//
@@ skipping 463 matching lines @@
 //   consistent during recursive calls.
 //
 //   We need global state to keep track of the explicit prefix (PREFIX_*)
 //   instructions. Unfortunately, the assembly parser prefers to generate
 //   these instead of combined instructions. At this time, having only
 //   one explicit prefix is supported.
 bool CustomExpandInstNaClX86(const llvm::MCSubtargetInfo &STI,
                              const MCInst &Inst, MCStreamer &Out,
                              X86MCNaClSFIState &State) {
   // If we are emitting to .s, only sandbox pseudos not supported by gas.
+
   if (Out.hasRawTextSupport()) {
     if (!(Inst.getOpcode() == X86::NACL_ANDSPi8 ||
-          Inst.getOpcode() == X86::NACL_ANDSPi32))
+          Inst.getOpcode() == X86::NACL_ANDSPi32 ||
+          Inst.getOpcode() == X86::RETL))
       return false;
   }
+
   // If we make a call to EmitInstruction, we will be called recursively. In
   // this case we just want the raw instruction to be emitted instead of
   // handling the insruction here.
   if (State.EmitRaw == true && !State.PrefixPass) {
     return false;
   }
   EmitRawState E(State);
   unsigned Opc = Inst.getOpcode();
   DEBUG(dbgs() << "CustomExpandInstNaClX86("; Inst.dump(); dbgs() << ")\n");
   switch (Opc) {
@@ skipping 30 matching lines @@
     return true;
   case X86::NACL_JMP32r:
     assert(State.PrefixSaved == 0);
     EmitIndirectBranch(STI, Inst.getOperand(0), false, false, Out);
     return true;
   case X86::NACL_JMP64r:
   case X86::NACL_JMP64z:
     assert(State.PrefixSaved == 0);
     EmitIndirectBranch(STI, Inst.getOperand(0), true, false, Out);
     return true;
+  case X86::RETL:
   case X86::NACL_RET32:
     assert(State.PrefixSaved == 0);
     EmitRet(STI, NULL, false, Out);
     return true;
   case X86::NACL_RET64:
     assert(State.PrefixSaved == 0);
     EmitRet(STI, NULL, true, Out);
     return true;
   case X86::NACL_RETI32:
     assert(State.PrefixSaved == 0);
@@ skipping 276 matching lines @@
 
 unsigned DemoteRegTo32_(unsigned RegIn) {
   if (RegIn == 0)
     return 0;
   unsigned RegOut = getX86SubSuperRegister_(RegIn, MVT::i32, false);
   assert(RegOut != 0);
   return RegOut;
 }
 } //namespace
 // @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@