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Side by Side Diff: src/IceTargetLoweringX8632.cpp

Issue 1179313004: Fix a bug that would cause subzero to fail when --threads=0. (Closed) Base URL: https://chromium.googlesource.com/native_client/pnacl-subzero.git@master
Patch Set: Addresses codereview comments. Created 5 years, 6 months ago
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1 //===- subzero/src/IceTargetLoweringX8632.cpp - x86-32 lowering -----------===// 1 //===- subzero/src/IceTargetLoweringX8632.cpp - x86-32 lowering -----------===//
2 // 2 //
3 // The Subzero Code Generator 3 // The Subzero Code Generator
4 // 4 //
5 // This file is distributed under the University of Illinois Open Source 5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details. 6 // License. See LICENSE.TXT for details.
7 // 7 //
8 //===----------------------------------------------------------------------===// 8 //===----------------------------------------------------------------------===//
9 // 9 //
10 // This file implements the TargetLoweringX8632 class, which 10 // This file implements the TargetLoweringX8632 class, which
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3289 Context.insert( 3289 Context.insert(
3290 InstFakeUse::create(Func, Context.getLastInserted()->getDest())); 3290 InstFakeUse::create(Func, Context.getLastInserted()->getDest()));
3291 return; 3291 return;
3292 } 3292 }
3293 case Intrinsics::AtomicRMW: 3293 case Intrinsics::AtomicRMW:
3294 if (!Intrinsics::isMemoryOrderValid( 3294 if (!Intrinsics::isMemoryOrderValid(
3295 ID, getConstantMemoryOrder(Instr->getArg(3)))) { 3295 ID, getConstantMemoryOrder(Instr->getArg(3)))) {
3296 Func->setError("Unexpected memory ordering for AtomicRMW"); 3296 Func->setError("Unexpected memory ordering for AtomicRMW");
3297 return; 3297 return;
3298 } 3298 }
3299 lowerAtomicRMW( 3299 lowerAtomicRMW(Instr->getDest(),
3300 Instr->getDest(), 3300 static_cast<uint32_t>(llvm::cast<ConstantInteger32>(
3301 static_cast<uint32_t>( 3301 Instr->getArg(0))->getValue()),
3302 llvm::cast<ConstantInteger32>(Instr->getArg(0))->getValue()), 3302 Instr->getArg(1), Instr->getArg(2));
3303 Instr->getArg(1), Instr->getArg(2));
3304 return; 3303 return;
3305 case Intrinsics::AtomicStore: { 3304 case Intrinsics::AtomicStore: {
3306 if (!Intrinsics::isMemoryOrderValid( 3305 if (!Intrinsics::isMemoryOrderValid(
3307 ID, getConstantMemoryOrder(Instr->getArg(2)))) { 3306 ID, getConstantMemoryOrder(Instr->getArg(2)))) {
3308 Func->setError("Unexpected memory ordering for AtomicStore"); 3307 Func->setError("Unexpected memory ordering for AtomicStore");
3309 return; 3308 return;
3310 } 3309 }
3311 // We require the memory address to be naturally aligned. 3310 // We require the memory address to be naturally aligned.
3312 // Given that is the case, then normal stores are atomic. 3311 // Given that is the case, then normal stores are atomic.
3313 // Add a fence after the store to make it visible. 3312 // Add a fence after the store to make it visible.
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5014 C->emitPoolLabel(Str); 5013 C->emitPoolLabel(Str);
5015 } 5014 }
5016 5015
5017 void TargetX8632::emit(const ConstantUndef *) const { 5016 void TargetX8632::emit(const ConstantUndef *) const {
5018 llvm::report_fatal_error("undef value encountered by emitter."); 5017 llvm::report_fatal_error("undef value encountered by emitter.");
5019 } 5018 }
5020 5019
5021 TargetDataX8632::TargetDataX8632(GlobalContext *Ctx) 5020 TargetDataX8632::TargetDataX8632(GlobalContext *Ctx)
5022 : TargetDataLowering(Ctx) {} 5021 : TargetDataLowering(Ctx) {}
5023 5022
5024 void TargetDataX8632::lowerGlobals( 5023 void TargetDataX8632::lowerGlobals(const VariableDeclarationList &Vars,
5025 std::unique_ptr<VariableDeclarationList> Vars) { 5024 const IceString &SectionSuffix) {
5026 switch (Ctx->getFlags().getOutFileType()) { 5025 switch (Ctx->getFlags().getOutFileType()) {
5027 case FT_Elf: { 5026 case FT_Elf: {
5028 ELFObjectWriter *Writer = Ctx->getObjectWriter(); 5027 ELFObjectWriter *Writer = Ctx->getObjectWriter();
5029 Writer->writeDataSection(*Vars, llvm::ELF::R_386_32); 5028 Writer->writeDataSection(Vars, llvm::ELF::R_386_32, SectionSuffix);
5030 } break; 5029 } break;
5031 case FT_Asm: 5030 case FT_Asm:
5032 case FT_Iasm: { 5031 case FT_Iasm: {
5033 const IceString &TranslateOnly = Ctx->getFlags().getTranslateOnly(); 5032 const IceString &TranslateOnly = Ctx->getFlags().getTranslateOnly();
5034 OstreamLocker L(Ctx); 5033 OstreamLocker L(Ctx);
5035 for (const VariableDeclaration *Var : *Vars) { 5034 for (const VariableDeclaration *Var : Vars) {
5036 if (GlobalContext::matchSymbolName(Var->getName(), TranslateOnly)) { 5035 if (GlobalContext::matchSymbolName(Var->getName(), TranslateOnly)) {
5037 emitGlobal(*Var); 5036 emitGlobal(*Var, SectionSuffix);
5038 } 5037 }
5039 } 5038 }
5040 } break; 5039 } break;
5041 } 5040 }
5042 } 5041 }
5043 5042
5044 template <typename T> struct PoolTypeConverter {}; 5043 template <typename T> struct PoolTypeConverter {};
5045 5044
5046 template <> struct PoolTypeConverter<float> { 5045 template <> struct PoolTypeConverter<float> {
5047 typedef uint32_t PrimitiveIntType; 5046 typedef uint32_t PrimitiveIntType;
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5115 emitConstantPool<PoolTypeConverter<float>>(Ctx); 5114 emitConstantPool<PoolTypeConverter<float>>(Ctx);
5116 emitConstantPool<PoolTypeConverter<double>>(Ctx); 5115 emitConstantPool<PoolTypeConverter<double>>(Ctx);
5117 } break; 5116 } break;
5118 } 5117 }
5119 } 5118 }
5120 5119
5121 TargetHeaderX8632::TargetHeaderX8632(GlobalContext *Ctx) 5120 TargetHeaderX8632::TargetHeaderX8632(GlobalContext *Ctx)
5122 : TargetHeaderLowering(Ctx) {} 5121 : TargetHeaderLowering(Ctx) {}
5123 5122
5124 } // end of namespace Ice 5123 } // end of namespace Ice
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