MIPS: Adapt Danno's Track Allocation Info idea to fast literals.

src/mips/macro-assembler-mips.cc

 // Copyright 2012 the V8 project authors. All rights reserved.
 // Redistribution and use in source and binary forms, with or without
 // modification, are permitted provided that the following conditions are
 // met:
 //
 //     * Redistributions of source code must retain the above copyright
 //       notice, this list of conditions and the following disclaimer.
 //     * Redistributions in binary form must reproduce the above
 //       copyright notice, this list of conditions and the following
 //       disclaimer in the documentation and/or other materials provided
@@ skipping 5431 matching lines @@
   Branch(&done);
 
   // In 0-255 range, round and truncate.
   bind(&in_bounds);
   cvt_w_d(temp_double_reg, input_reg);
   mfc1(result_reg, temp_double_reg);
   bind(&done);
 }
 
 
+void MacroAssembler::TestJSArrayForAllocationSiteInfo(
+    Register receiver_reg,
+    Register scratch_reg,
+    Label* allocation_info_present) {
+  Label no_info_available;
+  ExternalReference new_space_start =
+      ExternalReference::new_space_start(isolate());
+  ExternalReference new_space_allocation_top =
+      ExternalReference::new_space_allocation_top_address(isolate());
+  lw(scratch_reg, FieldMemOperand(receiver_reg,
+                                  JSArray::kSize + AllocationSiteInfo::kSize));
+  Branch(&no_info_available, lt, scratch_reg, Operand(new_space_start));
+  Branch(&no_info_available, hs, scratch_reg,
+      Operand(new_space_allocation_top));
+  lw(scratch_reg, MemOperand(scratch_reg));
+  Branch(allocation_info_present, eq, scratch_reg,
+      Operand(Handle<Map>(isolate()->heap()->allocation_site_info_map())));
+  bind(&no_info_available);
+}
+
+
 bool AreAliased(Register r1, Register r2, Register r3, Register r4) {
   if (r1.is(r2)) return true;
   if (r1.is(r3)) return true;
   if (r1.is(r4)) return true;
   if (r2.is(r3)) return true;
   if (r2.is(r4)) return true;
   if (r3.is(r4)) return true;
   return false;
 }
 
@@ skipping 48 matching lines @@
        opcode == BGTZL);
   opcode = (cond == eq) ? BEQ : BNE;
   instr = (instr & ~kOpcodeMask) | opcode;
   masm_.emit(instr);
 }
 
 
 } }  // namespace v8::internal
 
 #endif  // V8_TARGET_ARCH_MIPS